Searched defs:PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3282 #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_BB (0x1f<<19) // Along with the scale field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface. macro
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