Searched defs:PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_REJECT_EVENT_E5 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h4353 #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_REJECT_EVENT_E5 (0x1<<7) // EQ reject event. Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ master phase again. macro
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