Searched defs:PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_E5 (Results 1 - 1 of 1) sorted by relevance
| /freebsd-11-stable/sys/dev/qlnx/qlnxe/ | ||
| H A D | reg_addr.h | 3061 #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_E5 (0x7<<3) // Margin type for this lane. macro [all...] |
Completed in 2191 milliseconds