Searched defs:PCIEIP_REG_PCIEEP_DEV_CAP_EL1AL_E5 (Results 1 - 1 of 1) sorted by relevance
| /freebsd-11-stable/sys/dev/qlnx/qlnxe/ | ||
| H A D | reg_addr.h | 712 #define PCIEIP_REG_PCIEEP_DEV_CAP_EL1AL_E5 (0x7<<9) // Endpoint L1 acceptable latency, writable through PEM()_CFG_WR. macro [all...] |
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