Searched defs:PCIEIP_REG_PCIEEP_ACK_FREQ_L1EL_E5 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h5288 #define PCIEIP_REG_PCIEEP_ACK_FREQ_L1EL_E5 (0x7<<27) // L1 entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 4 ms. 0x3 = 8 ms. 0x4 = 16 ms. 0x5 = 32 ms. 0x6 or 0x7 = 64 ms. macro
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