Searched defs:PCIEIP_REG_LTR_CAP_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2460 #define PCIEIP_REG_LTR_CAP_BB 0x0001b0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining LTR_ENABLED in version.v and setting bit 5 of EXT_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device. macro
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