Searched defs:PCIEIP_REG_LINK_STATUS_CONTROL_2_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1406 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_BB 0x0000dcUL //Access:RW DataWidth:0x20 // This register will be Read only by default, and will read all 0's to allow compliance with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bit in the register space to 0. macro
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