Searched defs:PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1117 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky. macro
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