Searched defs:PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1270 #define PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT_BB (0x7<<12) // L0s Exit Latency. These bits are programmable through register space. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or not, the value reflected by these bits is one of the following. macro
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