Searched defs:PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h841 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R macro
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