Searched defs:PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3608 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0_BB (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane0 macro
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