Searched defs:PCIEIP_REG_BAR1_REG_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h324 #define PCIEIP_REG_BAR1_REG_K2 0x000014UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". macro
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