Searched defs:PCIEIP_REG_ARI_CONTROL_REGISTER_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2516 #define PCIEIP_REG_ARI_CONTROL_REGISTER_BB 0x0001bcUL //Access:R DataWidth:0x20 // The RW value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes). macro
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