Searched defs:PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT (Results 1 - 13 of 13) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6965 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 macro
H A Dgfx_7_2_sh_mask.h5760 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 macro
H A Dgfx_8_0_sh_mask.h6548 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 macro
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H A Dgfx_8_1_sh_mask.h7082 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_sh_mask.h18126 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_9_1_sh_mask.h18249 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_9_0_sh_mask.h16940 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_9_4_2_sh_mask.h10373 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_9_4_3_sh_mask.h20252 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_11_0_3_sh_mask.h24475 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_10_1_0_sh_mask.h24437 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_11_0_0_sh_mask.h22145 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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H A Dgc_10_3_0_sh_mask.h22626 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT macro
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