| /freebsd-10.0-release/contrib/llvm/include/llvm/Analysis/ |
| H A D | ConstantsScanner.h | 28 unsigned OpIdx; // Operand index member in class:llvm::constant_iterator
[all...] |
| /freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 48 int OpIdx; member in struct:llvm::PhysRegSUOper
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| /freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 48 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, argument
140 getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, int MemSize) const argument
218 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
251 getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
286 getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
296 getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
307 getLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
320 getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
359 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 130 unsigned OpIdx; local
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| H A D | CodeGenInstruction.cpp | 134 unsigned OpIdx; local
170 unsigned OpIdx = getOperandNamed(OpName); local
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 385 unsigned OpIdx = 0; local
450 unsigned OpIdx = 0; local
502 unsigned OpIdx = 0; local
585 unsigned OpIdx = 0; local
945 unsigned OpIdx = 0; local
976 unsigned OpIdx = 0; local
1008 unsigned OpIdx = 0; local
[all...] |
| H A D | ARMCodeEmitter.cpp | 926 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1022 unsigned OpIdx = 0; local
1124 unsigned OpIdx = 0; local
1195 unsigned OpIdx = 0; local
1280 unsigned OpIdx = 0; local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 2394 unsigned OpIdx = Commute ? 2 : 1; local
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| /freebsd-10.0-release/contrib/llvm/include/llvm/Support/ |
| H A D | PatternMatch.h | 1019 Argument_match(unsigned OpIdx, const Opnd_t &V) : OpI(OpIdx), Val(V) { } argument
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| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineLICM.cpp | 779 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
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| H A D | MachineInstr.cpp | 919 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, argument
1695 unsigned OpIdx = DeadOps.back(); local
1760 unsigned OpIdx = DeadOps.back(); local
[all...] |
| H A D | RegisterCoalescer.cpp | 658 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); local
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| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 169 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const argument
462 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups) argument
499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
600 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
614 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
626 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
649 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
689 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
708 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
720 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &) const argument
734 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
783 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
814 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
854 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
879 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
938 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
971 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
985 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1007 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1018 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1037 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1073 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1088 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1102 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1112 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1150 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1197 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 15902 int OpIdx = -1; local
4782 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument
|