| /freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 50 class MachineInstr : public ilist_node<MachineInstr> { class in namespace:llvm
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| H A D | MachineInstrBuilder.h | [all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 37 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
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| H A D | Thumb1RegisterInfo.cpp | 90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
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| H A D | ARMFrameLowering.cpp | 107 emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
122 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
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| H A D | ARMCodeEmitter.cpp | 172 VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) const argument
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 538 CanPromoteToNewValueStore( MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument
719 CanPromoteToNewValue( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII) argument
748 CanPromoteToDotNew( MachineInstr *MI, SUnit *PacketSU, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC ) argument
805 RestrictingDepExistInPacket(MachineInstr* MI, unsigned DepReg, std::map <MachineInstr*, SUnit*> MIToSUnit) argument
863 ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) argument
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| /freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 532 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, function in class:MachineInstr
550 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) function in class:MachineInstr
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