Searched defs:IR (Results 1 - 25 of 36) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/
H A DPipeline.cpp60 InstRef IR; local
/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; local
46 Error MicroOpQueueStage::execute(InstRef &IR) { argument
H A DInstructionTables.cpp22 Error InstructionTables::execute(InstRef &IR) { argument
H A DRetireStage.cpp49 llvm::Error RetireStage::execute(InstRef &IR) { argument
H A DExecuteStage.cpp53 Error ExecuteStage::issueInstruction(InstRef &IR) { argument
81 InstRef IR = HWS.select(); local
161 verifyInstructionEliminated(const InstRef &IR) argument
173 handleInstructionEliminated(InstRef &IR) argument
186 execute(InstRef &IR) argument
252 notifyInstructionIssued( const InstRef &IR, MutableArrayRef<std::pair<ResourceRef, ResourceCycles>> Used) const argument
272 notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const argument
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H A DDispatchStage.cpp38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, argument
78 dispatch(InstRef IR) argument
176 execute(InstRef &IR) argument
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H A DInOrderIssueStage.cpp55 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) { argument
64 static unsigned findLastWriteBackCycle(const InstRef &IR) { argument
77 static unsigned findFirstWriteBackCycle(const InstRef &IR) { argument
92 checkRegisterHazard(const RegisterFile &PRF, const MCSchedModel &SM, const MCSubtargetInfo &STI, const InstRef &IR) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRetireControlUnit.cpp43 unsigned RetireControlUnit::dispatch(const InstRef &IR) { argument
H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { argument
204 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { argument
213 void LSUnitBase::onInstructionRetired(const InstRef &IR) { argument
232 onInstructionExecuted(const InstRef &IR) argument
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H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { argument
70 issueInstructionImpl( InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources) argument
99 issueInstruction( InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources, SmallVectorImpl<InstRef> &PendingInstructions, SmallVectorImpl<InstRef> &ReadyInstructions) argument
124 InstRef &IR = *I; local
160 InstRef &IR = *I; local
195 InstRef &IR = ReadySet[I]; local
221 InstRef &IR = *I; local
300 dispatch(InstRef &IR) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DPassManagerImpl.h36 AnalysisManager<IRUnitT, ExtraArgTs...>::clear(IRUnitT &IR, argument
54 getResultImpl( AnalysisKey *ID, IRUnitT &IR, ExtraArgTs... ExtraArgs) argument
89 invalidate( IRUnitT &IR, const PreservedAnalyses &PA) argument
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H A DPassInstrumentation.h241 runAfterPass(const PassT &Pass, const IRUnitT &IR, const PreservedAnalyses &PA) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DRetireControlUnit.h52 InstRef IR; member in struct:llvm::mca::RetireControlUnit::RUToken
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DStage.h70 Error moveToTheNextStage(InstRef &IR) { argument
/netbsd-current/external/apache2/llvm/dist/clang/tools/clang-fuzzer/handle-llvm/
H A Dhandle_llvm.cpp96 static std::string OptLLVM(const std::string &IR, CodeGenOpt::Level OLvl) { argument
154 CreateAndRunJITFunc(const std::string &IR, CodeGenOpt::Level OLvl) argument
212 HandleLLVM(const std::string &IR, const std::vector<const char *> &ExtraArgs) argument
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/netbsd-current/sys/arch/alpha/pci/
H A Dpci_1000a.c189 #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0) macro
H A Dpci_1000.c171 #define IR() bus_space_read_2(another_mystery_icu_iot, \ macro
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Passes/
H A DStandardInstrumentations.cpp192 unwrapModule(Any IR, bool Force = false) argument
260 getIRName(Any IR) argument
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/netbsd-current/external/apache2/llvm/dist/clang/lib/AST/
H A DComputeDependence.cpp422 OMPIteratorExpr::IteratorRange IR = E->getIteratorRange(I); local
/netbsd-current/external/gpl3/gdb.old/dist/sim/mips/
H A Dcp1.h61 #define IR 0 /* I: Inexact Result */ macro
/netbsd-current/external/gpl3/gdb/dist/sim/mips/
H A Dcp1.h67 #define IR 0 /* I: Inexact Result */ macro
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DHWEventListener.h59 const InstRef &IR; member in class:llvm::mca::HWInstructionEvent
65 HWInstructionIssuedEvent(const InstRef &IR, argument
74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, argument
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) argument
126 const InstRef &IR; member in class:llvm::mca::HWStallEvent
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Scalar/
H A DLoopPassManager.h358 runSinglePass( IRUnitT &IR, PassT &Pass, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &U, PassInstrumentation &PI) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
H A DInliner.cpp255 InlineResult IR = InlineFunction(CB, IFI, &AAR, InsertLifetime); local
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/netbsd-current/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp41 void TimelineView::onReservedBuffers(const InstRef &IR, argument

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