| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 283 bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/AsmParser/ |
| H A D | LLParser.cpp | 677 LocTy IDLoc = Lex.getLoc(); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/MC/MCParser/ |
| H A D | DarwinAsmParser.cpp | 763 bool DarwinAsmParser::parseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { argument
803 bool DarwinAsmParser::parseDirectiveSecureLogReset(StringRef, SMLoc IDLoc) { argument
585 parseDirectiveDumpOrLoad(StringRef Directive, SMLoc IDLoc) argument
830 SMLoc IDLoc = getLexer().getLoc(); local
915 SMLoc IDLoc = getLexer().getLoc(); local
[all...] |
| H A D | AsmParser.cpp | 1699 SMLoc IDLoc = ID.getLoc(); local
2656 SMLoc IDLoc = Lexer.getLoc(); local
5678 parseDirectiveMSEmit(SMLoc IDLoc, ParseStatementInfo &Info, size_t Len) argument
5695 parseDirectiveMSAlign(SMLoc IDLoc, ParseStatementInfo &Info) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 506 bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, argument
580 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, argument
130 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
175 emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
185 emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
190 emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
195 emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
205 emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
217 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
223 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
236 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
264 emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
275 emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
283 emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) argument
291 emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
297 emitStoreWithImmOffset( unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
334 emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg, int64_t Offset, unsigned TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
665 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
1173 emitDirectiveCpRestore( int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 1134 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 808 bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
1663 emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg, const MCExpr *Symbol, RISCVMCExpr::VariantKind VKHi, unsigned SecondOpcode, SMLoc IDLoc, MCStreamer &Out) argument
1691 emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1705 emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1731 emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1746 emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1760 emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out, bool HasTmpReg) argument
1792 processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands, MCStreamer &Out) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 1241 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 464 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { argument
508 auto IDLoc = Parser.getTok().getLoc(); local
548 matchOneInstruction(MCInst &MCI, SMLoc IDLoc, OperandVector &InstOperands, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
606 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
1270 OutOfRange(SMLoc IDLoc, long long Val, long long Max) argument
1281 processInstruction(MCInst &Inst, OperandVector const &Operands, SMLoc IDLoc) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 3104 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
3115 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, argument
3141 ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures, bool MatchingInlineAsm) argument
3199 MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
3405 MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 3894 bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc, argument
4495 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3440 validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands) argument
3523 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 10460 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, argument
11590 FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, SmallVectorImpl<NearMissMessage> &NearMissesOut, SMLoc IDLoc, OperandVector &Operands) argument
11744 ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc, OperandVector &Operands) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1856 processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2332 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI); local
2344 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, local
2357 tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2607 expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2647 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc, local
2670 loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2834 expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2848 expandLoadAddress(unsigned DstReg, unsigned BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
2879 loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3256 emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym) argument
3330 expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3346 expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3400 expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3454 MCOperand::createExpr(LoExpr), IDLoc, STI); local
3465 expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3538 expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3583 expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3649 expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) argument
3776 expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) argument
3834 expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
3863 expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4134 expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, const bool IsMips64, const bool Signed) argument
4305 expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4344 expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4396 expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4447 expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4502 expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4536 expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4592 expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4639 expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4746 expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4808 expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4871 expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
4933 expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5028 expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5044 expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5067 expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5109 expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5145 expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5163 expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad) argument
5211 expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5248 expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5274 expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5297 DstReg, SrcReg, SrcReg, IDLoc, STI); local
5464 expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5534 expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument
5733 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
[all...] |