Searched defs:ICmp (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp378 Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32); local
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTypePromotion.cpp968 auto *ICmp = cast<ICmpInst>(&I); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1376 assert(Bit < 64 && �); bool UseWReg = Bit < 32; unsigned NecessarySize = UseWReg ? 32 : 64; if (Size != NecessarySize) TestReg = moveScalarRegClass( TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass, MIB); static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX}, {AArch64::TBZW, AArch64::TBNZW}}; unsigned Opc = OpcTable[UseWReg][IsNegative]; auto TestBitMI = MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI); return &*TestBitMI; } bool AArch64InstructionSelector::tryOptAndIntoCompareBranch( MachineInstr &AndInst, bool Invert, MachineBasicBlock *DstMBB, MachineIRBuilder &MIB) const { assert(AndInst.getOpcode() == TargetOpcode::G_AND && �); auto MaybeBit = getConstantVRegValWithLookThrough( AndInst.getOperand(2).getReg(), *MIB.getMRI()); if (!MaybeBit) return false; int32_t Bit = MaybeBit->Value.exactLogBase2(); if (Bit < 0) return false; Register TestReg = AndInst.getOperand(1).getReg(); emitTestBit(TestReg, Bit, Invert, DstMBB, MIB); return true; } MachineInstr *AArch64InstructionSelector::emitCBZ(Register CompareReg, bool IsNegative, MachineBasicBlock *DestMBB, MachineIRBuilder &MIB) const { assert(ProduceNonFlagSettingCondBr && �); MachineRegisterInfo &MRI = *MIB.getMRI(); assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == AArch64::GPRRegBankID && �); auto Ty = MRI.getType(CompareReg); unsigned Width = Ty.getSizeInBits(); assert(!Ty.isVector() && �); assert(Width <= 64 && �); static const unsigned OpcTable[2][2] = {{AArch64::CBZW, AArch64::CBZX}, {AArch64::CBNZW, AArch64::CBNZX}}; unsigned Opc = OpcTable[IsNegative][Width == 64]; auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); constrainSelectedInstRegOperands(*BranchMI, TII, TRI, RBI); return &*BranchMI; } bool AArch64InstructionSelector::selectCompareBranchFedByFCmp( MachineInstr &I, MachineInstr &FCmp, MachineIRBuilder &MIB) const { assert(FCmp.getOpcode() == TargetOpcode::G_FCMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); auto Pred = (CmpInst::Predicate)FCmp.getOperand(1).getPredicate(); emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, Pred); AArch64CC::CondCode CC1, CC2; changeFCMPPredToAArch64CC(static_cast<CmpInst::Predicate>(Pred), CC1, CC2); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); if (CC2 != AArch64CC::AL) MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); I.eraseFromParent(); return true; } bool AArch64InstructionSelector::tryOptCompareBranchFedByICmp( MachineInstr &I, MachineInstr &ICmp, MachineIRBuilder &MIB) const { assert(ICmp.getOpcode() == TargetOpcode::G_ICMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); if (!ProduceNonFlagSettingCondBr) return false; MachineRegisterInfo &MRI = *MIB.getMRI(); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); auto Pred = static_cast<CmpInst::Predicate>(ICmp.getOperand(1).getPredicate()); Register LHS = ICmp.getOperand(2).getReg(); Register RHS = ICmp.getOperand(3).getReg(); auto VRegAndVal = getConstantVRegValWithLookThrough(RHS, MRI); MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); if (VRegAndVal && !AndInst) { int64_t C = VRegAndVal->Value.getSExtValue(); if (C == -1 && Pred == CmpInst::ICMP_SGT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, false, DestMBB, MIB); I.eraseFromParent(); return true; } if (C == 0 && Pred == CmpInst::ICMP_SLT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, true, DestMBB, MIB); I.eraseFromParent(); return true; } } if (ICmpInst::isEquality(Pred)) { if (!VRegAndVal) { std::swap(RHS, LHS); VRegAndVal = getConstantVRegValWithLookThrough(RHS, MRI); AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); } if (VRegAndVal && VRegAndVal->Value == 0) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1025 const auto *ICmp = cast<ICmpInst>(I); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
H A DControlHeightReduction.cpp1521 static bool negateICmpIfUsedByBranchOrSelectOnly(ICmpInst *ICmp, argument
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DIndVarSimplify.cpp701 ICmpInst *ICmp = dyn_cast<ICmpInst>(BI->getCondition()); local
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp195 bool SimplifyIndvar::makeIVComparisonInvariant(ICmpInst *ICmp, argument
265 eliminateIVComparison(ICmpInst *ICmp, Value *IVOperand) argument
364 ICmpInst *ICmp = new ICmpInst(Rem, ICmpInst::ICMP_EQ, N, D); local
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H A DScalarEvolutionExpander.cpp1741 Value *ICmp = Builder.CreateICmpSGT(LHS, RHS); local
1770 Value *ICmp = Builder.CreateICmpUGT(LHS, RHS); local
1799 Value *ICmp = Builder.CreateICmpSLT(LHS, RHS); local
1828 Value *ICmp = Builder.CreateICmpULT(LHS, RHS); local
/netbsd-current/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/
H A Dllvm.ml227 | ICmp Constructor in type:Opcode/t
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp4412 static Instruction *foldICmpWithZextOrSext(ICmpInst &ICmp, argument
4505 foldICmpWithCastOp(ICmpInst &ICmp) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
H A DAttributorAttributes.cpp4841 bool checkForNullPtrCompare(Attributor &A, ICmpInst *ICmp, argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5255 auto ICmp = MIRBuilder.buildICmp( local
5306 auto ICmp = MIRBuilder.buildICmp( local

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