Searched defs:DstRB (Results 1 - 4 of 4) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 574 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); local
599 const RegisterBank &DstRB = local
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| H A D | AArch64InstructionSelector.cpp | 1692 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
2045 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
2379 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
2900 emitExtractVectorElt( Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy, Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const argument
2990 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
3017 const RegisterBank &DstRB = local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 258 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); local
299 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 718 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
807 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
893 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); local
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