| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.h | 136 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter
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| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | LiveRangeCalc.cpp | 91 unsigned DefIdx; local
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| H A D | TargetSchedule.cpp | 152 unsigned DefIdx = 0; local
216 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local
[all...] |
| H A D | RegAllocFast.cpp | 735 unsigned DefIdx = 0; local
738 << DefIdx << ".\n"); local
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| H A D | TargetInstrInfo.cpp | 574 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
659 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
710 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument
[all...] |
| H A D | InlineSpiller.cpp | 888 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM, local
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| H A D | MachineLICM.cpp | 1009 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
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| H A D | MachineVerifier.cpp | 877 unsigned DefIdx; local
1073 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); local
[all...] |
| H A D | MachineInstr.cpp | 700 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local
963 unsigned DefIdx; local
1109 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument
[all...] |
| H A D | RegisterCoalescer.cpp | 599 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local
702 SlotIndex DefIdx = UseIdx.getRegSlot(); local
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| /freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 203 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument
224 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument
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| /freebsd-10.0-release/contrib/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 854 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2810 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
2851 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
2955 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3066 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3303 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
3394 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
3676 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4712 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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