Searched defs:DAG (Results 76 - 85 of 85) sorted by relevance

1234

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp47 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { argument
53 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { argument
759 isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument
815 getNegatedExpression( SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const argument
1152 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument
1192 SelectionDAG &DAG = CLI.DAG; local
1235 Op->print(errs(), &DAG); local
1656 LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool Sign) const argument
1767 LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) const argument
2137 extractF64Exponent(SDValue Hi, const SDLoc &SL, SelectionDAG &DAG) argument
2294 LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const argument
2399 LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2484 LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2584 LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
2774 isU24(SDValue Op, SelectionDAG &DAG) argument
2778 isI24(SDValue Op, SelectionDAG &DAG) argument
2787 SelectionDAG &DAG = DCI.DAG; local
2823 constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL) argument
2876 SelectionDAG &DAG = DCI.DAG; local
2933 SelectionDAG &DAG = DCI.DAG; local
2979 SelectionDAG &DAG = DCI.DAG; local
3028 SelectionDAG &DAG = DCI.DAG; local
3061 SelectionDAG &DAG = DCI.DAG; local
3159 SelectionDAG &DAG = DCI.DAG; local
3202 SelectionDAG &DAG = DCI.DAG; local
3288 getMul24(SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed) argument
3412 getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const argument
3480 SelectionDAG &DAG = DCI.DAG; local
3498 SelectionDAG &DAG = DCI.DAG; local
3574 SelectionDAG &DAG = DCI.DAG; local
3647 SelectionDAG &DAG = DCI.DAG; local
3857 SelectionDAG &DAG = DCI.DAG; local
3894 SelectionDAG &DAG = DCI.DAG; local
4100 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg) const argument
4136 loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const argument
4152 storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const argument
4166 loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const argument
4358 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument
4376 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument
4397 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
4540 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
4605 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
[all...]
H A DSIISelLowering.cpp866 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, argument
1609 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG, argument
1632 getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const argument
1639 convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, bool Signed, const ISD::InputArg *Arg) const argument
1670 lowerKernargMemParameter( SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, uint64_t Offset, Align Alignment, bool Signed, const ISD::InputArg *Arg) const argument
1713 lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, const SDLoc &SL, SDValue Chain, const ISD::InputArg &Arg) const argument
1762 getPreloadedValue(SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT, AMDGPUFunctionArgInfo::PreloadedValue PVID) const argument
2255 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2623 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn, SDValue ThisVal) const argument
2935 SelectionDAG &DAG = CLI.DAG; local
4386 isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const argument
4563 adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, const SDLoc &DL, SelectionDAG &DAG, bool Unpacked) argument
4604 adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG, ArrayRef<SDValue> Ops, bool IsIntrinsic) const argument
4641 lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, ArrayRef<SDValue> Ops) const argument
4676 lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
4711 lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
4741 lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
5087 getFPExtOrFPRound(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, EVT VT) const argument
5626 buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV, const SDLoc &DL, int64_t Offset, EVT PtrVT, unsigned GAFlags = SIInstrInfo::MO_NONE) argument
5732 copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const argument
5748 lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, MVT VT, unsigned Offset) const argument
5760 emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT) argument
5769 emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT) argument
5778 getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL, ArrayRef<SDValue> Elts) argument
5820 padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, SDValue Src, int ExtraElts) argument
5841 constructRetValue(SelectionDAG &DAG, MachineSDNode *Result, ArrayRef<EVT> ResultTypes, bool IsTexFail, bool Unpacked, bool IsD16, int DMaskPop, int NumVDataDwords, const SDLoc &DL) argument
5911 parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE, SDValue *LWE, bool &IsTexFail) argument
5929 packImage16bitOpsToDwords(SelectionDAG &DAG, SDValue Op, MVT PackVectorVT, SmallVectorImpl<SDValue> &PackedAddrs, unsigned DimIdx, unsigned EndIdx, unsigned NumGradients) argument
5958 lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, SelectionDAG &DAG, bool WithChain) const argument
6752 lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, unsigned NewOpcode) const argument
6780 lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, unsigned NewOpcode) const argument
7457 handleD16VData(SDValue VData, SelectionDAG &DAG, bool ImageStore) const argument
7862 setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, SDValue *Offsets, Align Alignment) const argument
7897 handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, ArrayRef<SDValue> Ops, MemSDNode *M) const argument
7916 handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, SDLoc DL, SDValue Ops[], MemSDNode *M) const argument
7932 getLoadExtOrTrunc(SelectionDAG &DAG, ISD::LoadExtType ExtType, SDValue Op, const SDLoc &SL, EVT VT) argument
7953 SelectionDAG &DAG = DCI.DAG; local
8300 getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue GlueChain, SDNodeFlags Flags) argument
8322 getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue C, SDValue GlueChain, SDNodeFlags Flags) argument
8400 getSPDenormModeValue(int SPDenormMode, SelectionDAG &DAG, const SDLoc &SL, const GCNSubtarget *ST) argument
8876 SelectionDAG &DAG = DCI.DAG; local
8971 getPermuteMask(SelectionDAG &DAG, SDValue V) argument
9202 SelectionDAG &DAG = DCI.DAG; local
9467 SelectionDAG &DAG = DCI.DAG; local
9504 isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth) const argument
9705 getCanonicalConstantFP( SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const argument
9738 SelectionDAG &DAG = DCI.DAG; local
9844 performIntMed3ImmCombine( SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1, bool Signed) const argument
9898 performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1) const argument
9953 SelectionDAG &DAG = DCI.DAG; local
10039 SelectionDAG &DAG = DCI.DAG; local
10133 SelectionDAG &DAG = DCI.DAG; local
10273 getFusedOpcode(const SelectionDAG &DAG, const SDNode *N0, const SDNode *N1) const argument
10337 getMad64_32(SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue N0, SDValue N1, SDValue N2, bool Signed) argument
10349 SelectionDAG &DAG = DCI.DAG; local
10428 SelectionDAG &DAG = DCI.DAG; local
10585 SelectionDAG &DAG = DCI.DAG; local
10660 SelectionDAG &DAG = DCI.DAG; local
10756 SelectionDAG &DAG = DCI.DAG; local
10904 SelectionDAG &DAG = DCI.DAG; local
11425 buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL, uint64_t Val) argument
11431 wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const argument
11466 buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const argument
12056 denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const argument
12082 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp51 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, argument
148 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, argument
292 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EV argument
302 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling) const argument
565 SelectionDAG &DAG = TLO.DAG; local
603 SelectionDAG &DAG = DCI.DAG; local
641 SimplifyMultipleUseDemandedBits( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const argument
873 SimplifyMultipleUseDemandedBits( SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth) const argument
884 SimplifyMultipleUseDemandedVectorElts( SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const argument
2311 SelectionDAG &DAG = DCI.DAG; local
2327 getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG, const APInt &UndefOp0, const APInt &UndefOp1) argument
2934 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
3013 SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const argument
3047 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
3166 SelectionDAG &DAG = DCI.DAG; local
3280 SelectionDAG &DAG = DCI.DAG; local
3311 SelectionDAG &DAG = DCI.DAG; local
3383 SelectionDAG &DAG = DCI.DAG; local
3412 simplifySetCCWithCTPOP(const TargetLowering &TLI, EVT VT, SDValue N0, const APInt &C1, ISD::CondCode Cond, const SDLoc &dl, SelectionDAG &DAG) argument
3486 SelectionDAG &DAG = DCI.DAG; local
4918 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument
5013 BuildExactSDIV(const TargetLowering &TLI, SDNode *N, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) argument
5079 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
5093 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl<SDNode *> &Created) const argument
5241 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl<SDNode *> &Created) const argument
5466 SelectionDAG &DAG = DCI.DAG; local
5710 SelectionDAG &DAG = DCI.DAG; local
5958 getSqrtInputTest(SDValue Op, SelectionDAG &DAG, const DenormalMode &Mode) const argument
5980 getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth) const argument
6253 expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL, SDValue LH, SDValue RL, SDValue RH) const argument
6435 expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL, SDValue LH, SDValue RL, SDValue RH) const argument
[all...]
H A DSelectionDAGBuilder.cpp164 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, argument
326 getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, Optional<CallingConv::ID> CallConv) argument
473 getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, Optional<CallingConv::ID> CallConv = None, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) argument
610 widenVectorToPartType(SelectionDAG &DAG, SDValue Val, const SDLoc &DL, EVT PartVT) argument
647 getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, Optional<CallingConv::ID> CallConv) argument
806 getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
893 getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V, ISD::NodeType PreferredExtendType) const argument
949 AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector<SDValue> &Ops) const argument
2599 getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) argument
4356 SelectionDAG& DAG = SDB->DAG; local
4873 GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) argument
4886 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl) argument
4899 getF32Constant(SelectionDAG &DAG, unsigned Flt, const SDLoc &dl) argument
4905 getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, SelectionDAG &DAG) argument
4997 expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5019 expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5118 expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5215 expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5305 expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5317 expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags) argument
5346 ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG) argument
5399 expandDivFix(unsigned Opcode, const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue Scale, SelectionDAG &DAG, const TargetLowering &TLI) argument
8130 patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG) argument
8159 getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG) argument
8205 GetRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &RefOpInfo) argument
8934 lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op) argument
9989 SelectionDAG &DAG = SDB->DAG; local
[all...]
H A DDAGCombiner.cpp143 SelectionDAG &DAG; member in class:__anon1871::DAGCombiner
2045 canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) argument
2168 foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) argument
2209 foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) argument
2620 foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL) argument
2751 extractBooleanFlip(SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force) argument
2959 combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N) argument
3050 combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG, const TargetLowering &TLI, SDValue Carry0, SDValue Carry1, SDNode *N) argument
3155 getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &DL) argument
3230 tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations) argument
4067 simplifyDivRem(SDNode *N, SelectionDAG &DAG) argument
5530 combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) argument
6170 matchBSwapHWordOrAndAnd(const TargetLowering &TLI, SelectionDAG &DAG, SDNode *N, SDValue N0, SDValue N1, EVT VT, EVT ShiftAmountTy) argument
6330 visitORCommutative( SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) argument
6524 stripConstantMask(SelectionDAG &DAG, SDValue Op, SDValue &Mask) argument
6534 matchRotateHalf(SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask) argument
6568 extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL) argument
6687 matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG, bool IsRotate) argument
7942 combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) argument
8445 combineShiftToMULH(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) argument
9162 isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI) argument
9174 combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) argument
9223 foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) argument
9366 foldBoolSelectToLogic(SDNode *N, SelectionDAG &DAG) argument
9570 ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) argument
9623 refineUniformBase(SDValue &BasePtr, SDValue &Index, SelectionDAG &DAG) argument
9639 refineIndexType(MaskedGatherScatterSDNode *MGS, SDValue &Index, bool Scaled, SelectionDAG &DAG) argument
10205 tryToFoldExtendSelectLoad(SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG) argument
10248 tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes) argument
10639 tryToFoldExtOfExtload(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType) argument
10670 tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
10710 tryToFoldExtOfMaskedLoad(SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
10738 foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG, bool LegalOperations) argument
11036 isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known) argument
11068 widenCtPop(SDNode *Extend, SelectionDAG &DAG) argument
12371 getPPCf128HiElementSelector(const SelectionDAG &DAG) argument
12377 foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) argument
14392 foldFPToIntToFP(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) argument
14519 FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) argument
14775 visitFMinMax(SelectionDAG &DAG, SDNode *N, APFloat (*Op)(const APFloat &, const APFloat &)) argument
15299 shouldCombineToPostInc(SDNode *N, SDValue Ptr, SDNode *PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) argument
15348 getPostIndexedLoadStoreOp(SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) argument
15869 SelectionDAG *DAG; member in struct:__anon1873::LoadedSlice
16391 SelectionDAG &DAG = DC->getDAG(); local
18474 scalarizeExtractedBinop(SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations) argument
19129 reduceBuildVecToShuffleWithZero(SDNode *BV, SelectionDAG &DAG) argument
19557 combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) argument
19622 combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) argument
19696 combineConcatVectorOfCasts(SDNode *N, SelectionDAG &DAG) argument
19951 narrowInsertExtractVectorBinOp(SDNode *Extract, SelectionDAG &DAG, bool LegalOperations) argument
19988 narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG, bool LegalOperations) argument
20119 narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) argument
20357 foldShuffleOfConcatUndefs(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
20481 combineShuffleOfScalars(ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI) argument
20619 combineTruncationShuffle(ShuffleVectorSDNode *SVN, SelectionDAG &DAG) argument
20680 combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
20732 formSplatFromShuffles(ShuffleVectorSDNode *OuterShuf, SelectionDAG &DAG) argument
20809 replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
21721 scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG) argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1318 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, argument
1347 convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, CCValAssign &VA, SDValue Value) argument
1371 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1541 SelectionDAG &DAG = CLI.DAG; local
1993 emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument
2013 emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument
2056 adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2076 adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2232 adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2302 adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2434 adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2525 adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2543 getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond) argument
3894 lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const argument
4150 getCCResult(SelectionDAG &DAG, SDValue CCReg) argument
4471 getPermuteNode(SelectionDAG &DAG, const SDLoc &DL, const Permute &P, SDValue Op0, SDValue Op1) argument
4517 getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL, SDValue *Ops, const SmallVectorImpl<int> &Bytes) argument
4688 getNode(SelectionDAG &DAG, const SDLoc &DL) argument
5728 SelectionDAG &DAG = DCI.DAG; local
5867 SelectionDAG &DAG = DCI.DAG; local
5896 SelectionDAG &DAG = DCI.DAG; local
5917 SelectionDAG &DAG = DCI.DAG; local
5944 SelectionDAG &DAG = DCI.DAG; local
5978 SelectionDAG &DAG = DCI.DAG; local
6043 SelectionDAG &DAG = DCI.DAG; local
6104 SelectionDAG &DAG = DCI.DAG; local
6143 SelectionDAG &DAG = DCI.DAG; local
6184 SelectionDAG &DAG = DCI.DAG; local
6218 SelectionDAG &DAG = DCI.DAG; local
6284 SelectionDAG &DAG = DCI.DAG; local
6343 SelectionDAG &DAG = DCI.DAG; local
6365 SelectionDAG &DAG = DCI.DAG; local
6562 SelectionDAG &DAG = DCI.DAG; local
6586 SelectionDAG &DAG = DCI.DAG; local
6651 SelectionDAG &DAG = DCI.DAG; local
6668 SelectionDAG &DAG = DCI.DAG; local
6834 computeKnownBitsBinOp(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument
6848 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
6942 computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument
6966 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1241 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, argument
1252 static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, argument
987 translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG) argument
1264 convertFromScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1279 getDefaultVLOps(MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1293 getDefaultScalableVLOps(MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1320 lowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1337 lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1610 splatPartsI64ThroughStack(const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG) argument
1645 splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG) argument
1663 splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, SDValue VL, SelectionDAG &DAG) argument
1676 lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1703 lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
1896 getRVVFPExtendOrRound(SDValue Op, MVT VT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
2443 getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument
2448 getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument
2454 getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument
2460 getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument
2466 getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const argument
2549 getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const argument
2845 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument
2974 lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const argument
3025 lowerFixedLengthVectorExtendToRVV( SDValue Op, SelectionDAG &DAG, unsigned ExtendOpc) const argument
3244 lowerVectorIntrinsicSplats(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
3611 getRVVFPReductionOpAndOperands(SDValue Op, SelectionDAG &DAG, EVT EltVT) argument
4187 lowerFixedLengthVectorLogicOpToRVV( SDValue Op, SelectionDAG &DAG, unsigned MaskOpc, unsigned VecOpc) const argument
4269 lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, bool HasMask) const argument
4308 lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const argument
4595 customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, unsigned ExtOpc = ISD::ANY_EXTEND) argument
4608 customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) argument
5211 combineORToGREV(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
5237 combineORToGORC(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
5316 combineORToSHFL(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument
5393 combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) argument
5430 combineSelectCCAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes) argument
5467 combineSelectCCAndUseCommutative(SDNode *N, SelectionDAG &DAG, bool AllOnes) argument
5481 SelectionDAG &DAG = DCI.DAG; local
5490 SelectionDAG &DAG = DCI.DAG; local
5508 SelectionDAG &DAG = DCI.DAG; local
5517 SelectionDAG &DAG = DCI.DAG; local
6055 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
6140 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
6960 convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget) argument
6984 unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const RISCVTargetLowering &TLI) argument
7002 convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget) argument
7028 unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL) argument
7056 unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL) argument
7207 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
7433 getPrefTypeAlign(EVT VT, SelectionDAG &DAG) argument
7442 SelectionDAG &DAG = CLI.DAG; local
8524 splitValueIntoRegisterParts( SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument
8566 joinRegisterPartsIntoValue( SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1767 isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1798 isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1835 isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1903 isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument
1928 isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument
2018 isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG) argument
2047 isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
2389 getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG) argument
2403 get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) argument
2530 provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) argument
2578 SelectAddressRegReg( SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const argument
2634 fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) argument
2669 SelectAddressRegImm( SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const argument
3021 LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) argument
3045 setUsesTOCBasePtr(SelectionDAG &DAG) argument
3049 getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const argument
3925 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3940 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4192 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, const SDLoc &dl) const argument
4206 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4592 CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, unsigned ParamSize) argument
4897 isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) argument
4926 StoreTailCallArgumentsToStackSlot( SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) argument
4943 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) argument
4967 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) argument
4985 EmitTailCallLoadFPAndRetAddr( SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, const SDLoc &dl) const argument
5004 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
5015 LowerMemOpCallTo( SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) argument
5039 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument
5076 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
5140 isIndirectCall(const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint) argument
5209 transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) argument
5303 prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl) argument
5314 prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) argument
5407 buildCallOperands(SmallVectorImpl<SDValue> &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget) argument
5489 FinishCall( CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const argument
5562 SelectionDAG &DAG = CLI.DAG; local
5636 LowerCall_32SVR4( SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const argument
5875 createMemcpyOutsideCallSeq( SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) const argument
5890 LowerCall_64SVR4( SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const argument
6766 truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl) argument
6840 LowerFormalArguments_AIX( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
7111 LowerCall_AIX( SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const argument
7941 convertFPToInt(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) argument
7988 LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, SelectionDAG &DAG, const SDLoc &dl) const argument
8035 LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
8046 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
8156 canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, SelectionDAG &DAG, ISD::LoadExtType ET) const argument
8263 convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG, const PPCSubtarget &Subtarget, SDValue Chain = SDValue()) argument
8292 LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
8309 widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) argument
8329 LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
8837 getCanonicalConstSplat(uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
8859 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8868 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8878 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8888 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
9292 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
12618 getSqrtInputTest(SDValue Op, SelectionDAG &DAG, const DenormalMode &Mode) const argument
12659 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument
12679 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument
12719 getBaseWithConstantOffset(SDValue Loc, SDValue &Base, int64_t& Offset, SelectionDAG &DAG) argument
12731 isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) argument
12771 isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) argument
12848 findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) argument
12915 generateEquivalentSub(SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG) argument
12951 SelectionDAG &DAG = DCI.DAG; local
12991 SelectionDAG &DAG = DCI.DAG; local
13273 SelectionDAG &DAG = DCI.DAG; local
13573 SelectionDAG &DAG = DCI.DAG; local
13605 SelectionDAG &DAG = DCI.DAG; local
13686 combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) argument
13776 addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems) argument
13815 combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) argument
13913 combineBVZEXTLOAD(SDNode *N, SelectionDAG &DAG) argument
13954 SelectionDAG &DAG = DCI.DAG; local
14150 SelectionDAG &DAG = DCI.DAG; local
14218 SelectionDAG &DAG = DCI.DAG; local
14284 SelectionDAG &DAG = DCI.DAG; local
14623 SelectionDAG &DAG = DCI.DAG; local
14674 SelectionDAG &DAG = DCI.DAG; local
15388 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
15421 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
16337 getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth) const argument
16439 stripModuloOnShift(const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
16519 combineADDToADDZE(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) argument
16607 combineADDToMAT_PCREL_ADDR(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) argument
16729 SelectionDAG &DAG = DCI.DAG; local
16822 SelectionDAG &DAG = DCI.DAG; local
16960 SelectionDAG &DAG = DCI.DAG; local
17036 setAlignFlagsForFI(SDValue N, unsigned &FlagSet, SelectionDAG &DAG) argument
17065 computeFlagsForAddressComputation(SDValue N, unsigned &FlagSet, SelectionDAG &DAG) argument
17250 SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1928 static bool isS16(const SDValue &Op, SelectionDAG &DAG) { argument
2062 SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, argument
2076 MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, SDValue Val) const argument
2093 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
2182 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
2196 PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
2228 SelectionDAG &DAG = CLI.DAG; local
2780 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, const bool isIndirect) const argument
2917 LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, const SDLoc &DL, SelectionDAG &DAG) argument
3214 LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) argument
3474 LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG, TLSModel::Model model) const argument
3570 promoteToConstantPool(const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl) argument
3834 LowerINTRINSIC_VOID( SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument
3877 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument
4015 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
4052 LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
4079 LowerVASTART(SDValue Op, SelectionDAG &DAG) argument
4093 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &dl) const argument
4138 StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, int ArgOffset, unsigned ArgSize) const argument
4192 VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable) const argument
4212 splitValueIntoRegisterParts( SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument
4230 joinRegisterPartsIntoValue( SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument
4248 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4495 getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const argument
4636 getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, bool Signaling) const argument
4676 getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const argument
4768 ConvertBooleanCarryToCarryFlag(SDValue BoolCarry, SelectionDAG &DAG) argument
4781 ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT, SelectionDAG &DAG) argument
4829 LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
5043 LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) argument
5342 bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) argument
5354 expandf64Toi32(SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2) argument
5592 LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument
5662 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument
5866 ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument
5891 CombineVMOVDRRCandidateWithVecOp(const SDNode *BC, SelectionDAG &DAG) argument
5939 ExpandBITCAST(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument
6003 getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
6160 LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
6216 LowerCTPOP(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
6302 LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
6345 Expand64BitShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
6427 LowerVSETCC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
6607 LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) argument
6640 isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type) argument
6790 LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument
7268 LowerBuildVectorOfFPTrunc(SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) argument
7321 LowerBuildVectorOfFPExt(SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) argument
7363 IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl) argument
7380 LowerBUILD_VECTOR_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
7440 LowerBUILD_VECTORToVIDUP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
7475 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument
8007 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
8066 LowerVECTOR_SHUFFLEv8i8(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument
8087 LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op, SelectionDAG &DAG) argument
8117 PromoteMVEPredVector(SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG) argument
8152 LowerVECTOR_SHUFFLE_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8192 LowerVECTOR_SHUFFLEUsingMovs(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument
8278 LowerVECTOR_SHUFFLEUsingOneOff(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument
8329 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8537 LowerINSERT_VECTOR_ELT_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8600 LowerEXTRACT_VECTOR_ELT_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8618 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8639 LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8691 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8716 LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8754 LowerTruncatei1(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
8773 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument
8826 isSignExtended(SDNode *N, SelectionDAG &DAG) argument
8836 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument
8865 AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument
8887 SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) argument
8911 SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) argument
8962 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument
8973 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument
8984 LowerMUL(SDValue Op, SelectionDAG &DAG) argument
9059 LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG) argument
9090 LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG) argument
9129 LowerSDIV(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
9165 LowerUDIV(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
9242 LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) argument
9361 LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, SDValue &Chain) const argument
9403 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
9441 LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const argument
9453 WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) argument
9466 ExpandDIV_Windows( SDValue Op, SelectionDAG &DAG, bool Signed, SmallVectorImpl<SDValue> &Results) const argument
9488 LowerPredicateLoad(SDValue Op, SelectionDAG &DAG) argument
9544 LowerPredicateStore(SDValue Op, SelectionDAG &DAG) argument
9581 LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
9619 LowerMLOAD(SDValue Op, SelectionDAG &DAG) argument
9646 LowerVecReduce(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
9712 LowerVecReduceF(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument
9719 LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) argument
9729 ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
9752 createGPRPairNode(SelectionDAG &DAG, SDValue V) argument
9770 ReplaceCMP_SWAP_64Results(SDNode *N, SmallVectorImpl<SDValue> & Results, SelectionDAG &DAG) argument
9954 ReplaceLongIntrinsic(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument
11777 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument
11854 SelectionDAG &DAG = DCI.DAG; local
12369 SelectionDAG &DAG = DCI.DAG; local
12385 PerformUMLALCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
12444 SelectionDAG &DAG = DCI.DAG; local
12579 PerformVQDMULHCombine(SDNode *N, SelectionDAG &DAG) argument
12694 SelectionDAG &DAG = DCI.DAG; local
13109 PerformMVEVMULLCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
13177 SelectionDAG &DAG = DCI.DAG; local
13302 SelectionDAG &DAG = DCI.DAG; local
13371 SelectionDAG &DAG = DCI.DAG; local
13452 SelectionDAG &DAG = DCI.DAG; local
13484 SelectionDAG &DAG = DCI.DAG; local
13665 SelectionDAG &DAG = DCI.DAG; local
13762 SelectionDAG &DAG = DCI.DAG; local
13952 SelectionDAG &DAG = DCI.DAG; local
14027 PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) argument
14144 SelectionDAG &DAG = DCI.DAG; local
14484 PerformSignExtendInregCombine(SDNode *N, SelectionDAG &DAG) argument
14501 FlattenVectorShuffle(ShuffleVectorSDNode *N, SelectionDAG &DAG) argument
14539 PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) argument
14599 SelectionDAG &DAG = DCI.DAG; local
14961 SelectionDAG &DAG = DCI.DAG; local
15085 SelectionDAG &DAG = DCI.DAG; local
15137 PerformTruncatingStoreCombine(StoreSDNode *St, SelectionDAG &DAG) argument
15222 PerformSplittingToNarrowingStores(StoreSDNode *St, SelectionDAG &DAG) argument
15331 PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) argument
15392 SelectionDAG &DAG = DCI.DAG; local
15415 SelectionDAG &DAG = DCI.DAG; local
15451 PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
15508 PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument
15558 PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
15842 PerformLongShiftCombine(SDNode *N, SelectionDAG &DAG) argument
15873 SelectionDAG &DAG = DCI.DAG; local
16101 SelectionDAG &DAG = DCI.DAG; local
16187 PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) argument
16270 PerformExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
16313 PerformFPExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
16324 PerformMinMaxCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument
16633 SelectionDAG &DAG = DCI.DAG; local
16914 SelectionDAG &DAG = DCI.DAG; local
17793 getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
17852 getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
17877 getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
18081 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
19483 shouldExpandShift(SelectionDAG &DAG, SDNode *N) const argument
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp191 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { argument
1689 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
2398 emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling) argument
2409 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument
2515 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument
2625 emitConjunctionRec(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) argument
2737 emitConjunction(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) argument
2785 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) argument
2917 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument
3114 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
3150 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument
3181 LowerPREFETCH(SDValue Op, SelectionDAG &DAG) argument
3498 addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument
3515 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument
3541 skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) argument
3566 isSignExtended(SDNode *N, SelectionDAG &DAG) argument
3572 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument
3578 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument
3589 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument
3743 getPTrue(SelectionDAG &DAG, SDLoc DL, EVT VT, int Pattern) argument
3749 lowerConvertToSVBool(SDValue Op, SelectionDAG &DAG) argument
4181 selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT, unsigned &Opcode, bool IsGather, SelectionDAG &DAG) argument
4335 LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG) argument
4808 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
5111 saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) const argument
5197 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
5426 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument
5470 SelectionDAG &DAG = CLI.DAG; local
6093 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
6100 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
6106 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
6113 getTargetNode(BlockAddressSDNode* N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument
6121 getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
6134 getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
6150 getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
6164 getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument
7666 getEstimate(const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) argument
7689 getSqrtInputTest(SDValue Op, SelectionDAG &DAG, const DenormalMode &Mode) const argument
7704 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const argument
7737 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps) const argument
8153 WidenVector(SDValue V64Reg, SelectionDAG &DAG) argument
8173 NarrowVector(SDValue V128Reg, SelectionDAG &DAG) argument
8740 tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) argument
8770 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
8873 GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument
8948 constructDup(SDValue V, int Lane, SDLoc dl, EVT VT, unsigned Opcode, SelectionDAG &DAG) argument
9293 tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
9314 tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument
9362 tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument
9402 tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
9433 tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
9454 tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument
9524 tryLowerToSLI(SDNode *N, SelectionDAG &DAG) argument
9652 NormalizeBuildVector(SDValue Op, SelectionDAG &DAG) argument
9683 ConstantBuildVector(SDValue Op, SelectionDAG &DAG) argument
10413 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) argument
10578 getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG) argument
11585 LowerSVEStructLoad(unsigned Intrinsic, ArrayRef<SDValue> LoadOps, EVT VT, SelectionDAG &DAG, const SDLoc &DL) const argument
11877 foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
11903 performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *ST) argument
11948 performABSCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
11987 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
11997 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
12064 calculatePreExtendType(SDValue Extend, SelectionDAG &DAG) argument
12103 performCommonVectorExtendCombine(SDValue VectorShuffle, SelectionDAG &DAG) argument
12178 performMulVectorExtendCombine(SDNode *Mul, SelectionDAG &DAG) argument
12196 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
12308 performVectorCompareAndMaskUnaryOpCombine(SDNode *N, SelectionDAG &DAG) argument
12354 performIntToFpCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
12395 performFpToIntCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
12470 performFDivCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
12563 SelectionDAG &DAG = DCI.DAG; local
12604 SelectionDAG &DAG = DCI.DAG; local
12694 SelectionDAG &DAG = DCI.DAG; local
12827 SelectionDAG &DAG = DCI.DAG; local
12875 SelectionDAG &DAG = DCI.DAG; local
12913 performVectorTruncateCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
12995 performExtractVectorEltCombine(SDNode *N, SelectionDAG &DAG) argument
13038 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13167 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13229 tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) argument
13362 performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) argument
13409 performUADDVCombine(SDNode *N, SelectionDAG &DAG) argument
13446 performAddDotCombine(SDNode *N, SelectionDAG &DAG) argument
13479 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13521 performAddSubCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13540 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13572 tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) argument
13643 tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) argument
13656 combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N, SelectionDAG &DAG) argument
13666 LowerSVEIntrinsicIndex(SDNode *N, SelectionDAG &DAG) argument
13684 LowerSVEIntrinsicDUP(SDNode *N, SelectionDAG &DAG) argument
13698 LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) argument
13724 tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
13788 getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond) argument
13812 combineSVEReductionInt(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument
13831 combineSVEReductionFP(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument
13848 combineSVEReductionOrderedFP(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument
13896 convertMergedOpToPredOp(SDNode *N, unsigned Opc, SelectionDAG &DAG, bool UnpredOp = false) argument
13920 SelectionDAG &DAG = DCI.DAG; local
14144 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
14165 splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) argument
14235 performLD1Combine(SDNode *N, SelectionDAG &DAG, unsigned Opc) argument
14261 performLDNT1Combine(SDNode *N, SelectionDAG &DAG) argument
14291 performLD1ReplicateCombine(SDNode *N, SelectionDAG &DAG) argument
14315 performST1Combine(SDNode *N, SelectionDAG &DAG) argument
14345 performSTNT1Combine(SDNode *N, SelectionDAG &DAG) argument
14381 replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument
14448 replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument
14501 splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
14572 performUzpCombine(SDNode *N, SelectionDAG &DAG) argument
14597 performGLD1Combine(SDNode *N, SelectionDAG &DAG) argument
14786 performTBISimplification(SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
14801 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
14817 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
15135 performCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) argument
15209 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
15272 performCSELCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
15286 getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) argument
15359 performTBZCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
15390 performVSelectCombine(SDNode *N, SelectionDAG &DAG) argument
15454 SelectionDAG &DAG = DCI.DAG; local
15526 performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM) argument
15578 getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset, SDLoc DL, unsigned BitWidth) argument
15624 performScatterStoreCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument
15728 performGatherLoadCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument
15830 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
15962 legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) argument
15985 combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG, unsigned ScalarSizeInBytes) argument
16075 SelectionDAG &DAG = DCI.DAG; local
16525 ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument
16543 ReplaceReductionResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) argument
16557 splitInt128(SDValue N, SelectionDAG &DAG) argument
16601 createGPRPairNode(SelectionDAG &DAG, SDValue V) argument
16618 ReplaceCMP_SWAP_128Results(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
17099 shouldExpandShift(SelectionDAG &DAG, SDNode *N) const argument
17233 getContainerForFixedLengthVector(SelectionDAG &DAG, EVT VT) argument
17258 getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument
17326 getPredicateForScalableVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument
17334 getPredicateForVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument
17342 convertToScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) argument
17353 convertFromScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) argument
17383 convertFixedMaskToScalableVector(SDValue Mask, SelectionDAG &DAG) argument
17644 LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp, bool OverrideNEON) const argument
[all...]

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