Searched defs:CC1 (Results 1 - 5 of 5) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp586 Constant *CC1 = local
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1584 assert(Bit < 64 && �); bool UseWReg = Bit < 32; unsigned NecessarySize = UseWReg ? 32 : 64; if (Size != NecessarySize) TestReg = moveScalarRegClass( TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass, MIB); static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX}, {AArch64::TBZW, AArch64::TBNZW}}; unsigned Opc = OpcTable[UseWReg][IsNegative]; auto TestBitMI = MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI); return &*TestBitMI; } bool AArch64InstructionSelector::tryOptAndIntoCompareBranch( MachineInstr &AndInst, bool Invert, MachineBasicBlock *DstMBB, MachineIRBuilder &MIB) const { assert(AndInst.getOpcode() == TargetOpcode::G_AND && �); auto MaybeBit = getIConstantVRegValWithLookThrough( AndInst.getOperand(2).getReg(), *MIB.getMRI()); if (!MaybeBit) return false; int32_t Bit = MaybeBit->Value.exactLogBase2(); if (Bit < 0) return false; Register TestReg = AndInst.getOperand(1).getReg(); emitTestBit(TestReg, Bit, Invert, DstMBB, MIB); return true; } MachineInstr *AArch64InstructionSelector::emitCBZ(Register CompareReg, bool IsNegative, MachineBasicBlock *DestMBB, MachineIRBuilder &MIB) const { assert(ProduceNonFlagSettingCondBr && �); MachineRegisterInfo &MRI = *MIB.getMRI(); assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == AArch64::GPRRegBankID && �); auto Ty = MRI.getType(CompareReg); unsigned Width = Ty.getSizeInBits(); assert(!Ty.isVector() && �); assert(Width <= 64 && �); static const unsigned OpcTable[2][2] = {{AArch64::CBZW, AArch64::CBZX}, {AArch64::CBNZW, AArch64::CBNZX}}; unsigned Opc = OpcTable[IsNegative][Width == 64]; auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); constrainSelectedInstRegOperands(*BranchMI, TII, TRI, RBI); return &*BranchMI; } bool AArch64InstructionSelector::selectCompareBranchFedByFCmp( MachineInstr &I, MachineInstr &FCmp, MachineIRBuilder &MIB) const { assert(FCmp.getOpcode() == TargetOpcode::G_FCMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); auto Pred = (CmpInst::Predicate)FCmp.getOperand(1).getPredicate(); emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, Pred); AArch64CC::CondCode CC1, CC2; changeFCMPPredToAArch64CC(static_cast<CmpInst::Predicate>(Pred), CC1, CC2); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); if (CC2 != AArch64CC::AL) MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); I.eraseFromParent(); return true; } bool AArch64InstructionSelector::tryOptCompareBranchFedByICmp( MachineInstr &I, MachineInstr &ICmp, MachineIRBuilder &MIB) const { assert(ICmp.getOpcode() == TargetOpcode::G_ICMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); if (!ProduceNonFlagSettingCondBr) return false; MachineRegisterInfo &MRI = *MIB.getMRI(); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); auto Pred = static_cast<CmpInst::Predicate>(ICmp.getOperand(1).getPredicate()); Register LHS = ICmp.getOperand(2).getReg(); Register RHS = ICmp.getOperand(3).getReg(); auto VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); if (VRegAndVal && !AndInst) { int64_t C = VRegAndVal->Value.getSExtValue(); if (C == -1 && Pred == CmpInst::ICMP_SGT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, false, DestMBB, MIB); I.eraseFromParent(); return true; } if (C == 0 && Pred == CmpInst::ICMP_SLT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, true, DestMBB, MIB); I.eraseFromParent(); return true; } if (C == 0 && Pred == CmpInst::ICMP_SGE) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, false, DestMBB, MIB); I.eraseFromParent(); return true; } } if (ICmpInst::isEquality(Pred)) { if (!VRegAndVal) { std::swap(RHS, LHS); VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); } if (VRegAndVal && VRegAndVal->Value == 0) argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5307 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1363 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get(); local
5962 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get(); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp9003 AArch64CC::CondCode CC1, CC2; local
9428 AArch64CC::CondCode CC1, CC2; local
9432 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1, local
9676 AArch64CC::CondCode CC1, CC2; local
14060 AArch64CC::CondCode CC1, CC2; local
17591 AArch64CC::CondCode CC1 = (AArch64CC::CondCode)CSel1.getConstantOperandVal(2); local
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