| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.h | 71 namespace AArch64 { namespace in namespace:llvm
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| H A D | AArch64FixupKinds.h | 15 namespace AArch64 { namespace in namespace:llvm
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 511 namespace AArch64 { namespace in namespace:llvm
1315 namespace AArch64 { namespace in namespace:llvm
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| H A D | AArch64InstrInfo.h | 608 namespace AArch64 { namespace in namespace:llvm
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| H A D | AArch64ISelLowering.cpp | 18563 AArch64SetCCInfo AArch64; member in union:SetCCInfo
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | AArch64TargetParser.h | 29 namespace AArch64 { namespace in namespace:llvm
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| /freebsd-current/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | TargetBuiltins.h | 68 namespace AArch64 { namespace in namespace:clang
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| /freebsd-current/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | AArch64.cpp | 32 class AArch64 : public TargetInfo { class in namespace:__anon1290
72 AArch64::AArch64() { function in class:AArch64
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1584 assert(Bit < 64 && �); bool UseWReg = Bit < 32; unsigned NecessarySize = UseWReg ? 32 : 64; if (Size != NecessarySize) TestReg = moveScalarRegClass( TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass, MIB); static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX}, {AArch64::TBZW, AArch64::TBNZW}}; unsigned Opc = OpcTable[UseWReg][IsNegative]; auto TestBitMI = MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB); constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI); return &*TestBitMI; } bool AArch64InstructionSelector::tryOptAndIntoCompareBranch( MachineInstr &AndInst, bool Invert, MachineBasicBlock *DstMBB, MachineIRBuilder &MIB) const { assert(AndInst.getOpcode() == TargetOpcode::G_AND && �); auto MaybeBit = getIConstantVRegValWithLookThrough( AndInst.getOperand(2).getReg(), *MIB.getMRI()); if (!MaybeBit) return false; int32_t Bit = MaybeBit->Value.exactLogBase2(); if (Bit < 0) return false; Register TestReg = AndInst.getOperand(1).getReg(); emitTestBit(TestReg, Bit, Invert, DstMBB, MIB); return true; } MachineInstr *AArch64InstructionSelector::emitCBZ(Register CompareReg, bool IsNegative, MachineBasicBlock *DestMBB, MachineIRBuilder &MIB) const { assert(ProduceNonFlagSettingCondBr && �); MachineRegisterInfo &MRI = *MIB.getMRI(); assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == AArch64::GPRRegBankID && �); auto Ty = MRI.getType(CompareReg); unsigned Width = Ty.getSizeInBits(); assert(!Ty.isVector() && �); assert(Width <= 64 && �); static const unsigned OpcTable[2][2] = {{AArch64::CBZW, AArch64::CBZX}, {AArch64::CBNZW, AArch64::CBNZX}}; unsigned Opc = OpcTable[IsNegative][Width == 64]; auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB); constrainSelectedInstRegOperands(*BranchMI, TII, TRI, RBI); return &*BranchMI; } bool AArch64InstructionSelector::selectCompareBranchFedByFCmp( MachineInstr &I, MachineInstr &FCmp, MachineIRBuilder &MIB) const { assert(FCmp.getOpcode() == TargetOpcode::G_FCMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); auto Pred = (CmpInst::Predicate)FCmp.getOperand(1).getPredicate(); emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, Pred); AArch64CC::CondCode CC1, CC2; changeFCMPPredToAArch64CC(static_cast<CmpInst::Predicate>(Pred), CC1, CC2); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB); if (CC2 != AArch64CC::AL) MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB); I.eraseFromParent(); return true; } bool AArch64InstructionSelector::tryOptCompareBranchFedByICmp( MachineInstr &I, MachineInstr &ICmp, MachineIRBuilder &MIB) const { assert(ICmp.getOpcode() == TargetOpcode::G_ICMP); assert(I.getOpcode() == TargetOpcode::G_BRCOND); if (!ProduceNonFlagSettingCondBr) return false; MachineRegisterInfo &MRI = *MIB.getMRI(); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); auto Pred = static_cast<CmpInst::Predicate>(ICmp.getOperand(1).getPredicate()); Register LHS = ICmp.getOperand(2).getReg(); Register RHS = ICmp.getOperand(3).getReg(); auto VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); if (VRegAndVal && !AndInst) { int64_t C = VRegAndVal->Value.getSExtValue(); if (C == -1 && Pred == CmpInst::ICMP_SGT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, false, DestMBB, MIB); I.eraseFromParent(); return true; } if (C == 0 && Pred == CmpInst::ICMP_SLT) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, true, DestMBB, MIB); I.eraseFromParent(); return true; } if (C == 0 && Pred == CmpInst::ICMP_SGE) { uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; emitTestBit(LHS, Bit, false, DestMBB, MIB); I.eraseFromParent(); return true; } } if (ICmpInst::isEquality(Pred)) { if (!VRegAndVal) { std::swap(RHS, LHS); VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); } if (VRegAndVal && VRegAndVal->Value == 0) argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 849 namespace AArch64 { namespace in namespace:llvm::TailFoldingOpts::AArch64PACKey
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