Searched +hist:7737 +hist:fd96 (Results 1 - 3 of 3) sorted by relevance
| /linux-master/drivers/net/ethernet/atheros/atl1c/ | ||
| H A D | atl1c_hw.h | diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
| H A D | atl1c_ethtool.c | diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
| H A D | atl1c_main.c | diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> diff 7737fd96 Wed Apr 25 14:27:12 MDT 2012 Huang, Xiong <xiong@qca.qualcomm.com> atl1c: refine SERDES-clock related code bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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