Searched hist:80486 (Results 1 - 18 of 18) sorted by relevance
| /freebsd-11-stable/contrib/ipfilter/iplang/ | ||
| H A D | iplang.h | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| /freebsd-11-stable/contrib/ipfilter/ | ||
| H A D | ipt.h | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | kmem.h | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | ipf.h | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| /freebsd-11-stable/contrib/ipfilter/ipsend/ | ||
| H A D | ip.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | sdlpi.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | arp.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | ipsopt.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | resend.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | ipresend.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | ipsend.h | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| H A D | iptest.c | diff 80486 Sat Jul 28 09:59:33 MDT 2001 darrenr Import IPFilter version 3.4.20 |
| /freebsd-11-stable/sys/i386/include/ | ||
| H A D | atomic.h | diff 220404 Wed Apr 06 22:03:21 MDT 2011 jkim Implement atomic_load_acq_64(9) and atomic_store_rel_64(9) for i386. These functions are implemented with CMPXCHG8B instruction where it is available, i. e., all Pentium-class and later processors. Note this instruction is also used for atomic_store_rel_64() because a simple XCHG-like instruction for 64-bit memory access does not exist, unfortunately. If the processor lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are performed with interrupt temporarily disabled, assuming it does not support SMP. Although this assumption may be little naive, it is true in reality. This implementation is inspired by Linux. |
| H A D | cpu.h | diff 69003 Tue Nov 21 17:55:21 MST 2000 markm Add a consistent API to a feature that most modern CPUs have; a fast counter register in-CPU. This is to be used as a fast "timer", where linearity is more important than time, and multiple lines in the linearity caused by multiple CPUs in an SMP machine is not a problem. This adds no code whatsoever to the FreeBSD kernel until it is actually used, and then as a single-instruction inline routine (except for the 80386 and 80486 where it is some more inline code around nanotime(9). Reviewed by: bde, kris, jhb |
| /freebsd-11-stable/sys/amd64/include/ | ||
| H A D | cpu.h | diff 69003 Tue Nov 21 17:55:21 MST 2000 markm Add a consistent API to a feature that most modern CPUs have; a fast counter register in-CPU. This is to be used as a fast "timer", where linearity is more important than time, and multiple lines in the linearity caused by multiple CPUs in an SMP machine is not a problem. This adds no code whatsoever to the FreeBSD kernel until it is actually used, and then as a single-instruction inline routine (except for the 80386 and 80486 where it is some more inline code around nanotime(9). Reviewed by: bde, kris, jhb |
| /freebsd-11-stable/sys/x86/x86/ | ||
| H A D | mptable.c | diff 139864 Fri Jan 07 16:42:59 MST 2005 jhb Fix support for machines with default MP Table configurations: - Fix the MP Table pci bridge drivers to not probe the configuration table unless we actually have one. Machines using a default configuration do not have such a table. - Only allow default configuration types of 5 (ISA + PCI) and 6 (EISA + PCI) as the others are not likely to work. Types 1 through 4 use an external APIC (probably with 80486 processors) which we certainly do not support, and type 7 uses an MCA bus which has not been tested with the new MP Table code. - Correct the fact that the single I/O APIC in a default configuration has an ID of 2, not 0. - Fix off by one errors in setting the bus types from the default_data[] arrays for default configurations. - Explicitly configure each of the 16 interrupt pins on the sole I/O APIC when using a default configuration. This is especially helpful for type 6 (EISA + PCI) since the EISA interrupts need to have their polarity programmed based on the values in the ELCR. Much thanks to the submitter and tester who endured several rounds of testing to get this fixed. MFC after: 1 week Tested by: Georg Schwarz georg dot schwarz at freenet dot de |
| H A D | cpu_machdep.c | diff 220404 Wed Apr 06 22:03:21 MDT 2011 jkim Implement atomic_load_acq_64(9) and atomic_store_rel_64(9) for i386. These functions are implemented with CMPXCHG8B instruction where it is available, i. e., all Pentium-class and later processors. Note this instruction is also used for atomic_store_rel_64() because a simple XCHG-like instruction for 64-bit memory access does not exist, unfortunately. If the processor lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are performed with interrupt temporarily disabled, assuming it does not support SMP. Although this assumption may be little naive, it is true in reality. This implementation is inspired by Linux. |
| /freebsd-11-stable/sys/i386/i386/ | ||
| H A D | machdep.c | diff 220404 Wed Apr 06 22:03:21 MDT 2011 jkim Implement atomic_load_acq_64(9) and atomic_store_rel_64(9) for i386. These functions are implemented with CMPXCHG8B instruction where it is available, i. e., all Pentium-class and later processors. Note this instruction is also used for atomic_store_rel_64() because a simple XCHG-like instruction for 64-bit memory access does not exist, unfortunately. If the processor lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are performed with interrupt temporarily disabled, assuming it does not support SMP. Although this assumption may be little naive, it is true in reality. This implementation is inspired by Linux. |
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