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| /freebsd-11-stable/sys/dev/aic7xxx/ | ||
| H A D | aic7xxx.c | diff 79874 Wed Jul 18 19:39:48 MDT 2001 gibbs ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days |
| H A D | aic7xxx_osm.c | diff 79874 Wed Jul 18 19:39:48 MDT 2001 gibbs ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days |
| H A D | aic7xxx.seq | diff 79874 Wed Jul 18 19:39:48 MDT 2001 gibbs ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days |
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