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| /freebsd-11-stable/sys/arm/arm/ | ||
| H A D | busdma_machdep-v4.c | diff 159107 Wed May 31 13:50:33 MDT 2006 cognet If our buffer is not aligned on the cache line size, write back/invalidate the first and last cache line in PREREAD, and just invalidate the cache lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which could lead to stale data overriding what has been transfered by DMA. |
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