Searched hist:239674 (Results 1 - 2 of 2) sorted by path
| /freebsd-10-stable/share/man/man4/ | ||
| H A D | altera_avgen.4 | 239674 Sat Aug 25 09:09:42 MDT 2012 rwatson Add altera_avgen(4), a generic device driver to be used by hard and soft CPU cores on Altera FPGAs. The device driver allows memory-mapped devices on Altera's Avalon SoC bus to be exported to userspace via device nodes. device.hints directories dictate device name, permissible access methods, physical address and length, and I/O alignment. Devices can be accessed using read(2)/write(2), but also memory mapped in userspace using mmap(2). Devices attach directly to the Nexus, as is common for embedded device drivers; in the future something more mature might be desirable. There is currently no facility to support directing device-originated interrupts to userspace. In the future, this device driver may be renamed to socgen(4), as it can in principle also be used with other system-on-chip (SoC) busses, such as Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses with memory-mapped ROMs, frame buffers, etc. Sponsored by: DARPA, AFRL |
| /freebsd-10-stable/sys/dev/altera/avgen/ | ||
| H A D | altera_avgen.h | 239674 Sat Aug 25 09:09:42 MDT 2012 rwatson Add altera_avgen(4), a generic device driver to be used by hard and soft CPU cores on Altera FPGAs. The device driver allows memory-mapped devices on Altera's Avalon SoC bus to be exported to userspace via device nodes. device.hints directories dictate device name, permissible access methods, physical address and length, and I/O alignment. Devices can be accessed using read(2)/write(2), but also memory mapped in userspace using mmap(2). Devices attach directly to the Nexus, as is common for embedded device drivers; in the future something more mature might be desirable. There is currently no facility to support directing device-originated interrupts to userspace. In the future, this device driver may be renamed to socgen(4), as it can in principle also be used with other system-on-chip (SoC) busses, such as Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses with memory-mapped ROMs, frame buffers, etc. Sponsored by: DARPA, AFRL |
Completed in 204 milliseconds