VeriLogger simulation log created at Sat Apr 19 18:46:03 2003
Beginning Compile
Beginning Phase I
Compiling source file: test_c1.v
Finished Phase I
Entering Phase II...
Finished Phase II
Entering Phase III...
Finished Phase III
Highest level modules:   test
Compile Complete
.
Running...
Checker1: state = 0
Checker1: state = 1
Checker1: state = 1
Checker1: state = 1
Checker1: state = 2
Checker1: state = 2
Checker1: state = 3
Checker1: property violated!
Exiting VeriLogger at simulation time 70000
0 Errors, 0 Warnings
Compile time = 0.00000, Load time = 0.00000, Execution time = 0.00000

Normal exit