(* mips - generated by L3 - Mon Jul 03 10:13:58 2017 *) structure mips :> mips = struct structure Map = MutableMap (* ------------------------------------------------------------------------- Type declarations ------------------------------------------------------------------------- *) type Index = { Index: BitsN.nbit, P: bool, index'rst: BitsN.nbit } type Random = { Random: BitsN.nbit, random'rst: BitsN.nbit } type Wired = { Wired: BitsN.nbit, wired'rst: BitsN.nbit } type EntryLo = { C: BitsN.nbit, D: bool, G: bool, PFN: BitsN.nbit, V: bool, entrylo'rst: BitsN.nbit } type PageMask = { Mask: BitsN.nbit, pagemask'rst: BitsN.nbit } type EntryHi = { ASID: BitsN.nbit, R: BitsN.nbit, VPN2: BitsN.nbit, entryhi'rst: BitsN.nbit } type StatusRegister = { BEV: bool, CU0: bool, CU1: bool, ERL: bool, EXL: bool, FR: bool, IE: bool, IM: BitsN.nbit, KSU: BitsN.nbit, KX: bool, RE: bool, SX: bool, UX: bool, statusregister'rst: BitsN.nbit } type ConfigRegister = { AR: BitsN.nbit, AT: BitsN.nbit, BE: bool, K0: BitsN.nbit, M: bool, MT: BitsN.nbit, configregister'rst: BitsN.nbit } type ConfigRegister1 = { C2: bool, CA: bool, DA: BitsN.nbit, DL: BitsN.nbit, DS: BitsN.nbit, EP: bool, FP: bool, IA: BitsN.nbit, IL: BitsN.nbit, IS: BitsN.nbit, M: bool, MD: bool, MMUSize: BitsN.nbit, PC: bool, WR: bool } type ConfigRegister2 = { M: bool, SA: BitsN.nbit, SL: BitsN.nbit, SS: BitsN.nbit, SU: BitsN.nbit, TA: BitsN.nbit, TL: BitsN.nbit, TS: BitsN.nbit, TU: BitsN.nbit } type ConfigRegister3 = { DSPP: bool, LPA: bool, M: bool, MT: bool, SM: bool, SP: bool, TL: bool, ULRI: bool, VEIC: bool, VInt: bool, configregister3'rst: BitsN.nbit } type ConfigRegister6 = { LTLB: bool, TLBSize: BitsN.nbit, configregister6'rst: BitsN.nbit } type CauseRegister = { BD: bool, CE: BitsN.nbit, ExcCode: BitsN.nbit, IP: BitsN.nbit, TI: bool, causeregister'rst: BitsN.nbit } type Context = { BadVPN2: BitsN.nbit, PTEBase: BitsN.nbit, context'rst: BitsN.nbit } type XContext = { BadVPN2: BitsN.nbit, PTEBase: BitsN.nbit, R: BitsN.nbit, xcontext'rst: BitsN.nbit } type HWREna = { CC: bool, CCRes: bool, CPUNum: bool, UL: bool, hwrena'rst: BitsN.nbit } type CP0 = { BadVAddr: BitsN.nbit, Cause: CauseRegister, Compare: BitsN.nbit, Config: ConfigRegister, Config1: ConfigRegister1, Config2: ConfigRegister2, Config3: ConfigRegister3, Config6: ConfigRegister6, Context: Context, Count: BitsN.nbit, Debug: BitsN.nbit, EPC: BitsN.nbit, EntryHi: EntryHi, EntryLo0: EntryLo, EntryLo1: EntryLo, ErrCtl: BitsN.nbit, ErrorEPC: BitsN.nbit, HWREna: HWREna, Index: Index, LLAddr: BitsN.nbit, PRId: BitsN.nbit, PageMask: PageMask, Random: Random, Status: StatusRegister, UsrLocal: BitsN.nbit, Wired: Wired, XContext: XContext } datatype ExceptionType = Int | Mod | TLBL | TLBS | AdEL | AdES | Sys | Bp | ResI | CpU | Ov | Tr | XTLBRefillL | XTLBRefillS datatype LorS = LOAD | STORE type FCSR = { ABS2008: bool, CauseE: bool, CauseI: bool, CauseO: bool, CauseU: bool, CauseV: bool, CauseZ: bool, EnableI: bool, EnableO: bool, EnableU: bool, EnableV: bool, EnableZ: bool, FCC: BitsN.nbit, FS: bool, FlagI: bool, FlagO: bool, FlagU: bool, FlagV: bool, FlagZ: bool, NAN2008: bool, RM: BitsN.nbit, fcsr'rst: BitsN.nbit } type FIR = { ASE: bool, D: bool, F64: bool, L: bool, PS: bool, PrID: BitsN.nbit, Rev: BitsN.nbit, S: bool, W: bool, fir'rst: BitsN.nbit } datatype Branch = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BEQL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BGEZ of BitsN.nbit * BitsN.nbit | BGEZAL of BitsN.nbit * BitsN.nbit | BGEZALL of BitsN.nbit * BitsN.nbit | BGEZL of BitsN.nbit * BitsN.nbit | BGTZ of BitsN.nbit * BitsN.nbit | BGTZL of BitsN.nbit * BitsN.nbit | BLEZ of BitsN.nbit * BitsN.nbit | BLEZL of BitsN.nbit * BitsN.nbit | BLTZ of BitsN.nbit * BitsN.nbit | BLTZAL of BitsN.nbit * BitsN.nbit | BLTZALL of BitsN.nbit * BitsN.nbit | BLTZL of BitsN.nbit * BitsN.nbit | BNE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BNEL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | J of BitsN.nbit | JAL of BitsN.nbit | JALR of BitsN.nbit * BitsN.nbit | JR of BitsN.nbit datatype CP = DMFC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DMTC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MFC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MTC0 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype Store = SB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SC of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SCD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SDL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SDR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SWL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SWR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype Load = LB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LDL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LDR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LLD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LWL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LWR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LWU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype Trap = TEQ of BitsN.nbit * BitsN.nbit | TEQI of BitsN.nbit * BitsN.nbit | TGE of BitsN.nbit * BitsN.nbit | TGEI of BitsN.nbit * BitsN.nbit | TGEIU of BitsN.nbit * BitsN.nbit | TGEU of BitsN.nbit * BitsN.nbit | TLT of BitsN.nbit * BitsN.nbit | TLTI of BitsN.nbit * BitsN.nbit | TLTIU of BitsN.nbit * BitsN.nbit | TLTU of BitsN.nbit * BitsN.nbit | TNE of BitsN.nbit * BitsN.nbit | TNEI of BitsN.nbit * BitsN.nbit datatype Shift = DSLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSLL32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSLLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRA32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRAV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRL32 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSRLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SRAV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SRLV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype MultDiv = DDIV of BitsN.nbit * BitsN.nbit | DDIVU of BitsN.nbit * BitsN.nbit | DIV of BitsN.nbit * BitsN.nbit | DIVU of BitsN.nbit * BitsN.nbit | DMULT of BitsN.nbit * BitsN.nbit | DMULTU of BitsN.nbit * BitsN.nbit | MADD of BitsN.nbit * BitsN.nbit | MADDU of BitsN.nbit * BitsN.nbit | MFHI of BitsN.nbit | MFLO of BitsN.nbit | MSUB of BitsN.nbit * BitsN.nbit | MSUBU of BitsN.nbit * BitsN.nbit | MTHI of BitsN.nbit | MTLO of BitsN.nbit | MUL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MULT of BitsN.nbit * BitsN.nbit | MULTU of BitsN.nbit * BitsN.nbit datatype ArithR = ADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | ADDU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | AND of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DADDU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DSUBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVN of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVZ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | NOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | OR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SUBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | XOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype ArithI = ADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | ADDIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | ANDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DADDIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LUI of BitsN.nbit * BitsN.nbit | ORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLTI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SLTIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | XORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) datatype COP1 = ABS_D of BitsN.nbit * BitsN.nbit | ABS_S of BitsN.nbit * BitsN.nbit | ADD_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | ADD_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | BC1F of BitsN.nbit * BitsN.nbit | BC1FL of BitsN.nbit * BitsN.nbit | BC1T of BitsN.nbit * BitsN.nbit | BC1TL of BitsN.nbit * BitsN.nbit | CEIL_L_D of BitsN.nbit * BitsN.nbit | CEIL_L_S of BitsN.nbit * BitsN.nbit | CEIL_W_D of BitsN.nbit * BitsN.nbit | CEIL_W_S of BitsN.nbit * BitsN.nbit | CFC1 of BitsN.nbit * BitsN.nbit | CTC1 of BitsN.nbit * BitsN.nbit | CVT_D_L of BitsN.nbit * BitsN.nbit | CVT_D_S of BitsN.nbit * BitsN.nbit | CVT_D_W of BitsN.nbit * BitsN.nbit | CVT_L_D of BitsN.nbit * BitsN.nbit | CVT_L_S of BitsN.nbit * BitsN.nbit | CVT_S_D of BitsN.nbit * BitsN.nbit | CVT_S_L of BitsN.nbit * BitsN.nbit | CVT_S_W of BitsN.nbit * BitsN.nbit | CVT_W_D of BitsN.nbit * BitsN.nbit | CVT_W_S of BitsN.nbit * BitsN.nbit | C_cond_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | C_cond_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | DIV_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DIV_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | DMFC1 of BitsN.nbit * BitsN.nbit | DMTC1 of BitsN.nbit * BitsN.nbit | FLOOR_L_D of BitsN.nbit * BitsN.nbit | FLOOR_L_S of BitsN.nbit * BitsN.nbit | FLOOR_W_D of BitsN.nbit * BitsN.nbit | FLOOR_W_S of BitsN.nbit * BitsN.nbit | LDC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LDXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LWC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | LWXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MADD_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | MADD_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | MFC1 of BitsN.nbit * BitsN.nbit | MOVF of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVF_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVF_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVZ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOVZ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MOV_D of BitsN.nbit * BitsN.nbit | MOV_S of BitsN.nbit * BitsN.nbit | MSUB_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | MSUB_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) | MTC1 of BitsN.nbit * BitsN.nbit | MUL_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | MUL_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | NEG_D of BitsN.nbit * BitsN.nbit | NEG_S of BitsN.nbit * BitsN.nbit | ROUND_L_D of BitsN.nbit * BitsN.nbit | ROUND_L_S of BitsN.nbit * BitsN.nbit | ROUND_W_D of BitsN.nbit * BitsN.nbit | ROUND_W_S of BitsN.nbit * BitsN.nbit | SDC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SDXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SQRT_D of BitsN.nbit * BitsN.nbit | SQRT_S of BitsN.nbit * BitsN.nbit | SUB_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SUB_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SWC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | SWXC1 of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | TRUNC_L_D of BitsN.nbit * BitsN.nbit | TRUNC_L_S of BitsN.nbit * BitsN.nbit | TRUNC_W_D of BitsN.nbit * BitsN.nbit | TRUNC_W_S of BitsN.nbit * BitsN.nbit | UnknownFPInstruction datatype instruction = ArithI of ArithI | ArithR of ArithR | BREAK | Branch of Branch | CACHE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) | COP1 of COP1 | CP of CP | ERET | Load of Load | MultDiv of MultDiv | RDHWR of BitsN.nbit * BitsN.nbit | ReservedInstruction | SYNC of BitsN.nbit | SYSCALL | Shift of Shift | Store of Store | TLBP | TLBR | TLBWI | TLBWR | Trap of Trap | Unpredictable | WAIT datatype maybe_instruction = FAIL of string | OK of instruction | WORD32 of BitsN.nbit (* ------------------------------------------------------------------------- Casting maps (for enumerated types) ------------------------------------------------------------------------- *) structure Cast = struct fun natToExceptionType x = case Nat.toInt x of 0 => Int | 1 => Mod | 2 => TLBL | 3 => TLBS | 4 => AdEL | 5 => AdES | 6 => Sys | 7 => Bp | 8 => ResI | 9 => CpU | 10 => Ov | 11 => Tr | 12 => XTLBRefillL | 13 => XTLBRefillS | _ => raise Fail "natToExceptionType" fun natToLorS x = case Nat.toInt x of 0 => LOAD | 1 => STORE | _ => raise Fail "natToLorS" fun ExceptionTypeToNat x = case x of Int => 0 | Mod => 1 | TLBL => 2 | TLBS => 3 | AdEL => 4 | AdES => 5 | Sys => 6 | Bp => 7 | ResI => 8 | CpU => 9 | Ov => 10 | Tr => 11 | XTLBRefillL => 12 | XTLBRefillS => 13 fun LorSToNat x = case x of LOAD => 0 | STORE => 1 fun ExceptionTypeToString x = case x of Int => "Int" | Mod => "Mod" | TLBL => "TLBL" | TLBS => "TLBS" | AdEL => "AdEL" | AdES => "AdES" | Sys => "Sys" | Bp => "Bp" | ResI => "ResI" | CpU => "CpU" | Ov => "Ov" | Tr => "Tr" | XTLBRefillL => "XTLBRefillL" | XTLBRefillS => "XTLBRefillS" fun LorSToString x = case x of LOAD => "LOAD" | STORE => "STORE" fun stringToExceptionType x = case x of "Int" => Int | "Mod" => Mod | "TLBL" => TLBL | "TLBS" => TLBS | "AdEL" => AdEL | "AdES" => AdES | "Sys" => Sys | "Bp" => Bp | "ResI" => ResI | "CpU" => CpU | "Ov" => Ov | "Tr" => Tr | "XTLBRefillL" => XTLBRefillL | "XTLBRefillS" => XTLBRefillS | _ => raise Fail "stringToExceptionType" fun stringToLorS x = case x of "LOAD" => LOAD | "STORE" => STORE | _ => raise Fail "stringToLorS" end (* ------------------------------------------------------------------------- Record update functions ------------------------------------------------------------------------- *) fun Index_Index_rupd ({Index, P, index'rst}: Index, x') = {Index = x', P = P, index'rst = index'rst}: Index fun Index_P_rupd ({Index, P, index'rst}: Index, x') = {Index = Index, P = x', index'rst = index'rst}: Index fun Index_index'rst_rupd ({Index, P, index'rst}: Index, x') = {Index = Index, P = P, index'rst = x'}: Index fun Random_Random_rupd ({Random, random'rst}: Random, x') = {Random = x', random'rst = random'rst}: Random fun Random_random'rst_rupd ({Random, random'rst}: Random, x') = {Random = Random, random'rst = x'}: Random fun Wired_Wired_rupd ({Wired, wired'rst}: Wired, x') = {Wired = x', wired'rst = wired'rst}: Wired fun Wired_wired'rst_rupd ({Wired, wired'rst}: Wired, x') = {Wired = Wired, wired'rst = x'}: Wired fun EntryLo_C_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = {C = x', D = D, G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} : EntryLo fun EntryLo_D_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = {C = C, D = x', G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} : EntryLo fun EntryLo_G_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = {C = C, D = D, G = x', PFN = PFN, V = V, entrylo'rst = entrylo'rst} : EntryLo fun EntryLo_PFN_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = {C = C, D = D, G = G, PFN = x', V = V, entrylo'rst = entrylo'rst} : EntryLo fun EntryLo_V_rupd ({C, D, G, PFN, V, entrylo'rst}: EntryLo, x') = {C = C, D = D, G = G, PFN = PFN, V = x', entrylo'rst = entrylo'rst} : EntryLo fun EntryLo_entrylo'rst_rupd ({C, D, G, PFN, V, entrylo'rst} : EntryLo, x') = {C = C, D = D, G = G, PFN = PFN, V = V, entrylo'rst = x'}: EntryLo fun PageMask_Mask_rupd ({Mask, pagemask'rst}: PageMask, x') = {Mask = x', pagemask'rst = pagemask'rst}: PageMask fun PageMask_pagemask'rst_rupd ({Mask, pagemask'rst}: PageMask, x') = {Mask = Mask, pagemask'rst = x'}: PageMask fun EntryHi_ASID_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = {ASID = x', R = R, VPN2 = VPN2, entryhi'rst = entryhi'rst}: EntryHi fun EntryHi_R_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = {ASID = ASID, R = x', VPN2 = VPN2, entryhi'rst = entryhi'rst}: EntryHi fun EntryHi_VPN2_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = {ASID = ASID, R = R, VPN2 = x', entryhi'rst = entryhi'rst}: EntryHi fun EntryHi_entryhi'rst_rupd ({ASID, R, VPN2, entryhi'rst}: EntryHi, x') = {ASID = ASID, R = R, VPN2 = VPN2, entryhi'rst = x'}: EntryHi fun StatusRegister_BEV_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = x', CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_CU0_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = x', CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_CU1_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = x', ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_ERL_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = x', EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_EXL_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = x', FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_FR_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = x', IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_IE_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = x', IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_IM_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = x', KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_KSU_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = x', KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_KX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = x', RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_RE_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = x', SX = SX, UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_SX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = x', UX = UX, statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_UX_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = x', statusregister'rst = statusregister'rst}: StatusRegister fun StatusRegister_statusregister'rst_rupd ({BEV, CU0, CU1, ERL, EXL, FR, IE, IM, KSU, KX, RE, SX, UX, statusregister'rst}: StatusRegister, x') = {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = x'}: StatusRegister fun ConfigRegister_AR_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = x', AT = AT, BE = BE, K0 = K0, M = M, MT = MT, configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_AT_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = AR, AT = x', BE = BE, K0 = K0, M = M, MT = MT, configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_BE_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = AR, AT = AT, BE = x', K0 = K0, M = M, MT = MT, configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_K0_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = AR, AT = AT, BE = BE, K0 = x', M = M, MT = MT, configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_M_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = AR, AT = AT, BE = BE, K0 = K0, M = x', MT = MT, configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_MT_rupd ({AR, AT, BE, K0, M, MT, configregister'rst} : ConfigRegister, x') = {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = x', configregister'rst = configregister'rst}: ConfigRegister fun ConfigRegister_configregister'rst_rupd ({AR, AT, BE, K0, M, MT, configregister'rst}: ConfigRegister, x') = {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = MT, configregister'rst = x'}: ConfigRegister fun ConfigRegister1_C2_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = x', CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_CA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = x', DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_DA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = x', DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_DL_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = x', DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_DS_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = x', EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_EP_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = x', FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_FP_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = x', IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_IA_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = x', IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_IL_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = x', IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_IS_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = x', M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_M_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = x', MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_MD_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = x', MMUSize = MMUSize, PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_MMUSize_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = x', PC = PC, WR = WR} : ConfigRegister1 fun ConfigRegister1_PC_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = x', WR = WR} : ConfigRegister1 fun ConfigRegister1_WR_rupd ({C2, CA, DA, DL, DS, EP, FP, IA, IL, IS, M, MD, MMUSize, PC, WR}: ConfigRegister1, x') = {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = x'} : ConfigRegister1 fun ConfigRegister2_M_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = x', SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_SA_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = x', SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_SL_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = x', SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_SS_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = x', SU = SU, TA = TA, TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_SU_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = SS, SU = x', TA = TA, TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_TA_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = x', TL = TL, TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_TL_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = x', TS = TS, TU = TU}: ConfigRegister2 fun ConfigRegister2_TS_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = x', TU = TU}: ConfigRegister2 fun ConfigRegister2_TU_rupd ({M, SA, SL, SS, SU, TA, TL, TS, TU} : ConfigRegister2, x') = {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, TU = x'}: ConfigRegister2 fun ConfigRegister3_DSPP_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = x', LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_LPA_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = x', M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_M_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = x', MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_MT_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = x', SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_SM_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = x', SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_SP_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = x', TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_TL_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = x', ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_ULRI_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = x', VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_VEIC_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = x', VInt = VInt, configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_VInt_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = x', configregister3'rst = configregister3'rst}: ConfigRegister3 fun ConfigRegister3_configregister3'rst_rupd ({DSPP, LPA, M, MT, SM, SP, TL, ULRI, VEIC, VInt, configregister3'rst}: ConfigRegister3, x') = {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = x'} : ConfigRegister3 fun ConfigRegister6_LTLB_rupd ({LTLB, TLBSize, configregister6'rst} : ConfigRegister6, x') = {LTLB = x', TLBSize = TLBSize, configregister6'rst = configregister6'rst} : ConfigRegister6 fun ConfigRegister6_TLBSize_rupd ({LTLB, TLBSize, configregister6'rst} : ConfigRegister6, x') = {LTLB = LTLB, TLBSize = x', configregister6'rst = configregister6'rst} : ConfigRegister6 fun ConfigRegister6_configregister6'rst_rupd ({LTLB, TLBSize, configregister6'rst}: ConfigRegister6, x') = {LTLB = LTLB, TLBSize = TLBSize, configregister6'rst = x'} : ConfigRegister6 fun CauseRegister_BD_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} : CauseRegister, x') = {BD = x', CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, causeregister'rst = causeregister'rst}: CauseRegister fun CauseRegister_CE_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} : CauseRegister, x') = {BD = BD, CE = x', ExcCode = ExcCode, IP = IP, TI = TI, causeregister'rst = causeregister'rst}: CauseRegister fun CauseRegister_ExcCode_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst}: CauseRegister, x') = {BD = BD, CE = CE, ExcCode = x', IP = IP, TI = TI, causeregister'rst = causeregister'rst}: CauseRegister fun CauseRegister_IP_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} : CauseRegister, x') = {BD = BD, CE = CE, ExcCode = ExcCode, IP = x', TI = TI, causeregister'rst = causeregister'rst}: CauseRegister fun CauseRegister_TI_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst} : CauseRegister, x') = {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = x', causeregister'rst = causeregister'rst}: CauseRegister fun CauseRegister_causeregister'rst_rupd ({BD, CE, ExcCode, IP, TI, causeregister'rst}: CauseRegister, x') = {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, causeregister'rst = x'}: CauseRegister fun Context_BadVPN2_rupd ({BadVPN2, PTEBase, context'rst}: Context, x') = {BadVPN2 = x', PTEBase = PTEBase, context'rst = context'rst}: Context fun Context_PTEBase_rupd ({BadVPN2, PTEBase, context'rst}: Context, x') = {BadVPN2 = BadVPN2, PTEBase = x', context'rst = context'rst}: Context fun Context_context'rst_rupd ({BadVPN2, PTEBase, context'rst} : Context, x') = {BadVPN2 = BadVPN2, PTEBase = PTEBase, context'rst = x'}: Context fun XContext_BadVPN2_rupd ({BadVPN2, PTEBase, R, xcontext'rst} : XContext, x') = {BadVPN2 = x', PTEBase = PTEBase, R = R, xcontext'rst = xcontext'rst} : XContext fun XContext_PTEBase_rupd ({BadVPN2, PTEBase, R, xcontext'rst} : XContext, x') = {BadVPN2 = BadVPN2, PTEBase = x', R = R, xcontext'rst = xcontext'rst} : XContext fun XContext_R_rupd ({BadVPN2, PTEBase, R, xcontext'rst}: XContext, x') = {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = x', xcontext'rst = xcontext'rst}: XContext fun XContext_xcontext'rst_rupd ({BadVPN2, PTEBase, R, xcontext'rst} : XContext, x') = {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = R, xcontext'rst = x'} : XContext fun HWREna_CC_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = {CC = x', CCRes = CCRes, CPUNum = CPUNum, UL = UL, hwrena'rst = hwrena'rst}: HWREna fun HWREna_CCRes_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = {CC = CC, CCRes = x', CPUNum = CPUNum, UL = UL, hwrena'rst = hwrena'rst} : HWREna fun HWREna_CPUNum_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = {CC = CC, CCRes = CCRes, CPUNum = x', UL = UL, hwrena'rst = hwrena'rst} : HWREna fun HWREna_UL_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst}: HWREna, x') = {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = x', hwrena'rst = hwrena'rst}: HWREna fun HWREna_hwrena'rst_rupd ({CC, CCRes, CPUNum, UL, hwrena'rst} : HWREna, x') = {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = UL, hwrena'rst = x'} : HWREna fun CP0_BadVAddr_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = x', Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Cause_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = x', Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Compare_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = x', Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Config_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = x', Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Config1_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = x', Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Config2_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = x', Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Config3_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = x', Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Config6_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = x', Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Context_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = x', Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Count_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = x', Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Debug_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = x', EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_EPC_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = x', EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_EntryHi_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = x', EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_EntryLo0_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = x', EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_EntryLo1_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = x', ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_ErrCtl_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = x', ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_ErrorEPC_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = x', HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_HWREna_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = x', Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Index_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = x', LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_LLAddr_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = x', PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_PRId_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = x', PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_PageMask_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = x', Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Random_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = x', Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = XContext}: CP0 fun CP0_Status_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = x', UsrLocal = UsrLocal, Wired = Wired, XContext = XContext} : CP0 fun CP0_UsrLocal_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = x', Wired = Wired, XContext = XContext} : CP0 fun CP0_Wired_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = x', XContext = XContext} : CP0 fun CP0_XContext_rupd ({BadVAddr, Cause, Compare, Config, Config1, Config2, Config3, Config6, Context, Count, Debug, EPC, EntryHi, EntryLo0, EntryLo1, ErrCtl, ErrorEPC, HWREna, Index, LLAddr, PRId, PageMask, Random, Status, UsrLocal, Wired, XContext}: CP0, x') = {BadVAddr = BadVAddr, Cause = Cause, Compare = Compare, Config = Config, Config1 = Config1, Config2 = Config2, Config3 = Config3, Config6 = Config6, Context = Context, Count = Count, Debug = Debug, EPC = EPC, EntryHi = EntryHi, EntryLo0 = EntryLo0, EntryLo1 = EntryLo1, ErrCtl = ErrCtl, ErrorEPC = ErrorEPC, HWREna = HWREna, Index = Index, LLAddr = LLAddr, PRId = PRId, PageMask = PageMask, Random = Random, Status = Status, UsrLocal = UsrLocal, Wired = Wired, XContext = x'} : CP0 fun FCSR_ABS2008_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = x', CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseE_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = x', CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = x', CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = x', CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = x', CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = x', CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_CauseZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = x', EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_EnableI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = x', EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_EnableO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = x', EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_EnableU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = x', EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_EnableV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = x', EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_EnableZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = x', FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FCC_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = x', FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FS_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = x', FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FlagI_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = x', FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FlagO_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = x', FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FlagU_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = x', FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FlagV_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = x', FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_FlagZ_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = x', NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_NAN2008_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = x', RM = RM, fcsr'rst = fcsr'rst}: FCSR fun FCSR_RM_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = x', fcsr'rst = fcsr'rst}: FCSR fun FCSR_fcsr'rst_rupd ({ABS2008, CauseE, CauseI, CauseO, CauseU, CauseV, CauseZ, EnableI, EnableO, EnableU, EnableV, EnableZ, FCC, FS, FlagI, FlagO, FlagU, FlagV, FlagZ, NAN2008, RM, fcsr'rst}: FCSR, x') = {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = x'}: FCSR fun FIR_ASE_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = x', D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_D_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = {ASE = ASE, D = x', F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_F64_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = ASE, D = D, F64 = x', L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_L_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = {ASE = ASE, D = D, F64 = F64, L = x', PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_PS_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = x', PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_PrID_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = x', Rev = Rev, S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_Rev_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = x', S = S, W = W, fir'rst = fir'rst}: FIR fun FIR_S_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = x', W = W, fir'rst = fir'rst}: FIR fun FIR_W_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst}: FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = x', fir'rst = fir'rst}: FIR fun FIR_fir'rst_rupd ({ASE, D, F64, L, PS, PrID, Rev, S, W, fir'rst} : FIR, x') = {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = x'}: FIR (* ------------------------------------------------------------------------- Exceptions ------------------------------------------------------------------------- *) exception UNPREDICTABLE of string (* ------------------------------------------------------------------------- Global variables (state) ------------------------------------------------------------------------- *) val BranchDelay = ref (NONE): ((BitsN.nbit option) option) ref val BranchTo = ref (NONE): ((bool * BitsN.nbit) option) ref val CP0 = ref ({BadVAddr = BitsN.B(0x0,64), Cause = {BD = false, CE = BitsN.B(0x0,2), ExcCode = BitsN.B(0x0,5), IP = BitsN.B(0x0,8), TI = false, causeregister'rst = BitsN.B(0x0,15)}, Compare = BitsN.B(0x0,32), Config = {AR = BitsN.B(0x0,3), AT = BitsN.B(0x0,2), BE = false, K0 = BitsN.B(0x0,3), M = false, MT = BitsN.B(0x0,3), configregister'rst = BitsN.B(0x0,19)}, Config1 = {C2 = false, CA = false, DA = BitsN.B(0x0,3), DL = BitsN.B(0x0,3), DS = BitsN.B(0x0,3), EP = false, FP = false, IA = BitsN.B(0x0,3), IL = BitsN.B(0x0,3), IS = BitsN.B(0x0,3), M = false, MD = false, MMUSize = BitsN.B(0x0,6), PC = false, WR = false}, Config2 = {M = false, SA = BitsN.B(0x0,4), SL = BitsN.B(0x0,4), SS = BitsN.B(0x0,4), SU = BitsN.B(0x0,4), TA = BitsN.B(0x0,4), TL = BitsN.B(0x0,4), TS = BitsN.B(0x0,4), TU = BitsN.B(0x0,3)}, Config3 = {DSPP = false, LPA = false, M = false, MT = false, SM = false, SP = false, TL = false, ULRI = false, VEIC = false, VInt = false, configregister3'rst = BitsN.B(0x0,22)}, Config6 = {LTLB = false, TLBSize = BitsN.B(0x0,16), configregister6'rst = BitsN.B(0x0,15)}, Context = {BadVPN2 = BitsN.B(0x0,19), PTEBase = BitsN.B(0x0,41), context'rst = BitsN.B(0x0,4)}, Count = BitsN.B(0x0,32), Debug = BitsN.B(0x0,32), EPC = BitsN.B(0x0,64), EntryHi = {ASID = BitsN.B(0x0,8), R = BitsN.B(0x0,2), VPN2 = BitsN.B(0x0,27), entryhi'rst = BitsN.B(0x0,27)}, EntryLo0 = {C = BitsN.B(0x0,3), D = false, G = false, PFN = BitsN.B(0x0,28), V = false, entrylo'rst = BitsN.B(0x0,30)}, EntryLo1 = {C = BitsN.B(0x0,3), D = false, G = false, PFN = BitsN.B(0x0,28), V = false, entrylo'rst = BitsN.B(0x0,30)}, ErrCtl = BitsN.B(0x0,32), ErrorEPC = BitsN.B(0x0,64), HWREna = {CC = false, CCRes = false, CPUNum = false, UL = false, hwrena'rst = BitsN.B(0x0,28)}, Index = {Index = BitsN.B(0x0,8), P = false, index'rst = BitsN.B(0x0,23)}, LLAddr = BitsN.B(0x0,64), PRId = BitsN.B(0x0,32), PageMask = {Mask = BitsN.B(0x0,12), pagemask'rst = BitsN.B(0x0,20)}, Random = {Random = BitsN.B(0x0,8), random'rst = BitsN.B(0x0,24)}, Status = {BEV = false, CU0 = false, CU1 = false, ERL = false, EXL = false, FR = false, IE = false, IM = BitsN.B(0x0,8), KSU = BitsN.B(0x0,2), KX = false, RE = false, SX = false, UX = false, statusregister'rst = BitsN.B(0x0,11)}, UsrLocal = BitsN.B(0x0,64), Wired = {Wired = BitsN.B(0x0,8), wired'rst = BitsN.B(0x0,24)}, XContext = {BadVPN2 = BitsN.B(0x0,27), PTEBase = BitsN.B(0x0,31), R = BitsN.B(0x0,2), xcontext'rst = BitsN.B(0x0,4)}}): CP0 ref val FGR = ref (Map.mkMap(SOME 32,BitsN.B(0x0,64))) : (BitsN.nbit Map.map) ref val LLbit = ref (NONE): (bool option) ref val MEM = ref (Map.mkMap(SOME 18446744073709551616,BitsN.B(0x0,8))) : (BitsN.nbit Map.map) ref val PC = ref (BitsN.B(0x0,64)): BitsN.nbit ref val exceptionSignalled = ref (false): bool ref val fcsr = ref ({ABS2008 = false, CauseE = false, CauseI = false, CauseO = false, CauseU = false, CauseV = false, CauseZ = false, EnableI = false, EnableO = false, EnableU = false, EnableV = false, EnableZ = false, FCC = BitsN.B(0x0,8), FS = false, FlagI = false, FlagO = false, FlagU = false, FlagV = false, FlagZ = false, NAN2008 = false, RM = BitsN.B(0x0,2), fcsr'rst = BitsN.B(0x0,3)}): FCSR ref val fir = ref ({ASE = false, D = false, F64 = false, L = false, PS = false, PrID = BitsN.B(0x0,8), Rev = BitsN.B(0x0,8), S = false, W = false, fir'rst = BitsN.B(0x0,9)}): FIR ref val gpr = ref (Map.mkMap(SOME 32,BitsN.B(0x0,64))) : (BitsN.nbit Map.map) ref val hi = ref (NONE): (BitsN.nbit option) ref val lo = ref (NONE): (BitsN.nbit option) ref (* ------------------------------------------------------------------------- Main specification ------------------------------------------------------------------------- *) local fun tuple'32 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, t31] = (t0, (t1, (t2, (t3, (t4, (t5, (t6, (t7, (t8, (t9, (t10, (t11, (t12, (t13, (t14, (t15, (t16, (t17, (t18, (t19, (t20, (t21, (t22, (t23, (t24,(t25,(t26,(t27,(t28,(t29,(t30,t31))))))))))))))))))))))))))))))) | tuple'32 (_: bool list) = raise Fail "tuple'32" in val boolify'32 = tuple'32 o BitsN.toList end local fun tuple'5 [t0,t1,t2,t3,t4] = (t0,(t1,(t2,(t3,t4)))) | tuple'5 (_: bool list) = raise Fail "tuple'5" in val boolify'5 = tuple'5 o BitsN.toList end local fun tuple'26 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, t17,t18,t19,t20,t21,t22,t23,t24,t25] = (t0, (t1, (t2, (t3, (t4, (t5, (t6, (t7, (t8, (t9, (t10, (t11, (t12, (t13, (t14, (t15, (t16, (t17,(t18,(t19,(t20,(t21,(t22,(t23,(t24,t25))))))))))))))))))))))))) | tuple'26 (_: bool list) = raise Fail "tuple'26" in val boolify'26 = tuple'26 o BitsN.toList end fun rec'Index x = {Index = BitsN.bits(7,0) x, P = BitsN.bit(x,31), index'rst = BitsN.bits(30,8) x}; fun reg'Index x = case x of {Index = Index, P = P, index'rst = index'rst} => BitsN.concat[BitsN.fromBit P,index'rst,Index]; fun write'rec'Index (_,x) = reg'Index x; fun write'reg'Index (_,x) = rec'Index x; fun rec'Random x = {Random = BitsN.bits(7,0) x, random'rst = BitsN.bits(31,8) x}; fun reg'Random x = case x of {Random = Random, random'rst = random'rst} => BitsN.@@(random'rst,Random); fun write'rec'Random (_,x) = reg'Random x; fun write'reg'Random (_,x) = rec'Random x; fun rec'Wired x = {Wired = BitsN.bits(7,0) x, wired'rst = BitsN.bits(31,8) x}; fun reg'Wired x = case x of {Wired = Wired, wired'rst = wired'rst} => BitsN.@@(wired'rst,Wired); fun write'rec'Wired (_,x) = reg'Wired x; fun write'reg'Wired (_,x) = rec'Wired x; fun rec'EntryLo x = {C = BitsN.bits(5,3) x, D = BitsN.bit(x,2), G = BitsN.bit(x,0), PFN = BitsN.bits(33,6) x, V = BitsN.bit(x,1), entrylo'rst = BitsN.bits(63,34) x}; fun reg'EntryLo x = case x of {C = C, D = D, G = G, PFN = PFN, V = V, entrylo'rst = entrylo'rst} => BitsN.concat [entrylo'rst,PFN,C,BitsN.fromBit D,BitsN.fromBit V, BitsN.fromBit G]; fun write'rec'EntryLo (_,x) = reg'EntryLo x; fun write'reg'EntryLo (_,x) = rec'EntryLo x; fun rec'PageMask x = {Mask = BitsN.bits(24,13) x, pagemask'rst = BitsN.@@(BitsN.bits(12,0) x,BitsN.bits(31,25) x)}; fun reg'PageMask x = case x of {Mask = Mask, pagemask'rst = pagemask'rst} => BitsN.concat [BitsN.bits(6,0) pagemask'rst,Mask,BitsN.bits(19,7) pagemask'rst]; fun write'rec'PageMask (_,x) = reg'PageMask x; fun write'reg'PageMask (_,x) = rec'PageMask x; fun rec'EntryHi x = {ASID = BitsN.bits(7,0) x, R = BitsN.bits(63,62) x, VPN2 = BitsN.bits(39,13) x, entryhi'rst = BitsN.@@(BitsN.bits(12,8) x,BitsN.bits(61,40) x)}; fun reg'EntryHi x = case x of {ASID = ASID, R = R, VPN2 = VPN2, entryhi'rst = entryhi'rst} => BitsN.concat [R,BitsN.bits(21,0) entryhi'rst,VPN2, BitsN.bits(26,22) entryhi'rst,ASID]; fun write'rec'EntryHi (_,x) = reg'EntryHi x; fun write'reg'EntryHi (_,x) = rec'EntryHi x; fun rec'StatusRegister x = {BEV = BitsN.bit(x,22), CU0 = BitsN.bit(x,28), CU1 = BitsN.bit(x,29), ERL = BitsN.bit(x,2), EXL = BitsN.bit(x,1), FR = BitsN.bit(x,26), IE = BitsN.bit(x,0), IM = BitsN.bits(15,8) x, KSU = BitsN.bits(4,3) x, KX = BitsN.bit(x,7), RE = BitsN.bit(x,25), SX = BitsN.bit(x,6), UX = BitsN.bit(x,5), statusregister'rst = BitsN.concat [BitsN.bits(21,16) x,BitsN.bits(24,23) x,BitsN.bits(27,27) x, BitsN.bits(31,30) x]}; fun reg'StatusRegister x = case x of {BEV = BEV, CU0 = CU0, CU1 = CU1, ERL = ERL, EXL = EXL, FR = FR, IE = IE, IM = IM, KSU = KSU, KX = KX, RE = RE, SX = SX, UX = UX, statusregister'rst = statusregister'rst} => BitsN.concat [BitsN.bits(1,0) statusregister'rst,BitsN.fromBit CU1, BitsN.fromBit CU0,BitsN.bits(2,2) statusregister'rst, BitsN.fromBit FR,BitsN.fromBit RE, BitsN.bits(4,3) statusregister'rst,BitsN.fromBit BEV, BitsN.bits(10,5) statusregister'rst,IM,BitsN.fromBit KX, BitsN.fromBit SX,BitsN.fromBit UX,KSU,BitsN.fromBit ERL, BitsN.fromBit EXL,BitsN.fromBit IE]; fun write'rec'StatusRegister (_,x) = reg'StatusRegister x; fun write'reg'StatusRegister (_,x) = rec'StatusRegister x; fun rec'ConfigRegister x = {AR = BitsN.bits(12,10) x, AT = BitsN.bits(14,13) x, BE = BitsN.bit(x,15), K0 = BitsN.bits(2,0) x, M = BitsN.bit(x,31), MT = BitsN.bits(9,7) x, configregister'rst = BitsN.@@(BitsN.bits(6,3) x,BitsN.bits(30,16) x)}; fun reg'ConfigRegister x = case x of {AR = AR, AT = AT, BE = BE, K0 = K0, M = M, MT = MT, configregister'rst = configregister'rst} => BitsN.concat [BitsN.fromBit M,BitsN.bits(14,0) configregister'rst, BitsN.fromBit BE,AT,AR,MT,BitsN.bits(18,15) configregister'rst, K0]; fun write'rec'ConfigRegister (_,x) = reg'ConfigRegister x; fun write'reg'ConfigRegister (_,x) = rec'ConfigRegister x; fun rec'ConfigRegister1 x = {C2 = BitsN.bit(x,6), CA = BitsN.bit(x,2), DA = BitsN.bits(9,7) x, DL = BitsN.bits(12,10) x, DS = BitsN.bits(15,13) x, EP = BitsN.bit(x,1), FP = BitsN.bit(x,0), IA = BitsN.bits(18,16) x, IL = BitsN.bits(21,19) x, IS = BitsN.bits(24,22) x, M = BitsN.bit(x,31), MD = BitsN.bit(x,5), MMUSize = BitsN.bits(30,25) x, PC = BitsN.bit(x,4), WR = BitsN.bit(x,3)}; fun reg'ConfigRegister1 x = case x of {C2 = C2, CA = CA, DA = DA, DL = DL, DS = DS, EP = EP, FP = FP, IA = IA, IL = IL, IS = IS, M = M, MD = MD, MMUSize = MMUSize, PC = PC, WR = WR} => BitsN.concat [BitsN.fromBit M,MMUSize,IS,IL,IA,DS,DL,DA,BitsN.fromBit C2, BitsN.fromBit MD,BitsN.fromBit PC,BitsN.fromBit WR, BitsN.fromBit CA,BitsN.fromBit EP,BitsN.fromBit FP]; fun write'rec'ConfigRegister1 (_,x) = reg'ConfigRegister1 x; fun write'reg'ConfigRegister1 (_,x) = rec'ConfigRegister1 x; fun rec'ConfigRegister2 x = {M = BitsN.bit(x,31), SA = BitsN.bits(3,0) x, SL = BitsN.bits(7,4) x, SS = BitsN.bits(11,8) x, SU = BitsN.bits(15,12) x, TA = BitsN.bits(19,16) x, TL = BitsN.bits(23,20) x, TS = BitsN.bits(27,24) x, TU = BitsN.bits(30,28) x}; fun reg'ConfigRegister2 x = case x of {M = M, SA = SA, SL = SL, SS = SS, SU = SU, TA = TA, TL = TL, TS = TS, TU = TU} => BitsN.concat[BitsN.fromBit M,TU,TS,TL,TA,SU,SS,SL,SA]; fun write'rec'ConfigRegister2 (_,x) = reg'ConfigRegister2 x; fun write'reg'ConfigRegister2 (_,x) = rec'ConfigRegister2 x; fun rec'ConfigRegister3 x = {DSPP = BitsN.bit(x,10), LPA = BitsN.bit(x,7), M = BitsN.bit(x,31), MT = BitsN.bit(x,2), SM = BitsN.bit(x,1), SP = BitsN.bit(x,4), TL = BitsN.bit(x,0), ULRI = BitsN.bit(x,13), VEIC = BitsN.bit(x,6), VInt = BitsN.bit(x,5), configregister3'rst = BitsN.concat [BitsN.bits(3,3) x,BitsN.bits(9,8) x,BitsN.bits(12,11) x, BitsN.bits(30,14) x]}; fun reg'ConfigRegister3 x = case x of {DSPP = DSPP, LPA = LPA, M = M, MT = MT, SM = SM, SP = SP, TL = TL, ULRI = ULRI, VEIC = VEIC, VInt = VInt, configregister3'rst = configregister3'rst} => BitsN.concat [BitsN.fromBit M,BitsN.bits(16,0) configregister3'rst, BitsN.fromBit ULRI,BitsN.bits(18,17) configregister3'rst, BitsN.fromBit DSPP,BitsN.bits(20,19) configregister3'rst, BitsN.fromBit LPA,BitsN.fromBit VEIC,BitsN.fromBit VInt, BitsN.fromBit SP,BitsN.bits(21,21) configregister3'rst, BitsN.fromBit MT,BitsN.fromBit SM,BitsN.fromBit TL]; fun write'rec'ConfigRegister3 (_,x) = reg'ConfigRegister3 x; fun write'reg'ConfigRegister3 (_,x) = rec'ConfigRegister3 x; fun rec'ConfigRegister6 x = {LTLB = BitsN.bit(x,2), TLBSize = BitsN.bits(31,16) x, configregister6'rst = BitsN.@@(BitsN.bits(1,0) x,BitsN.bits(15,3) x)}; fun reg'ConfigRegister6 x = case x of {LTLB = LTLB, TLBSize = TLBSize, configregister6'rst = configregister6'rst} => BitsN.concat [TLBSize,BitsN.bits(12,0) configregister6'rst,BitsN.fromBit LTLB, BitsN.bits(14,13) configregister6'rst]; fun write'rec'ConfigRegister6 (_,x) = reg'ConfigRegister6 x; fun write'reg'ConfigRegister6 (_,x) = rec'ConfigRegister6 x; fun rec'CauseRegister x = {BD = BitsN.bit(x,31), CE = BitsN.bits(29,28) x, ExcCode = BitsN.bits(6,2) x, IP = BitsN.bits(15,8) x, TI = BitsN.bit(x,30), causeregister'rst = BitsN.concat[BitsN.bits(1,0) x,BitsN.bits(7,7) x,BitsN.bits(27,16) x]}; fun reg'CauseRegister x = case x of {BD = BD, CE = CE, ExcCode = ExcCode, IP = IP, TI = TI, causeregister'rst = causeregister'rst} => BitsN.concat [BitsN.fromBit BD,BitsN.fromBit TI,CE, BitsN.bits(11,0) causeregister'rst,IP, BitsN.bits(12,12) causeregister'rst,ExcCode, BitsN.bits(14,13) causeregister'rst]; fun write'rec'CauseRegister (_,x) = reg'CauseRegister x; fun write'reg'CauseRegister (_,x) = rec'CauseRegister x; fun rec'Context x = {BadVPN2 = BitsN.bits(22,4) x, PTEBase = BitsN.bits(63,23) x, context'rst = BitsN.bits(3,0) x}; fun reg'Context x = case x of {BadVPN2 = BadVPN2, PTEBase = PTEBase, context'rst = context'rst} => BitsN.concat[PTEBase,BadVPN2,context'rst]; fun write'rec'Context (_,x) = reg'Context x; fun write'reg'Context (_,x) = rec'Context x; fun rec'XContext x = {BadVPN2 = BitsN.bits(30,4) x, PTEBase = BitsN.bits(63,33) x, R = BitsN.bits(32,31) x, xcontext'rst = BitsN.bits(3,0) x}; fun reg'XContext x = case x of {BadVPN2 = BadVPN2, PTEBase = PTEBase, R = R, xcontext'rst = xcontext'rst} => BitsN.concat[PTEBase,R,BadVPN2,xcontext'rst]; fun write'rec'XContext (_,x) = reg'XContext x; fun write'reg'XContext (_,x) = rec'XContext x; fun rec'HWREna x = {CC = BitsN.bit(x,2), CCRes = BitsN.bit(x,3), CPUNum = BitsN.bit(x,0), UL = BitsN.bit(x,29), hwrena'rst = BitsN.concat [BitsN.bits(1,1) x,BitsN.bits(28,4) x,BitsN.bits(31,30) x]}; fun reg'HWREna x = case x of {CC = CC, CCRes = CCRes, CPUNum = CPUNum, UL = UL, hwrena'rst = hwrena'rst} => BitsN.concat [BitsN.bits(1,0) hwrena'rst,BitsN.fromBit UL, BitsN.bits(26,2) hwrena'rst,BitsN.fromBit CCRes, BitsN.fromBit CC,BitsN.bits(27,27) hwrena'rst, BitsN.fromBit CPUNum]; fun write'rec'HWREna (_,x) = reg'HWREna x; fun write'reg'HWREna (_,x) = rec'HWREna x; fun ConditionalBranch (b,offset) = BranchTo := (Option.SOME (if b then (false, BitsN.+ (BitsN.+((!PC),BitsN.B(0x4,64)), BitsN.<<(BitsN.signExtend 64 offset,2))) else (true,BitsN.+((!PC),BitsN.B(0x4,64))))); fun ConditionalBranchLikely (b,offset) = if b then BranchTo := (Option.SOME (false, BitsN.+ (BitsN.+((!PC),BitsN.B(0x4,64)), BitsN.<<(BitsN.signExtend 64 offset,2)))) else if Option.isSome (!BranchDelay) then BranchTo := (Option.SOME(true,BitsN.+((!PC),BitsN.B(0x8,64)))) else PC := (BitsN.+((!PC),BitsN.B(0x4,64))); fun NotWordValue value = let val top = BitsN.bits(63,31) value in (not(top = (BitsN.B(0x0,33)))) andalso (not(top = (BitsN.B(0x1FFFFFFFF,33)))) end; fun ExceptionCode ExceptionType = let val x0 = #Cause((!CP0) : CP0) in CP0 := (CP0_Cause_rupd ((!CP0), CauseRegister_ExcCode_rupd (x0, case ExceptionType of Int => BitsN.B(0x0,5) | Mod => BitsN.B(0x1,5) | TLBL => BitsN.B(0x2,5) | TLBS => BitsN.B(0x3,5) | AdEL => BitsN.B(0x4,5) | AdES => BitsN.B(0x5,5) | Sys => BitsN.B(0x8,5) | Bp => BitsN.B(0x9,5) | ResI => BitsN.B(0xA,5) | CpU => BitsN.B(0xB,5) | Ov => BitsN.B(0xC,5) | Tr => BitsN.B(0xD,5) | XTLBRefillL => BitsN.B(0x2,5) | XTLBRefillS => BitsN.B(0x3,5)))) end; fun SignalException ExceptionType = ( if not(#EXL((#Status((!CP0) : CP0)) : StatusRegister)) then case (!BranchDelay) of Option.SOME(Option.SOME _) => ( CP0 := (CP0_EPC_rupd((!CP0),BitsN.-((!PC),BitsN.B(0x4,64)))) ; let val x0 = #Cause((!CP0) : CP0) in CP0 := (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,true))) end ) | _ => ( CP0 := (CP0_EPC_rupd((!CP0),(!PC))) ; let val x0 = #Cause((!CP0) : CP0) in CP0 := (CP0_Cause_rupd((!CP0),CauseRegister_BD_rupd(x0,false))) end ) else () ; let val vectorOffset = if ((ExceptionType = XTLBRefillL) orelse (ExceptionType = XTLBRefillS)) andalso (not(#EXL((#Status((!CP0) : CP0)) : StatusRegister))) then BitsN.B(0x80,30) else BitsN.B(0x180,30) in ( ExceptionCode ExceptionType ; let val x0 = #Status((!CP0) : CP0) in CP0 := (CP0_Status_rupd((!CP0),StatusRegister_EXL_rupd(x0,true))) end ; let val vectorBase = if #BEV((#Status((!CP0) : CP0)) : StatusRegister) then BitsN.B(0xFFFFFFFFBFC00200,64) else BitsN.B(0xFFFFFFFF80000000,64) in ( BranchDelay := NONE ; PC := (BitsN.- (BitsN.@@ (BitsN.bits(63,30) vectorBase, BitsN.+(BitsN.bits(29,0) vectorBase,vectorOffset)), BitsN.B(0x4,64))) ; exceptionSignalled := true ) end ) end ); fun SignalCP1UnusableException () = ( let val x0 = #Cause((!CP0) : CP0) in CP0 := (CP0_Cause_rupd((!CP0),CauseRegister_CE_rupd(x0,BitsN.B(0x1,2)))) end ; SignalException CpU ); fun UserMode () = ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x2,2))) andalso (not((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse (#ERL((#Status((!CP0) : CP0)) : StatusRegister)))); fun SupervisorMode () = ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x1,2))) andalso (not((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse (#ERL((#Status((!CP0) : CP0)) : StatusRegister)))); fun KernelMode () = ((#KSU((#Status((!CP0) : CP0)) : StatusRegister)) = (BitsN.B(0x0,2))) orelse ((#EXL((#Status((!CP0) : CP0)) : StatusRegister)) orelse (#ERL((#Status((!CP0) : CP0)) : StatusRegister))); fun GPR n = if n = (BitsN.B(0x0,5)) then BitsN.B(0x0,64) else Map.lookup((!gpr),BitsN.toNat n); fun write'GPR (value,n) = if not(n = (BitsN.B(0x0,5))) then gpr := (Map.update((!gpr),BitsN.toNat n,value)) else (); fun HI () = case (!hi) of Option.SOME v => v | NONE => raise UNPREDICTABLE "HI"; fun write'HI value = hi := (Option.SOME value); fun LO () = case (!lo) of Option.SOME v => v | NONE => raise UNPREDICTABLE "LO"; fun write'LO value = lo := (Option.SOME value); fun CPR (n,(reg,sel)) = case (n,(reg,sel)) of (0,(BitsN.B(0x8,_),BitsN.B(0x0,_))) => #BadVAddr((!CP0) : CP0) | (0,(BitsN.B(0x9,_),BitsN.B(0x0,_))) => BitsN.fromNat(BitsN.toNat(#Count((!CP0) : CP0)),64) | (0,(BitsN.B(0xB,_),BitsN.B(0x0,_))) => BitsN.fromNat(BitsN.toNat(#Compare((!CP0) : CP0)),64) | (0,(BitsN.B(0xC,_),BitsN.B(0x0,_))) => BitsN.fromNat (BitsN.toNat(reg'StatusRegister(#Status((!CP0) : CP0))),64) | (0,(BitsN.B(0xD,_),BitsN.B(0x0,_))) => BitsN.fromNat (BitsN.toNat(reg'CauseRegister(#Cause((!CP0) : CP0))),64) | (0,(BitsN.B(0xE,_),BitsN.B(0x0,_))) => #EPC((!CP0) : CP0) | (0,(BitsN.B(0xF,_),BitsN.B(0x0,_))) => BitsN.fromNat(BitsN.toNat(#PRId((!CP0) : CP0)),64) | (0,(BitsN.B(0x10,_),BitsN.B(0x0,_))) => BitsN.fromNat (BitsN.toNat(reg'ConfigRegister(#Config((!CP0) : CP0))),64) | (0,(BitsN.B(0x11,_),BitsN.B(0x0,_))) => #LLAddr((!CP0) : CP0) | (0,(BitsN.B(0x17,_),BitsN.B(0x0,_))) => BitsN.fromNat(BitsN.toNat(#Debug((!CP0) : CP0)),64) | (0,(BitsN.B(0x1A,_),BitsN.B(0x0,_))) => BitsN.fromNat(BitsN.toNat(#ErrCtl((!CP0) : CP0)),64) | (0,(BitsN.B(0x1E,_),BitsN.B(0x0,_))) => #ErrorEPC((!CP0) : CP0) | _ => BitsN.B(0x0,64); fun write'CPR (value,(n,(reg,sel))) = case (n,(reg,sel)) of (0,(BitsN.B(0x9,_),BitsN.B(0x0,_))) => CP0 := (CP0_Count_rupd((!CP0),BitsN.bits(31,0) value)) | (0,(BitsN.B(0xB,_),BitsN.B(0x0,_))) => CP0 := (CP0_Compare_rupd((!CP0),BitsN.bits(31,0) value)) | (0,(BitsN.B(0xC,_),BitsN.B(0x0,_))) => let val x0 = #Status((!CP0) : CP0) in CP0 := (CP0_Status_rupd ((!CP0),write'reg'StatusRegister(x0,BitsN.bits(31,0) value))) end | (0,(BitsN.B(0xD,_),BitsN.B(0x0,_))) => let val x0 = #Cause((!CP0) : CP0) in CP0 := (CP0_Cause_rupd ((!CP0),write'reg'CauseRegister(x0,BitsN.bits(31,0) value))) end | (0,(BitsN.B(0xE,_),BitsN.B(0x0,_))) => CP0 := (CP0_EPC_rupd((!CP0),value)) | (0,(BitsN.B(0x10,_),BitsN.B(0x0,_))) => let val x0 = #Config((!CP0) : CP0) in CP0 := (CP0_Config_rupd ((!CP0),write'reg'ConfigRegister(x0,BitsN.bits(31,0) value))) end | (0,(BitsN.B(0x17,_),BitsN.B(0x0,_))) => CP0 := (CP0_Debug_rupd((!CP0),BitsN.bits(31,0) value)) | (0,(BitsN.B(0x1A,_),BitsN.B(0x0,_))) => CP0 := (CP0_ErrCtl_rupd((!CP0),BitsN.bits(31,0) value)) | (0,(BitsN.B(0x1E,_),BitsN.B(0x0,_))) => CP0 := (CP0_ErrorEPC_rupd((!CP0),value)) | _ => (); val BYTE = BitsN.B(0x0,3) val HALFWORD = BitsN.B(0x1,3) val WORD = BitsN.B(0x3,3) val DOUBLEWORD = BitsN.B(0x7,3) fun BigEndianMem () = #BE((#Config((!CP0) : CP0)) : ConfigRegister); fun ReverseEndian () = BitsN.fromBit ((#RE((#Status((!CP0) : CP0)) : StatusRegister)) andalso (UserMode ())); fun BigEndianCPU () = BitsN.??(BitsN.fromBit(BigEndianMem ()),ReverseEndian ()); fun AddressTranslation (vAddr,LorS) = (vAddr,BitsN.B(0x2,3)); fun Aligned (vAddr,MemType) = (BitsN.&&(BitsN.fromNat(BitsN.toNat vAddr,3),MemType)) = (BitsN.B(0x0,3)); fun AdjustEndian (MemType,pAddr) = case MemType of BitsN.B(0x0,_) => BitsN.?? (pAddr, BitsN.fromNat (BitsN.toNat(BitsN.resize_replicate 3 (ReverseEndian (),3)),64)) | BitsN.B(0x1,_) => BitsN.?? (pAddr, BitsN.fromNat (BitsN.toNat (BitsN.@@ (BitsN.resize_replicate 2 (ReverseEndian (),2), BitsN.B(0x0,1))),64)) | BitsN.B(0x3,_) => BitsN.?? (pAddr, BitsN.fromNat (BitsN.toNat(BitsN.@@(ReverseEndian (),BitsN.B(0x0,2))),64)) | BitsN.B(0x7,_) => pAddr | _ => raise UNPREDICTABLE "bad access length"; fun ReadData a = let val a = BitsN.&&(a,BitsN.~(BitsN.B(0x7,64))) in if BigEndianMem () then BitsN.concat [Map.lookup((!MEM),BitsN.toNat a), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64))))] else BitsN.concat [Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x7,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x6,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x5,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x4,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x3,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x2,64)))), Map.lookup((!MEM),BitsN.toNat(BitsN.+(a,BitsN.B(0x1,64)))), Map.lookup((!MEM),BitsN.toNat a)] end; fun LoadMemory (MemType,(AccessLength,(needAlign,(vAddr,link)))) = if needAlign andalso (not(Aligned(vAddr,MemType))) then ( CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) ; SignalException AdEL ; BitsN.B(0x0,64) ) else let val (pAddr,_) = AddressTranslation(vAddr,LOAD) in if (!exceptionSignalled) then BitsN.B(0x0,64) else let val pAddr = AdjustEndian(MemType,pAddr) in ( case link of Option.SOME true => ( LLbit := (Option.SOME true) ; CP0 := (CP0_LLAddr_rupd((!CP0),pAddr)) ) | Option.SOME false => LLbit := NONE | NONE => () ; ReadData pAddr ) end end; fun loadByte (base,(rt,(offset,unsigned))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory(BYTE,(BYTE,(false,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val membyte = BitsN.bits (Nat.+(7,Nat.*(8,BitsN.toNat byte)), Nat.*(8,BitsN.toNat byte)) memdoubleword in write'GPR (if unsigned then BitsN.zeroExtend 64 membyte else BitsN.signExtend 64 membyte,rt) end else () end; fun loadHalf (base,(rt,(offset,unsigned))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory(HALFWORD,(HALFWORD,(true,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@ (BitsN.resize_replicate 2 (BigEndianCPU (),2), BitsN.B(0x0,1))) val memhalf = BitsN.bits (Nat.+(15,Nat.*(8,BitsN.toNat byte)), Nat.*(8,BitsN.toNat byte)) memdoubleword in write'GPR (if unsigned then BitsN.zeroExtend 64 memhalf else BitsN.signExtend 64 memhalf,rt) end else () end; fun loadWord (link,(base,(rt,(offset,unsigned)))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME link)))) in if not (!exceptionSignalled) then let val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val memword = BitsN.bits (Nat.+(31,Nat.*(8,BitsN.toNat byte)), Nat.*(8,BitsN.toNat byte)) memdoubleword in write'GPR (if unsigned then BitsN.zeroExtend 64 memword else BitsN.signExtend 64 memword,rt) end else () end; fun loadDoubleword (link,(base,(rt,offset))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory(DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME link)))) in if not (!exceptionSignalled) then write'GPR(memdoubleword,rt) else () end; fun Fetch () = let val vAddr = (!PC) val memdoubleword = LoadMemory(WORD,(WORD,(true,(vAddr,NONE)))) in if (!exceptionSignalled) then NONE else let val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val memword = BitsN.bits (Nat.+(31,Nat.*(8,BitsN.toNat bytesel)), Nat.*(8,BitsN.toNat bytesel)) memdoubleword in Option.SOME memword end end; fun WriteData (a,(MemElem,(l,h))) = let val a = BitsN.&&(a,BitsN.~(BitsN.B(0x7,64))) in if BigEndianMem () then ( if (Nat.<=(l,7)) andalso (Nat.<=(7,h)) then MEM := (Map.update ((!MEM),BitsN.toNat a,BitsN.bits(63,56) MemElem)) else () ; if (Nat.<=(l,6)) andalso (Nat.<=(6,h)) then let val x = BitsN.+(a,BitsN.B(0x1,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(55,48) MemElem)) end else () ; if (Nat.<=(l,5)) andalso (Nat.<=(5,h)) then let val x = BitsN.+(a,BitsN.B(0x2,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(47,40) MemElem)) end else () ; if (Nat.<=(l,4)) andalso (Nat.<=(4,h)) then let val x = BitsN.+(a,BitsN.B(0x3,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(39,32) MemElem)) end else () ; if (Nat.<=(l,3)) andalso (Nat.<=(3,h)) then let val x = BitsN.+(a,BitsN.B(0x4,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(31,24) MemElem)) end else () ; if (Nat.<=(l,2)) andalso (Nat.<=(2,h)) then let val x = BitsN.+(a,BitsN.B(0x5,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(23,16) MemElem)) end else () ; if (Nat.<=(l,1)) andalso (Nat.<=(1,h)) then let val x = BitsN.+(a,BitsN.B(0x6,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(15,8) MemElem)) end else () ; if l = 0 then let val x = BitsN.+(a,BitsN.B(0x7,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(7,0) MemElem)) end else () ) else ( if (Nat.<=(l,7)) andalso (Nat.<=(7,h)) then MEM := (Map.update ((!MEM),BitsN.toNat a,BitsN.bits(7,0) MemElem)) else () ; if (Nat.<=(l,6)) andalso (Nat.<=(6,h)) then let val x = BitsN.+(a,BitsN.B(0x1,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(15,8) MemElem)) end else () ; if (Nat.<=(l,5)) andalso (Nat.<=(5,h)) then let val x = BitsN.+(a,BitsN.B(0x2,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(23,16) MemElem)) end else () ; if (Nat.<=(l,4)) andalso (Nat.<=(4,h)) then let val x = BitsN.+(a,BitsN.B(0x3,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(31,24) MemElem)) end else () ; if (Nat.<=(l,3)) andalso (Nat.<=(3,h)) then let val x = BitsN.+(a,BitsN.B(0x4,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(39,32) MemElem)) end else () ; if (Nat.<=(l,2)) andalso (Nat.<=(2,h)) then let val x = BitsN.+(a,BitsN.B(0x5,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(47,40) MemElem)) end else () ; if (Nat.<=(l,1)) andalso (Nat.<=(1,h)) then let val x = BitsN.+(a,BitsN.B(0x6,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(55,48) MemElem)) end else () ; if l = 0 then let val x = BitsN.+(a,BitsN.B(0x7,64)) in MEM := (Map.update ((!MEM),BitsN.toNat x,BitsN.bits(63,56) MemElem)) end else () ) end; fun StoreMemory (MemType,(AccessLength,(needAlign,(MemElem,(vAddr,cond))))) = if needAlign andalso (not(Aligned(vAddr,MemType))) then ( CP0 := (CP0_BadVAddr_rupd((!CP0),vAddr)) ; SignalException AdES ; false ) else let val (pAddr,_) = AddressTranslation(vAddr,STORE) in if (!exceptionSignalled) then true else let val pAddr = AdjustEndian(MemType,pAddr) val sc_success = (not cond) orelse (case (!LLbit) of NONE => raise UNPREDICTABLE "conditional store: LLbit not set" | Option.SOME false => false | Option.SOME true => ((#LLAddr((!CP0) : CP0)) = pAddr) orelse (raise UNPREDICTABLE "conditional store: address doesn't match previous LL address")) in ( if sc_success then let val b = Nat.+(BitsN.toNat AccessLength,1) val l = Nat.- (8, Nat.+ (b,BitsN.toNat(BitsN.bits(2,0) vAddr))) val h = Nat.-(Nat.+(l,b),1) in WriteData(pAddr,(MemElem,(l,h))) end else () ; LLbit := NONE ; sc_success ) end end; fun storeWord (base,(rt,(offset,cond))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr,BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) in StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,cond))))) end; fun storeDoubleword (base,(rt,(offset,cond))) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val datadoubleword = GPR rt in StoreMemory (DOUBLEWORD,(DOUBLEWORD,(true,(datadoubleword,(vAddr,cond))))) end; fun rec'FCSR x = {ABS2008 = BitsN.bit(x,19), CauseE = BitsN.bit(x,17), CauseI = BitsN.bit(x,12), CauseO = BitsN.bit(x,14), CauseU = BitsN.bit(x,13), CauseV = BitsN.bit(x,16), CauseZ = BitsN.bit(x,15), EnableI = BitsN.bit(x,7), EnableO = BitsN.bit(x,9), EnableU = BitsN.bit(x,8), EnableV = BitsN.bit(x,11), EnableZ = BitsN.bit(x,10), FCC = BitsN.@@(BitsN.bits(31,25) x,BitsN.bits(23,23) x), FS = BitsN.bit(x,24), FlagI = BitsN.bit(x,2), FlagO = BitsN.bit(x,4), FlagU = BitsN.bit(x,3), FlagV = BitsN.bit(x,6), FlagZ = BitsN.bit(x,5), NAN2008 = BitsN.bit(x,18), RM = BitsN.bits(1,0) x, fcsr'rst = BitsN.bits(22,20) x}; fun reg'FCSR x = case x of {ABS2008 = ABS2008, CauseE = CauseE, CauseI = CauseI, CauseO = CauseO, CauseU = CauseU, CauseV = CauseV, CauseZ = CauseZ, EnableI = EnableI, EnableO = EnableO, EnableU = EnableU, EnableV = EnableV, EnableZ = EnableZ, FCC = FCC, FS = FS, FlagI = FlagI, FlagO = FlagO, FlagU = FlagU, FlagV = FlagV, FlagZ = FlagZ, NAN2008 = NAN2008, RM = RM, fcsr'rst = fcsr'rst} => BitsN.concat [BitsN.bits(7,1) FCC,BitsN.fromBit FS,BitsN.bits(0,0) FCC, fcsr'rst,BitsN.fromBit ABS2008,BitsN.fromBit NAN2008, BitsN.fromBit CauseE,BitsN.fromBit CauseV,BitsN.fromBit CauseZ, BitsN.fromBit CauseO,BitsN.fromBit CauseU,BitsN.fromBit CauseI, BitsN.fromBit EnableV,BitsN.fromBit EnableZ, BitsN.fromBit EnableO,BitsN.fromBit EnableU, BitsN.fromBit EnableI,BitsN.fromBit FlagV,BitsN.fromBit FlagZ, BitsN.fromBit FlagO,BitsN.fromBit FlagU,BitsN.fromBit FlagI,RM]; fun write'rec'FCSR (_,x) = reg'FCSR x; fun write'reg'FCSR (_,x) = rec'FCSR x; fun rec'FIR x = {ASE = BitsN.bit(x,19), D = BitsN.bit(x,17), F64 = BitsN.bit(x,22), L = BitsN.bit(x,21), PS = BitsN.bit(x,18), PrID = BitsN.bits(15,8) x, Rev = BitsN.bits(7,0) x, S = BitsN.bit(x,16), W = BitsN.bit(x,20), fir'rst = BitsN.bits(31,23) x}; fun reg'FIR x = case x of {ASE = ASE, D = D, F64 = F64, L = L, PS = PS, PrID = PrID, Rev = Rev, S = S, W = W, fir'rst = fir'rst} => BitsN.concat [fir'rst,BitsN.fromBit F64,BitsN.fromBit L,BitsN.fromBit W, BitsN.fromBit ASE,BitsN.fromBit PS,BitsN.fromBit D, BitsN.fromBit S,PrID,Rev]; fun write'rec'FIR (_,x) = reg'FIR x; fun write'reg'FIR (_,x) = rec'FIR x; fun IntToWordMIPS v = if IntInf.>(v,2147483647) then BitsN.B(0x7FFFFFFF,32) else if IntInf.<(v,IntInf.~ 2147483648) then BitsN.B(0x7FFFFFFF,32) else BitsN.fromInt(v,32); fun IntToDWordMIPS v = if IntInf.>(v,9223372036854775807) then BitsN.B(0x7FFFFFFFFFFFFFFF,64) else if IntInf.<(v,IntInf.~ 9223372036854775808) then BitsN.B(0x7FFFFFFFFFFFFFFF,64) else BitsN.fromInt(v,64); fun PostOpF32 v = if (#FS((!fcsr) : FCSR)) andalso (FP32.isSubnormal v) then BitsN.B(0x0,32) else v; fun PostOpF64 v = if (#FS((!fcsr) : FCSR)) andalso (FP64.isSubnormal v) then BitsN.B(0x0,64) else v; fun FP32_Abs1985 a = if FP32.isNan a then a else FP32.abs a; fun FP32_Neg1985 a = if FP32.isNan a then a else FP32.neg a; fun FP64_Abs1985 a = if FP64.isNan a then a else FP64.abs a; fun FP64_Neg1985 a = if FP64.isNan a then a else FP64.neg a; fun FP64_Unordered (a,b) = (FP64.isNan a) orelse (FP64.isNan b); fun FP32_Unordered (a,b) = (FP32.isNan a) orelse (FP32.isNan b); fun Rounding_Mode () = case #RM((!fcsr) : FCSR) of BitsN.B(0x0,_) => IEEEReal.TO_NEAREST | BitsN.B(0x1,_) => IEEEReal.TO_ZERO | BitsN.B(0x2,_) => IEEEReal.TO_POSINF | BitsN.B(0x3,_) => IEEEReal.TO_NEGINF | _ => raise General.Bind; fun dfn'ABS_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if #ABS2008((!fcsr) : FCSR) then FGR := (Map.update ((!FGR),BitsN.toNat fd, FP64.abs(Map.lookup((!FGR),BitsN.toNat fs)))) else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64(FP64_Abs1985(Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'ABS_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if #ABS2008((!fcsr) : FCSR) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (FP32.abs (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 (FP32_Abs1985 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); fun dfn'ADD_D (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.add) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))))); fun dfn'ADD_S (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.add) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); fun dfn'BC1F (i,cc) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ConditionalBranch (not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)),i); fun dfn'BC1FL (i,cc) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ConditionalBranchLikely (not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)),i); fun dfn'BC1T (i,cc) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ConditionalBranch(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc),i); fun dfn'BC1TL (i,cc) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ConditionalBranchLikely (BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc),i); fun dfn'C_cond_D (fs,(ft,(cnd,cc))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val i = BitsN.toNat cc val w = #FCC((!fcsr) : FCSR) in fcsr := (FCSR_FCC_rupd ((!fcsr), BitsN.bitFieldInsert(i,i) (w, BitsN.fromBit (case cnd of BitsN.B(0x0,_) => false | BitsN.B(0x1,_) => FP64_Unordered (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)) | BitsN.B(0x2,_) => FP64.equal (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)) | BitsN.B(0x3,_) => (FP64.equal (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft))) orelse (FP64_Unordered (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x4,_) => FP64.lessThan (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)) | BitsN.B(0x5,_) => not(FP64.greaterEqual (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x6,_) => FP64.lessEqual (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)) | BitsN.B(0x7,_) => not(FP64.greaterThan (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft))) | _ => raise General.Bind)))) end; fun dfn'C_cond_S (fs,(ft,(cnd,cc))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val i = BitsN.toNat cc val w = #FCC((!fcsr) : FCSR) in fcsr := (FCSR_FCC_rupd ((!fcsr), BitsN.bitFieldInsert(i,i) (w, BitsN.fromBit (case cnd of BitsN.B(0x0,_) => false | BitsN.B(0x1,_) => FP32_Unordered (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x2,_) => FP32.equal (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x3,_) => (FP32.equal (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))) orelse (FP32_Unordered (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))) | BitsN.B(0x4,_) => FP32.lessThan (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x5,_) => not(FP32.greaterEqual (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))) | BitsN.B(0x6,_) => FP32.lessEqual (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))) | BitsN.B(0x7,_) => not(FP32.greaterThan (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))) | _ => raise General.Bind)))) end; fun dfn'CEIL_L_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_POSINF,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'CEIL_L_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_POSINF, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'CEIL_W_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_POSINF,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'CEIL_W_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_POSINF, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'CVT_D_L (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, FP64.fromInt (Rounding_Mode (), BitsN.toInt(Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'CVT_D_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, FPConvert.fp32_to_fp64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'CVT_D_W (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ( if NotWordValue(Map.lookup((!FGR),BitsN.toNat fs)) then raise UNPREDICTABLE "CVT.D.W: NotWordValue" else () ; FGR := (Map.update ((!FGR),BitsN.toNat fd, FP64.fromInt (Rounding_Mode (), BitsN.toInt (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) ); fun dfn'CVT_L_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'CVT_L_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (Rounding_Mode (), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'CVT_S_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (FPConvert.fp64_to_fp32 (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'CVT_S_L (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (FP32.fromInt (Rounding_Mode (), BitsN.toInt(Map.lookup((!FGR),BitsN.toNat fs)))))); fun dfn'CVT_S_W (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else ( if NotWordValue(Map.lookup((!FGR),BitsN.toNat fs)) then raise UNPREDICTABLE "CVT.S.W: NotWordValue" else () ; FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (FP32.fromInt (Rounding_Mode (), BitsN.toInt (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))) ); fun dfn'CVT_W_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'CVT_W_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (Rounding_Mode (), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'DIV_D (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.div) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))))); fun dfn'DIV_S (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.div) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); fun dfn'FLOOR_L_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_NEGINF,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'FLOOR_L_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_NEGINF, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'FLOOR_W_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_NEGINF,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'FLOOR_W_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_NEGINF, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'LDC1 (ft,(offset,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory (DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then FGR := (Map.update((!FGR),BitsN.toNat ft,memdoubleword)) else () end; fun dfn'LDXC1 (fd,(index,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(GPR index,GPR base) val memdoubleword = LoadMemory (DOUBLEWORD,(DOUBLEWORD,(true,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then FGR := (Map.update((!FGR),BitsN.toNat fd,memdoubleword)) else () end; fun dfn'LWC1 (ft,(offset,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val memdoubleword = LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val memword = BitsN.bits (Nat.+(31,Nat.*(8,BitsN.toNat byte)), Nat.*(8,BitsN.toNat byte)) memdoubleword in FGR := (Map.update ((!FGR),BitsN.toNat ft,BitsN.signExtend 64 memword)) end else () end; fun dfn'LWXC1 (ft,(index,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(GPR index,GPR base) val memdoubleword = LoadMemory(WORD,(WORD,(true,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val memword = BitsN.bits (Nat.+(31,Nat.*(8,BitsN.toNat byte)), Nat.*(8,BitsN.toNat byte)) memdoubleword in FGR := (Map.update ((!FGR),BitsN.toNat ft,BitsN.signExtend 64 memword)) end else () end; fun dfn'MADD_D (fd,(fr,(fs,ft))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.add) (Rounding_Mode (), (PostOpF64 ((L3.snd o FP64.mul) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))), Map.lookup((!FGR),BitsN.toNat fr)))))); fun dfn'MADD_S (fd,(fr,(fs,ft))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.add) (Rounding_Mode (), (PostOpF32 ((L3.snd o FP32.mul) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))))), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fr)))))))); fun dfn'MOV_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))); fun dfn'MOV_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'MOVF (rd,(rs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) then write'GPR(GPR rs,rd) else (); fun dfn'MOVF_D (fd,(fs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) then FGR := (Map.update ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) else (); fun dfn'MOVF_S (fd,(fs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if not(BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc)) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) else (); fun dfn'MOVN_D (fd,(fs,rt)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if not((GPR rt) = (BitsN.B(0x0,64))) then FGR := (Map.update ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) else (); fun dfn'MOVN_S (fd,(fs,rt)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if not((GPR rt) = (BitsN.B(0x0,64))) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) else (); fun dfn'MOVT (rd,(rs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) then write'GPR(GPR rs,rd) else (); fun dfn'MOVT_D (fd,(fs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) then FGR := (Map.update ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) else (); fun dfn'MOVT_S (fd,(fs,cc)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if BitsN.bit(#FCC((!fcsr) : FCSR),BitsN.toNat cc) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) else (); fun dfn'MOVZ_D (fd,(fs,rt)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if (GPR rt) = (BitsN.B(0x0,64)) then FGR := (Map.update ((!FGR),BitsN.toNat fd,Map.lookup((!FGR),BitsN.toNat fs))) else (); fun dfn'MOVZ_S (fd,(fs,rt)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if (GPR rt) = (BitsN.B(0x0,64)) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))) else (); fun dfn'MSUB_D (fd,(fr,(fs,ft))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.sub) (Rounding_Mode (), (PostOpF64 ((L3.snd o FP64.mul) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))), Map.lookup((!FGR),BitsN.toNat fr)))))); fun dfn'MSUB_S (fd,(fr,(fs,ft))) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.sub) (Rounding_Mode (), (PostOpF32 ((L3.snd o FP32.mul) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft))))), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fr)))))))); fun dfn'MUL_D (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.mul) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))))); fun dfn'MUL_S (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.mul) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); fun dfn'NEG_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if #ABS2008((!fcsr) : FCSR) then FGR := (Map.update ((!FGR),BitsN.toNat fd, FP64.neg(Map.lookup((!FGR),BitsN.toNat fs)))) else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64(FP64_Neg1985(Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'NEG_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else if #ABS2008((!fcsr) : FCSR) then FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (FP32.neg (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)))))) else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 (FP32_Neg1985 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); fun dfn'ROUND_L_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_NEAREST,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'ROUND_L_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_NEAREST, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'ROUND_W_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_NEAREST,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'ROUND_W_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_NEAREST, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'SDC1 (ft,(offset,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val datadoubleword = Map.lookup((!FGR),BitsN.toNat ft) val _ = StoreMemory (DOUBLEWORD, (DOUBLEWORD,(true,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SDXC1 (fs,(index,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(GPR index,GPR base) val datadoubleword = Map.lookup((!FGR),BitsN.toNat fs) val _ = StoreMemory (DOUBLEWORD, (DOUBLEWORD,(true,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SQRT_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.sqrt) (Rounding_Mode (),Map.lookup((!FGR),BitsN.toNat fs))))); fun dfn'SQRT_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.sqrt) (Rounding_Mode (), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))))))); fun dfn'SUB_D (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, PostOpF64 ((L3.snd o FP64.sub) (Rounding_Mode (), (Map.lookup((!FGR),BitsN.toNat fs), Map.lookup((!FGR),BitsN.toNat ft)))))); fun dfn'SUB_S (fd,(fs,ft)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, BitsN.signExtend 64 (PostOpF32 ((L3.snd o FP32.sub) (Rounding_Mode (), (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs)), BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat ft)))))))); fun dfn'SWC1 (ft,(offset,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val datadoubleword = BitsN.<< (Map.lookup((!FGR),BitsN.toNat ft), Nat.*(8,BitsN.toNat bytesel)) val _ = StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SWXC1 (ft,(index,base)) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else let val vAddr = BitsN.+(GPR index,GPR base) val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@(BigEndianCPU (),BitsN.B(0x0,2))) val datadoubleword = BitsN.<< (Map.lookup((!FGR),BitsN.toNat ft), Nat.*(8,BitsN.toNat bytesel)) val _ = StoreMemory(WORD,(WORD,(true,(datadoubleword,(vAddr,false))))) in () end; fun dfn'TRUNC_L_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_ZERO,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'TRUNC_L_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_ZERO, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => IntToDWordMIPS x | NONE => BitsN.B(0x7FFFFFFFFFFFFFFF,64))); fun dfn'TRUNC_W_D (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP64.toInt (IEEEReal.TO_ZERO,Map.lookup((!FGR),BitsN.toNat fs)) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'TRUNC_W_S (fd,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fd, case FP32.toInt (IEEEReal.TO_ZERO, BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))) of Option.SOME x => BitsN.signExtend 64 (IntToWordMIPS x) | NONE => BitsN.B(0x7FFFFFFF,64))); fun dfn'DMFC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else write'GPR(Map.lookup((!FGR),BitsN.toNat fs),rt); fun dfn'DMTC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update((!FGR),BitsN.toNat fs,GPR rt)); fun dfn'MFC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else write'GPR (BitsN.signExtend 64 (BitsN.bits(31,0) (Map.lookup((!FGR),BitsN.toNat fs))),rt); fun dfn'MTC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else FGR := (Map.update ((!FGR),BitsN.toNat fs, BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))); fun dfn'CFC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else write'GPR (case fs of BitsN.B(0x0,_) => BitsN.signExtend 64 (reg'FIR (!fir)) | BitsN.B(0x19,_) => BitsN.zeroExtend 64 (#FCC((!fcsr) : FCSR)) | BitsN.B(0x1F,_) => BitsN.signExtend 64 (reg'FCSR (!fcsr)) | _ => raise UNPREDICTABLE "Unsupported floating point control register",rt); fun dfn'CTC1 (rt,fs) = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else case fs of BitsN.B(0x0,_) => () | BitsN.B(0x19,_) => fcsr := (FCSR_FCC_rupd((!fcsr),BitsN.bits(7,0) (GPR rt))) | BitsN.B(0x1F,_) => ( fcsr := (write'reg'FCSR((!fcsr),BitsN.bits(31,0) (GPR rt))) ; fcsr := (FCSR_NAN2008_rupd((!fcsr),true)) ) | _ => raise UNPREDICTABLE "Unsupported floating point control register"; fun dfn'UnknownFPInstruction () = if not(#CU1((#Status((!CP0) : CP0)) : StatusRegister)) then SignalCP1UnusableException () else SignalException ResI; fun dfn'ADDI (rs,(rt,immediate)) = ( if NotWordValue(GPR rs) then raise UNPREDICTABLE "ADDI: NotWordValue" else () ; let val temp = BitsN.+(BitsN.bits(32,0) (GPR rs),BitsN.signExtend 33 immediate) in if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) then SignalException Ov else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rt) end ); fun dfn'ADDIU (rs,(rt,immediate)) = ( if NotWordValue(GPR rs) then raise UNPREDICTABLE "ADDIU: NotWordValue" else () ; let val temp = BitsN.+(BitsN.bits(31,0) (GPR rs),BitsN.signExtend 32 immediate) in write'GPR(BitsN.signExtend 64 temp,rt) end ); fun dfn'DADDI (rs,(rt,immediate)) = let val temp = BitsN.+(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 immediate) in if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) then SignalException Ov else write'GPR(BitsN.bits(63,0) temp,rt) end; fun dfn'DADDIU (rs,(rt,immediate)) = write'GPR(BitsN.+(GPR rs,BitsN.signExtend 64 immediate),rt); fun dfn'SLTI (rs,(rt,immediate)) = write'GPR (BitsN.fromBool 64 (BitsN.<(GPR rs,BitsN.signExtend 64 immediate)),rt); fun dfn'SLTIU (rs,(rt,immediate)) = write'GPR (BitsN.fromBool 64 (BitsN.<+(GPR rs,BitsN.signExtend 64 immediate)),rt); fun dfn'ANDI (rs,(rt,immediate)) = write'GPR(BitsN.&&(GPR rs,BitsN.zeroExtend 64 immediate),rt); fun dfn'ORI (rs,(rt,immediate)) = write'GPR(BitsN.||(GPR rs,BitsN.zeroExtend 64 immediate),rt); fun dfn'XORI (rs,(rt,immediate)) = write'GPR(BitsN.??(GPR rs,BitsN.zeroExtend 64 immediate),rt); fun dfn'LUI (rt,immediate) = write'GPR(BitsN.signExtend 64 (BitsN.@@(immediate,BitsN.B(0x0,16))),rt); fun dfn'ADD (rs,(rt,rd)) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "ADD: NotWordValue" else () ; let val temp = BitsN.+(BitsN.bits(32,0) (GPR rs),BitsN.bits(32,0) (GPR rt)) in if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) then SignalException Ov else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) end ); fun dfn'ADDU (rs,(rt,rd)) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "ADDU: NotWordValue" else () ; let val temp = BitsN.+(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt)) in write'GPR(BitsN.signExtend 64 temp,rd) end ); fun dfn'SUB (rs,(rt,rd)) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "SUB: NotWordValue" else () ; let val temp = BitsN.-(BitsN.bits(32,0) (GPR rs),BitsN.bits(32,0) (GPR rt)) in if not((BitsN.bit(temp,32)) = (BitsN.bit(temp,31))) then SignalException Ov else write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) end ); fun dfn'SUBU (rs,(rt,rd)) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "SUBU: NotWordValue" else () ; let val temp = BitsN.-(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt)) in write'GPR(BitsN.signExtend 64 temp,rd) end ); fun dfn'DADD (rs,(rt,rd)) = let val temp = BitsN.+(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 (GPR rt)) in if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) then SignalException Ov else write'GPR(BitsN.bits(63,0) temp,rd) end; fun dfn'DADDU (rs,(rt,rd)) = write'GPR(BitsN.+(GPR rs,GPR rt),rd); fun dfn'DSUB (rs,(rt,rd)) = let val temp = BitsN.-(BitsN.signExtend 65 (GPR rs),BitsN.signExtend 65 (GPR rt)) in if not((BitsN.bit(temp,64)) = (BitsN.bit(temp,63))) then SignalException Ov else write'GPR(BitsN.bits(63,0) temp,rd) end; fun dfn'DSUBU (rs,(rt,rd)) = write'GPR(BitsN.-(GPR rs,GPR rt),rd); fun dfn'SLT (rs,(rt,rd)) = write'GPR(BitsN.fromBool 64 (BitsN.<(GPR rs,GPR rt)),rd); fun dfn'SLTU (rs,(rt,rd)) = write'GPR(BitsN.fromBool 64 (BitsN.<+(GPR rs,GPR rt)),rd); fun dfn'AND (rs,(rt,rd)) = write'GPR(BitsN.&&(GPR rs,GPR rt),rd); fun dfn'OR (rs,(rt,rd)) = write'GPR(BitsN.||(GPR rs,GPR rt),rd); fun dfn'XOR (rs,(rt,rd)) = write'GPR(BitsN.??(GPR rs,GPR rt),rd); fun dfn'NOR (rs,(rt,rd)) = write'GPR(BitsN.~(BitsN.||(GPR rs,GPR rt)),rd); fun dfn'MOVN (rs,(rt,rd)) = if not((GPR rt) = (BitsN.B(0x0,64))) then write'GPR(GPR rs,rd) else (); fun dfn'MOVZ (rs,(rt,rd)) = if (GPR rt) = (BitsN.B(0x0,64)) then write'GPR(GPR rs,rd) else (); fun dfn'MADD (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MADD: NotWordValue" else () ; let val temp = BitsN.+ (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), BitsN.* (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))) in ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) ) end ); fun dfn'MADDU (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MADDU: NotWordValue" else () ; let val temp = BitsN.+ (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), BitsN.* (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt)))) in ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) ) end ); fun dfn'MSUB (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MSUB: NotWordValue" else () ; let val temp = BitsN.- (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), BitsN.* (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt)))) in ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) ) end ); fun dfn'MSUBU (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MSUBU: NotWordValue" else () ; let val temp = BitsN.- (BitsN.@@(BitsN.bits(31,0) (HI ()),BitsN.bits(31,0) (LO ())), BitsN.* (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt)))) in ( write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) temp)) ; write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) temp)) ) end ); fun dfn'MUL (rs,(rt,rd)) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MUL: NotWordValue" else () ; write'GPR (BitsN.signExtend 64 (BitsN.*(BitsN.bits(31,0) (GPR rs),BitsN.bits(31,0) (GPR rt))),rd) ; lo := NONE ; hi := NONE ); fun dfn'MULT (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MULT: NotWordValue" else () ; let val prod = BitsN.* (BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rt))) in ( write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) prod)) ; write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) prod)) ) end ); fun dfn'MULTU (rs,rt) = ( if (NotWordValue(GPR rs)) orelse (NotWordValue(GPR rt)) then raise UNPREDICTABLE "MULTU: NotWordValue" else () ; let val prod = BitsN.* (BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs)), BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rt))) in ( write'LO(BitsN.signExtend 64 (BitsN.bits(31,0) prod)) ; write'HI(BitsN.signExtend 64 (BitsN.bits(63,32) prod)) ) end ); fun dfn'DMULT (rs,rt) = let val prod = BitsN.*(BitsN.signExtend 128 (GPR rs),BitsN.signExtend 128 (GPR rt)) in ( write'LO(BitsN.bits(63,0) prod); write'HI(BitsN.bits(127,64) prod) ) end; fun dfn'DMULTU (rs,rt) = let val prod = BitsN.*(BitsN.zeroExtend 128 (GPR rs),BitsN.zeroExtend 128 (GPR rt)) in ( write'LO(BitsN.bits(63,0) prod); write'HI(BitsN.bits(127,64) prod) ) end; fun dfn'DIV (rs,rt) = let val s = GPR rs val t = GPR rt in ( if (NotWordValue s) orelse (NotWordValue t) then raise UNPREDICTABLE "DIV: NotWordValue" else () ; if t = (BitsN.B(0x0,64)) then ( lo := NONE; hi := NONE ) else let val q = BitsN.quot(BitsN.bits(31,0) s,BitsN.bits(31,0) t) val r = BitsN.rem(BitsN.bits(31,0) s,BitsN.bits(31,0) t) in ( write'LO(BitsN.signExtend 64 q) ; write'HI(BitsN.signExtend 64 r) ) end ) end; fun dfn'DIVU (rs,rt) = let val s = GPR rs val t = GPR rt in ( if (NotWordValue s) orelse (NotWordValue t) then raise UNPREDICTABLE "DIVU: NotWordValue" else () ; if t = (BitsN.B(0x0,64)) then ( lo := NONE; hi := NONE ) else let val q = BitsN.div(BitsN.bits(31,0) s,BitsN.bits(31,0) t) val r = BitsN.mod(BitsN.bits(31,0) s,BitsN.bits(31,0) t) in ( write'LO(BitsN.signExtend 64 q) ; write'HI(BitsN.signExtend 64 r) ) end ) end; fun dfn'DDIV (rs,rt) = let val t = GPR rt in if t = (BitsN.B(0x0,64)) then ( lo := NONE; hi := NONE ) else let val s = GPR rs in ( write'LO(BitsN.quot(s,t)); write'HI(BitsN.rem(s,t)) ) end end; fun dfn'DDIVU (rs,rt) = let val t = GPR rt in if t = (BitsN.B(0x0,64)) then ( lo := NONE; hi := NONE ) else let val s = GPR rs in ( write'LO(BitsN.div(s,t)); write'HI(BitsN.mod(s,t)) ) end end; fun dfn'MFHI rd = write'GPR(HI (),rd); fun dfn'MFLO rd = write'GPR(LO (),rd); fun dfn'MTHI rs = write'HI(GPR rs); fun dfn'MTLO rs = write'LO(GPR rs); fun dfn'SLL (rt,(rd,sa)) = write'GPR (BitsN.signExtend 64 (BitsN.<<(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd); fun dfn'SRL (rt,(rd,sa)) = ( if NotWordValue(GPR rt) then raise UNPREDICTABLE "SRL: NotWordValue" else () ; write'GPR (BitsN.signExtend 64 (BitsN.>>+(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) ); fun dfn'SRA (rt,(rd,sa)) = ( if NotWordValue(GPR rt) then raise UNPREDICTABLE "SRA: NotWordValue" else () ; write'GPR (BitsN.signExtend 64 (BitsN.>>(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) ); fun dfn'SLLV (rs,(rt,rd)) = let val sa = BitsN.bits(4,0) (GPR rs) in write'GPR (BitsN.signExtend 64 (BitsN.<<(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) end; fun dfn'SRLV (rs,(rt,rd)) = ( if NotWordValue(GPR rt) then raise UNPREDICTABLE "SRLV: NotWordValue" else () ; let val sa = BitsN.bits(4,0) (GPR rs) in write'GPR (BitsN.signExtend 64 (BitsN.>>+(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) end ); fun dfn'SRAV (rs,(rt,rd)) = ( if NotWordValue(GPR rt) then raise UNPREDICTABLE "SRAV: NotWordValue" else () ; let val sa = BitsN.bits(4,0) (GPR rs) in write'GPR (BitsN.signExtend 64 (BitsN.>>(BitsN.bits(31,0) (GPR rt),BitsN.toNat sa)),rd) end ); fun dfn'DSLL (rt,(rd,sa)) = write'GPR(BitsN.<<(GPR rt,BitsN.toNat sa),rd); fun dfn'DSRL (rt,(rd,sa)) = write'GPR(BitsN.>>+(GPR rt,BitsN.toNat sa),rd); fun dfn'DSRA (rt,(rd,sa)) = write'GPR(BitsN.>>(GPR rt,BitsN.toNat sa),rd); fun dfn'DSLLV (rs,(rt,rd)) = let val sa = BitsN.bits(5,0) (GPR rs) in write'GPR(BitsN.<<(GPR rt,BitsN.toNat sa),rd) end; fun dfn'DSRLV (rs,(rt,rd)) = let val sa = BitsN.bits(5,0) (GPR rs) in write'GPR(BitsN.>>+(GPR rt,BitsN.toNat sa),rd) end; fun dfn'DSRAV (rs,(rt,rd)) = let val sa = BitsN.bits(5,0) (GPR rs) in write'GPR(BitsN.>>(GPR rt,BitsN.toNat sa),rd) end; fun dfn'DSLL32 (rt,(rd,sa)) = write'GPR(BitsN.<<(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); fun dfn'DSRL32 (rt,(rd,sa)) = write'GPR(BitsN.>>+(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); fun dfn'DSRA32 (rt,(rd,sa)) = write'GPR(BitsN.>>(GPR rt,Nat.+(BitsN.toNat sa,32)),rd); fun dfn'TGE (rs,rt) = if BitsN.>=(GPR rs,GPR rt) then SignalException Tr else (); fun dfn'TGEU (rs,rt) = if BitsN.>=+(GPR rs,GPR rt) then SignalException Tr else (); fun dfn'TLT (rs,rt) = if BitsN.<(GPR rs,GPR rt) then SignalException Tr else (); fun dfn'TLTU (rs,rt) = if BitsN.<+(GPR rs,GPR rt) then SignalException Tr else (); fun dfn'TEQ (rs,rt) = if (GPR rs) = (GPR rt) then SignalException Tr else (); fun dfn'TNE (rs,rt) = if not((GPR rs) = (GPR rt)) then SignalException Tr else (); fun dfn'TGEI (rs,immediate) = if BitsN.>=(GPR rs,BitsN.signExtend 64 immediate) then SignalException Tr else (); fun dfn'TGEIU (rs,immediate) = if BitsN.>=+(GPR rs,BitsN.signExtend 64 immediate) then SignalException Tr else (); fun dfn'TLTI (rs,immediate) = if BitsN.<(GPR rs,BitsN.signExtend 64 immediate) then SignalException Tr else (); fun dfn'TLTIU (rs,immediate) = if BitsN.<+(GPR rs,BitsN.signExtend 64 immediate) then SignalException Tr else (); fun dfn'TEQI (rs,immediate) = if (GPR rs) = (BitsN.signExtend 64 immediate) then SignalException Tr else (); fun dfn'TNEI (rs,immediate) = if not((GPR rs) = (BitsN.signExtend 64 immediate)) then SignalException Tr else (); fun dfn'LB (base,(rt,offset)) = loadByte(base,(rt,(offset,false))); fun dfn'LBU (base,(rt,offset)) = loadByte(base,(rt,(offset,true))); fun dfn'LH (base,(rt,offset)) = loadHalf(base,(rt,(offset,false))); fun dfn'LHU (base,(rt,offset)) = loadHalf(base,(rt,(offset,true))); fun dfn'LW (base,(rt,offset)) = loadWord(false,(base,(rt,(offset,false)))); fun dfn'LWU (base,(rt,offset)) = loadWord(false,(base,(rt,(offset,true)))); fun dfn'LL (base,(rt,offset)) = loadWord(true,(base,(rt,(offset,false)))); fun dfn'LD (base,(rt,offset)) = loadDoubleword(false,(base,(rt,offset))); fun dfn'LLD (base,(rt,offset)) = loadDoubleword(true,(base,(rt,offset))); fun dfn'LWL (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(1,0) vAddr, BitsN.resize_replicate 2 (BigEndianCPU (),2)) val memdoubleword = LoadMemory (WORD, (BitsN.@@(BitsN.B(0x0,1),byte),(false,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) val temp = case (word,byte) of (BitsN.B(0x0,_),BitsN.B(0x0,_)) => BitsN.@@ (BitsN.bits(7,0) memdoubleword, BitsN.bits(23,0) (GPR rt)) | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => BitsN.@@ (BitsN.bits(15,0) memdoubleword, BitsN.bits(15,0) (GPR rt)) | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => BitsN.@@ (BitsN.bits(23,0) memdoubleword, BitsN.bits(7,0) (GPR rt)) | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => BitsN.bits(31,0) memdoubleword | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => BitsN.@@ (BitsN.bits(39,32) memdoubleword, BitsN.bits(23,0) (GPR rt)) | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => BitsN.@@ (BitsN.bits(47,32) memdoubleword, BitsN.bits(15,0) (GPR rt)) | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => BitsN.@@ (BitsN.bits(55,32) memdoubleword, BitsN.bits(7,0) (GPR rt)) | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => BitsN.bits(63,32) memdoubleword in write'GPR(BitsN.signExtend 64 temp,rt) end else () end; fun dfn'LWR (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(1,0) vAddr, BitsN.resize_replicate 2 (BigEndianCPU (),2)) val memdoubleword = LoadMemory (WORD, (BitsN.-(WORD,BitsN.@@(BitsN.B(0x0,1),byte)), (false,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then let val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) val temp = case (word,byte) of (BitsN.B(0x0,_),BitsN.B(0x0,_)) => BitsN.bits(31,0) memdoubleword | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => BitsN.@@ (BitsN.bits(31,24) (GPR rt), BitsN.bits(31,8) memdoubleword) | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => BitsN.@@ (BitsN.bits(31,16) (GPR rt), BitsN.bits(31,16) memdoubleword) | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => BitsN.@@ (BitsN.bits(31,8) (GPR rt), BitsN.bits(31,24) memdoubleword) | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => BitsN.bits(63,32) memdoubleword | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => BitsN.@@ (BitsN.bits(31,24) (GPR rt), BitsN.bits(63,40) memdoubleword) | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => BitsN.@@ (BitsN.bits(31,16) (GPR rt), BitsN.bits(63,48) memdoubleword) | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => BitsN.@@ (BitsN.bits(31,8) (GPR rt), BitsN.bits(63,56) memdoubleword) in write'GPR(BitsN.signExtend 64 temp,rt) end else () end; fun dfn'LDL (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val memdoubleword = LoadMemory(DOUBLEWORD,(byte,(false,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then write'GPR (case byte of BitsN.B(0x0,_) => BitsN.@@ (BitsN.bits(7,0) memdoubleword, BitsN.bits(55,0) (GPR rt)) | BitsN.B(0x1,_) => BitsN.@@ (BitsN.bits(15,0) memdoubleword, BitsN.bits(47,0) (GPR rt)) | BitsN.B(0x2,_) => BitsN.@@ (BitsN.bits(23,0) memdoubleword, BitsN.bits(39,0) (GPR rt)) | BitsN.B(0x3,_) => BitsN.@@ (BitsN.bits(31,0) memdoubleword, BitsN.bits(31,0) (GPR rt)) | BitsN.B(0x4,_) => BitsN.@@ (BitsN.bits(39,0) memdoubleword, BitsN.bits(23,0) (GPR rt)) | BitsN.B(0x5,_) => BitsN.@@ (BitsN.bits(47,0) memdoubleword, BitsN.bits(15,0) (GPR rt)) | BitsN.B(0x6,_) => BitsN.@@ (BitsN.bits(55,0) memdoubleword, BitsN.bits(7,0) (GPR rt)) | BitsN.B(0x7,_) => BitsN.bits(63,0) memdoubleword | _ => raise General.Bind,rt) else () end; fun dfn'LDR (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val memdoubleword = LoadMemory (DOUBLEWORD, (BitsN.-(DOUBLEWORD,byte),(false,(vAddr,Option.SOME false)))) in if not (!exceptionSignalled) then write'GPR (case byte of BitsN.B(0x0,_) => BitsN.bits(63,0) memdoubleword | BitsN.B(0x1,_) => BitsN.@@ (BitsN.bits(63,56) (GPR rt), BitsN.bits(63,8) memdoubleword) | BitsN.B(0x2,_) => BitsN.@@ (BitsN.bits(63,48) (GPR rt), BitsN.bits(63,16) memdoubleword) | BitsN.B(0x3,_) => BitsN.@@ (BitsN.bits(63,40) (GPR rt), BitsN.bits(63,24) memdoubleword) | BitsN.B(0x4,_) => BitsN.@@ (BitsN.bits(63,32) (GPR rt), BitsN.bits(63,32) memdoubleword) | BitsN.B(0x5,_) => BitsN.@@ (BitsN.bits(63,24) (GPR rt), BitsN.bits(63,40) memdoubleword) | BitsN.B(0x6,_) => BitsN.@@ (BitsN.bits(63,16) (GPR rt), BitsN.bits(63,48) memdoubleword) | BitsN.B(0x7,_) => BitsN.@@ (BitsN.bits(63,8) (GPR rt), BitsN.bits(63,56) memdoubleword) | _ => raise General.Bind,rt) else () end; fun dfn'SB (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) val _ = StoreMemory(BYTE,(BYTE,(false,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SH (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val bytesel = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.@@ (BitsN.resize_replicate 2 (BigEndianCPU (),2),BitsN.B(0x0,1))) val datadoubleword = BitsN.<<(GPR rt,Nat.*(8,BitsN.toNat bytesel)) val _ = StoreMemory (HALFWORD,(HALFWORD,(true,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SW (base,(rt,offset)) = let val _ = storeWord(base,(rt,(offset,false))) in () end; fun dfn'SD (base,(rt,offset)) = let val _ = storeDoubleword(base,(rt,(offset,false))) in () end; fun dfn'SC (base,(rt,offset)) = let val ret = BitsN.fromBool 64 (storeWord(base,(rt,(offset,true)))) in if not (!exceptionSignalled) then write'GPR(ret,rt) else () end; fun dfn'SCD (base,(rt,offset)) = let val ret = BitsN.fromBool 64 (storeDoubleword(base,(rt,(offset,true)))) in if not (!exceptionSignalled) then write'GPR(ret,rt) else () end; fun dfn'SWL (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(1,0) vAddr, BitsN.resize_replicate 2 (BigEndianCPU (),2)) val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) val datadoubleword = case byte of BitsN.B(0x0,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(31,24) (GPR rt)),64) | BitsN.B(0x1,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(31,16) (GPR rt)),64) | BitsN.B(0x2,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(31,8) (GPR rt)),64) | BitsN.B(0x3,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64) | _ => raise General.Bind val datadoubleword = if word = (BitsN.B(0x1,1)) then BitsN.<<(datadoubleword,32) else datadoubleword val _ = StoreMemory (WORD, (BitsN.fromNat(BitsN.toNat byte,3), (false,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SWR (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(1,0) vAddr, BitsN.resize_replicate 2 (BigEndianCPU (),2)) val word = BitsN.??(BitsN.bits(2,2) vAddr,BigEndianCPU ()) val datadoubleword = case (word,byte) of (BitsN.B(0x0,_),BitsN.B(0x0,_)) => BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64) | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),8) | (BitsN.B(0x0,_),BitsN.B(0x2,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),16) | (BitsN.B(0x0,_),BitsN.B(0x3,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),24) | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64),32) | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),40) | (BitsN.B(0x1,_),BitsN.B(0x2,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),48) | (BitsN.B(0x1,_),BitsN.B(0x3,_)) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),56) val _ = StoreMemory (WORD, (BitsN.-(WORD,BitsN.fromNat(BitsN.toNat byte,3)), (false,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SDL (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val datadoubleword = case byte of BitsN.B(0x0,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,56) (GPR rt)),64) | BitsN.B(0x1,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,48) (GPR rt)),64) | BitsN.B(0x2,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,40) (GPR rt)),64) | BitsN.B(0x3,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,32) (GPR rt)),64) | BitsN.B(0x4,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,24) (GPR rt)),64) | BitsN.B(0x5,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,16) (GPR rt)),64) | BitsN.B(0x6,_) => BitsN.fromNat(BitsN.toNat(BitsN.bits(63,8) (GPR rt)),64) | BitsN.B(0x7,_) => GPR rt | _ => raise General.Bind val _ = StoreMemory (DOUBLEWORD,(byte,(false,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SDR (base,(rt,offset)) = let val vAddr = BitsN.+(BitsN.signExtend 64 offset,GPR base) val byte = BitsN.?? (BitsN.bits(2,0) vAddr, BitsN.resize_replicate 3 (BigEndianCPU (),3)) val datadoubleword = case byte of BitsN.B(0x0,_) => GPR rt | BitsN.B(0x1,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(55,0) (GPR rt)),64),8) | BitsN.B(0x2,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(47,0) (GPR rt)),64),16) | BitsN.B(0x3,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(39,0) (GPR rt)),64),24) | BitsN.B(0x4,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(31,0) (GPR rt)),64),32) | BitsN.B(0x5,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(23,0) (GPR rt)),64),40) | BitsN.B(0x6,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(15,0) (GPR rt)),64),48) | BitsN.B(0x7,_) => BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.bits(7,0) (GPR rt)),64),56) | _ => raise General.Bind val _ = StoreMemory (DOUBLEWORD, (BitsN.-(DOUBLEWORD,byte),(false,(datadoubleword,(vAddr,false))))) in () end; fun dfn'SYNC stype = (); fun dfn'BREAK () = SignalException Bp; fun dfn'SYSCALL () = SignalException Sys; fun dfn'ERET () = if Option.isSome (!BranchDelay) then raise UNPREDICTABLE "ERET follows branch" else if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse (KernelMode ()) then ( if #ERL((#Status((!CP0) : CP0)) : StatusRegister) then ( PC := (BitsN.-(#ErrorEPC((!CP0) : CP0),BitsN.B(0x4,64))) ; let val x0 = #Status((!CP0) : CP0) in CP0 := (CP0_Status_rupd ((!CP0),StatusRegister_ERL_rupd(x0,false))) end ) else ( PC := (BitsN.-(#EPC((!CP0) : CP0),BitsN.B(0x4,64))) ; let val x0 = #Status((!CP0) : CP0) in CP0 := (CP0_Status_rupd ((!CP0),StatusRegister_EXL_rupd(x0,false))) end ) ; LLbit := (Option.SOME false) ) else SignalException CpU; fun dfn'MTC0 (rt,(rd,sel)) = if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse (KernelMode ()) then let val x = (0,(rd,sel)) in write'CPR(GPR rt,x) end else SignalException CpU; fun dfn'DMTC0 (rt,(rd,sel)) = if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse (KernelMode ()) then let val x = (0,(rd,sel)) in write'CPR(GPR rt,x) end else SignalException CpU; fun dfn'MFC0 (rt,(rd,sel)) = if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse (KernelMode ()) then write'GPR (BitsN.signExtend 64 (BitsN.bits(31,0) (CPR(0,(rd,sel)))),rt) else SignalException CpU; fun dfn'DMFC0 (rt,(rd,sel)) = if (#CU0((#Status((!CP0) : CP0)) : StatusRegister)) orelse (KernelMode ()) then write'GPR(CPR(0,(rd,sel)),rt) else SignalException CpU; fun dfn'J instr_index = BranchTo := (Option.SOME (false, BitsN.concat[BitsN.bits(63,28) (!PC),instr_index,BitsN.B(0x0,2)])); fun dfn'JAL instr_index = ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; BranchTo := (Option.SOME (false, BitsN.concat[BitsN.bits(63,28) (!PC),instr_index,BitsN.B(0x0,2)])) ); fun dfn'JR rs = BranchTo := (Option.SOME(false,GPR rs)); fun dfn'JALR (rs,rd) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),rd) ; BranchTo := (Option.SOME(false,temp)) ) end; fun dfn'BEQ (rs,(rt,offset)) = ConditionalBranch((GPR rs) = (GPR rt),offset); fun dfn'BNE (rs,(rt,offset)) = ConditionalBranch(not((GPR rs) = (GPR rt)),offset); fun dfn'BLEZ (rs,offset) = ConditionalBranch(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGTZ (rs,offset) = ConditionalBranch(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZ (rs,offset) = ConditionalBranch(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGEZ (rs,offset) = ConditionalBranch(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZAL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; ConditionalBranch(BitsN.<(temp,BitsN.B(0x0,64)),offset) ) end; fun dfn'BGEZAL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; ConditionalBranch(BitsN.>=(temp,BitsN.B(0x0,64)),offset) ) end; fun dfn'BEQL (rs,(rt,offset)) = ConditionalBranchLikely((GPR rs) = (GPR rt),offset); fun dfn'BNEL (rs,(rt,offset)) = ConditionalBranchLikely(not((GPR rs) = (GPR rt)),offset); fun dfn'BLEZL (rs,offset) = ConditionalBranchLikely(BitsN.<=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGTZL (rs,offset) = ConditionalBranchLikely(BitsN.>(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZL (rs,offset) = ConditionalBranchLikely(BitsN.<(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BGEZL (rs,offset) = ConditionalBranchLikely(BitsN.>=(GPR rs,BitsN.B(0x0,64)),offset); fun dfn'BLTZALL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; ConditionalBranchLikely(BitsN.<(temp,BitsN.B(0x0,64)),offset) ) end; fun dfn'BGEZALL (rs,offset) = let val temp = GPR rs in ( write'GPR(BitsN.+((!PC),BitsN.B(0x8,64)),BitsN.B(0x1F,5)) ; ConditionalBranchLikely(BitsN.>=(temp,BitsN.B(0x0,64)),offset) ) end; val dfn'WAIT = () fun dfn'TLBP () = SignalException ResI; fun dfn'TLBR () = SignalException ResI; fun dfn'TLBWI () = SignalException ResI; fun dfn'TLBWR () = SignalException ResI; fun dfn'CACHE (base,(opn,offset)) = SignalException ResI; fun dfn'RDHWR (rt,rd) = SignalException ResI; fun dfn'ReservedInstruction () = SignalException ResI; fun dfn'Unpredictable () = raise UNPREDICTABLE "Unpredictable instruction"; fun Run v0 = case v0 of BREAK => dfn'BREAK () | ERET => dfn'ERET () | ReservedInstruction => dfn'ReservedInstruction () | SYSCALL => dfn'SYSCALL () | TLBP => dfn'TLBP () | TLBR => dfn'TLBR () | TLBWI => dfn'TLBWI () | TLBWR => dfn'TLBWR () | Unpredictable => dfn'Unpredictable () | WAIT => dfn'WAIT | CACHE v204 => dfn'CACHE v204 | RDHWR v205 => dfn'RDHWR v205 | SYNC v206 => dfn'SYNC v206 | ArithI v1 => (case v1 of ADDI v2 => dfn'ADDI v2 | ADDIU v3 => dfn'ADDIU v3 | ANDI v4 => dfn'ANDI v4 | DADDI v5 => dfn'DADDI v5 | DADDIU v6 => dfn'DADDIU v6 | LUI v7 => dfn'LUI v7 | ORI v8 => dfn'ORI v8 | SLTI v9 => dfn'SLTI v9 | SLTIU v10 => dfn'SLTIU v10 | XORI v11 => dfn'XORI v11) | ArithR v12 => (case v12 of ADD v13 => dfn'ADD v13 | ADDU v14 => dfn'ADDU v14 | AND v15 => dfn'AND v15 | DADD v16 => dfn'DADD v16 | DADDU v17 => dfn'DADDU v17 | DSUB v18 => dfn'DSUB v18 | DSUBU v19 => dfn'DSUBU v19 | MOVN v20 => dfn'MOVN v20 | MOVZ v21 => dfn'MOVZ v21 | NOR v22 => dfn'NOR v22 | OR v23 => dfn'OR v23 | SLT v24 => dfn'SLT v24 | SLTU v25 => dfn'SLTU v25 | SUB v26 => dfn'SUB v26 | SUBU v27 => dfn'SUBU v27 | XOR v28 => dfn'XOR v28) | Branch v29 => (case v29 of BEQ v30 => dfn'BEQ v30 | BEQL v31 => dfn'BEQL v31 | BGEZ v32 => dfn'BGEZ v32 | BGEZAL v33 => dfn'BGEZAL v33 | BGEZALL v34 => dfn'BGEZALL v34 | BGEZL v35 => dfn'BGEZL v35 | BGTZ v36 => dfn'BGTZ v36 | BGTZL v37 => dfn'BGTZL v37 | BLEZ v38 => dfn'BLEZ v38 | BLEZL v39 => dfn'BLEZL v39 | BLTZ v40 => dfn'BLTZ v40 | BLTZAL v41 => dfn'BLTZAL v41 | BLTZALL v42 => dfn'BLTZALL v42 | BLTZL v43 => dfn'BLTZL v43 | BNE v44 => dfn'BNE v44 | BNEL v45 => dfn'BNEL v45 | J v46 => dfn'J v46 | JAL v47 => dfn'JAL v47 | JALR v48 => dfn'JALR v48 | JR v49 => dfn'JR v49) | COP1 v50 => (case v50 of UnknownFPInstruction => dfn'UnknownFPInstruction () | ABS_D v51 => dfn'ABS_D v51 | ABS_S v52 => dfn'ABS_S v52 | ADD_D v53 => dfn'ADD_D v53 | ADD_S v54 => dfn'ADD_S v54 | BC1F v55 => dfn'BC1F v55 | BC1FL v56 => dfn'BC1FL v56 | BC1T v57 => dfn'BC1T v57 | BC1TL v58 => dfn'BC1TL v58 | CEIL_L_D v59 => dfn'CEIL_L_D v59 | CEIL_L_S v60 => dfn'CEIL_L_S v60 | CEIL_W_D v61 => dfn'CEIL_W_D v61 | CEIL_W_S v62 => dfn'CEIL_W_S v62 | CFC1 v63 => dfn'CFC1 v63 | CTC1 v64 => dfn'CTC1 v64 | CVT_D_L v65 => dfn'CVT_D_L v65 | CVT_D_S v66 => dfn'CVT_D_S v66 | CVT_D_W v67 => dfn'CVT_D_W v67 | CVT_L_D v68 => dfn'CVT_L_D v68 | CVT_L_S v69 => dfn'CVT_L_S v69 | CVT_S_D v70 => dfn'CVT_S_D v70 | CVT_S_L v71 => dfn'CVT_S_L v71 | CVT_S_W v72 => dfn'CVT_S_W v72 | CVT_W_D v73 => dfn'CVT_W_D v73 | CVT_W_S v74 => dfn'CVT_W_S v74 | C_cond_D v75 => dfn'C_cond_D v75 | C_cond_S v76 => dfn'C_cond_S v76 | DIV_D v77 => dfn'DIV_D v77 | DIV_S v78 => dfn'DIV_S v78 | DMFC1 v79 => dfn'DMFC1 v79 | DMTC1 v80 => dfn'DMTC1 v80 | FLOOR_L_D v81 => dfn'FLOOR_L_D v81 | FLOOR_L_S v82 => dfn'FLOOR_L_S v82 | FLOOR_W_D v83 => dfn'FLOOR_W_D v83 | FLOOR_W_S v84 => dfn'FLOOR_W_S v84 | LDC1 v85 => dfn'LDC1 v85 | LDXC1 v86 => dfn'LDXC1 v86 | LWC1 v87 => dfn'LWC1 v87 | LWXC1 v88 => dfn'LWXC1 v88 | MADD_D v89 => dfn'MADD_D v89 | MADD_S v90 => dfn'MADD_S v90 | MFC1 v91 => dfn'MFC1 v91 | MOVF v92 => dfn'MOVF v92 | MOVF_D v93 => dfn'MOVF_D v93 | MOVF_S v94 => dfn'MOVF_S v94 | MOVN_D v95 => dfn'MOVN_D v95 | MOVN_S v96 => dfn'MOVN_S v96 | MOVT v97 => dfn'MOVT v97 | MOVT_D v98 => dfn'MOVT_D v98 | MOVT_S v99 => dfn'MOVT_S v99 | MOVZ_D v100 => dfn'MOVZ_D v100 | MOVZ_S v101 => dfn'MOVZ_S v101 | MOV_D v102 => dfn'MOV_D v102 | MOV_S v103 => dfn'MOV_S v103 | MSUB_D v104 => dfn'MSUB_D v104 | MSUB_S v105 => dfn'MSUB_S v105 | MTC1 v106 => dfn'MTC1 v106 | MUL_D v107 => dfn'MUL_D v107 | MUL_S v108 => dfn'MUL_S v108 | NEG_D v109 => dfn'NEG_D v109 | NEG_S v110 => dfn'NEG_S v110 | ROUND_L_D v111 => dfn'ROUND_L_D v111 | ROUND_L_S v112 => dfn'ROUND_L_S v112 | ROUND_W_D v113 => dfn'ROUND_W_D v113 | ROUND_W_S v114 => dfn'ROUND_W_S v114 | SDC1 v115 => dfn'SDC1 v115 | SDXC1 v116 => dfn'SDXC1 v116 | SQRT_D v117 => dfn'SQRT_D v117 | SQRT_S v118 => dfn'SQRT_S v118 | SUB_D v119 => dfn'SUB_D v119 | SUB_S v120 => dfn'SUB_S v120 | SWC1 v121 => dfn'SWC1 v121 | SWXC1 v122 => dfn'SWXC1 v122 | TRUNC_L_D v123 => dfn'TRUNC_L_D v123 | TRUNC_L_S v124 => dfn'TRUNC_L_S v124 | TRUNC_W_D v125 => dfn'TRUNC_W_D v125 | TRUNC_W_S v126 => dfn'TRUNC_W_S v126) | CP v127 => (case v127 of DMFC0 v128 => dfn'DMFC0 v128 | DMTC0 v129 => dfn'DMTC0 v129 | MFC0 v130 => dfn'MFC0 v130 | MTC0 v131 => dfn'MTC0 v131) | Load v132 => (case v132 of LB v133 => dfn'LB v133 | LBU v134 => dfn'LBU v134 | LD v135 => dfn'LD v135 | LDL v136 => dfn'LDL v136 | LDR v137 => dfn'LDR v137 | LH v138 => dfn'LH v138 | LHU v139 => dfn'LHU v139 | LL v140 => dfn'LL v140 | LLD v141 => dfn'LLD v141 | LW v142 => dfn'LW v142 | LWL v143 => dfn'LWL v143 | LWR v144 => dfn'LWR v144 | LWU v145 => dfn'LWU v145) | MultDiv v146 => (case v146 of DDIV v147 => dfn'DDIV v147 | DDIVU v148 => dfn'DDIVU v148 | DIV v149 => dfn'DIV v149 | DIVU v150 => dfn'DIVU v150 | DMULT v151 => dfn'DMULT v151 | DMULTU v152 => dfn'DMULTU v152 | MADD v153 => dfn'MADD v153 | MADDU v154 => dfn'MADDU v154 | MFHI v155 => dfn'MFHI v155 | MFLO v156 => dfn'MFLO v156 | MSUB v157 => dfn'MSUB v157 | MSUBU v158 => dfn'MSUBU v158 | MTHI v159 => dfn'MTHI v159 | MTLO v160 => dfn'MTLO v160 | MUL v161 => dfn'MUL v161 | MULT v162 => dfn'MULT v162 | MULTU v163 => dfn'MULTU v163) | Shift v164 => (case v164 of DSLL v165 => dfn'DSLL v165 | DSLL32 v166 => dfn'DSLL32 v166 | DSLLV v167 => dfn'DSLLV v167 | DSRA v168 => dfn'DSRA v168 | DSRA32 v169 => dfn'DSRA32 v169 | DSRAV v170 => dfn'DSRAV v170 | DSRL v171 => dfn'DSRL v171 | DSRL32 v172 => dfn'DSRL32 v172 | DSRLV v173 => dfn'DSRLV v173 | SLL v174 => dfn'SLL v174 | SLLV v175 => dfn'SLLV v175 | SRA v176 => dfn'SRA v176 | SRAV v177 => dfn'SRAV v177 | SRL v178 => dfn'SRL v178 | SRLV v179 => dfn'SRLV v179) | Store v180 => (case v180 of SB v181 => dfn'SB v181 | SC v182 => dfn'SC v182 | SCD v183 => dfn'SCD v183 | SD v184 => dfn'SD v184 | SDL v185 => dfn'SDL v185 | SDR v186 => dfn'SDR v186 | SH v187 => dfn'SH v187 | SW v188 => dfn'SW v188 | SWL v189 => dfn'SWL v189 | SWR v190 => dfn'SWR v190) | Trap v191 => (case v191 of TEQ v192 => dfn'TEQ v192 | TEQI v193 => dfn'TEQI v193 | TGE v194 => dfn'TGE v194 | TGEI v195 => dfn'TGEI v195 | TGEIU v196 => dfn'TGEIU v196 | TGEU v197 => dfn'TGEU v197 | TLT v198 => dfn'TLT v198 | TLTI v199 => dfn'TLTI v199 | TLTIU v200 => dfn'TLTIU v200 | TLTU v201 => dfn'TLTU v201 | TNE v202 => dfn'TNE v202 | TNEI v203 => dfn'TNEI v203); fun COP1Decode v = COP1 (case boolify'26 v of (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => MFC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (false, (false, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => DMFC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (false, (false, (true, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => CFC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (false, (true, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => MTC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (false, (true, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => DMTC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (false, (true, (true, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => CTC1 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (false, (true, (false, (false, (false, (cc'2, (cc'1, (cc'0, (false, (false, (i'15, (i'14, (i'13, (i'12, (i'11, (i'10, (i'9, (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => BC1F (BitsN.fromBitstring ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) | (false, (true, (false, (false, (false, (cc'2, (cc'1, (cc'0, (false, (true, (i'15, (i'14, (i'13, (i'12, (i'11, (i'10, (i'9, (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => BC1T (BitsN.fromBitstring ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) | (false, (true, (false, (false, (false, (cc'2, (cc'1, (cc'0, (true, (false, (i'15, (i'14, (i'13, (i'12, (i'11, (i'10, (i'9, (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => BC1FL (BitsN.fromBitstring ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) | (false, (true, (false, (false, (false, (cc'2, (cc'1, (cc'0, (true, (true, (i'15, (i'14, (i'13, (i'12, (i'11, (i'10, (i'9, (i'8,(i'7,(i'6,(i'5,(i'4,(i'3,(i'2,(i'1,i'0))))))))))))))))))))))))) => BC1TL (BitsN.fromBitstring ([i'15,i'14,i'13,i'12,i'11,i'10,i'9,i'8,i'7,i'6,i'5,i'4,i'3, i'2,i'1,i'0],16),BitsN.fromBitstring([cc'2,cc'1,cc'0],3)) | (true, (false, (false, (false, (false, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => ADD_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (false, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => SUB_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (false, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(true,false))))))))))))))))))))))))) => MUL_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (false, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(false,(true,true))))))))))))))))))))))))) => DIV_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(true,(false,false))))))))))))))))))))))))) => SQRT_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(false,true))))))))))))))))))))))))) => ABS_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(true,false))))))))))))))))))))))))) => MOV_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(true,true))))))))))))))))))))))))) => NEG_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => ROUND_L_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(false,true))))))))))))))))))))))))) => TRUNC_L_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(true,false))))))))))))))))))))))))) => CEIL_L_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(true,true))))))))))))))))))))))))) => FLOOR_L_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(false,false))))))))))))))))))))))))) => ROUND_W_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(false,true))))))))))))))))))))))))) => TRUNC_W_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(true,false))))))))))))))))))))))))) => CEIL_W_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(true,true))))))))))))))))))))))))) => FLOOR_W_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (cc'2, (cc'1, (cc'0, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => MOVF_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) | (true, (false, (false, (false, (false, (cc'2, (cc'1, (cc'0, (false, (true, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => MOVT_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) | (true, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(true,false))))))))))))))))))))))))) => MOVZ_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (true, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(true,true))))))))))))))))))))))))) => MOVN_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (true, (false, (false, (false, (false, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (cc'2, (cc'1, (cc'0, (false, (false, (true,(true,(false,(cnd'2,(cnd'1,cnd'0))))))))))))))))))))))))) => C_cond_S (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), (BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5), (BitsN.fromBitstring([cnd'2,cnd'1,cnd'0],3), BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) | (true, (false, (false, (false, (true, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => ADD_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (true, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => SUB_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (true, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(true,false))))))))))))))))))))))))) => MUL_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (true, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(false,(true,true))))))))))))))))))))))))) => DIV_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5))) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(true,(false,false))))))))))))))))))))))))) => SQRT_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(false,true))))))))))))))))))))))))) => ABS_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(true,false))))))))))))))))))))))))) => MOV_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(false,(true,(true,true))))))))))))))))))))))))) => NEG_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => ROUND_L_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(false,true))))))))))))))))))))))))) => TRUNC_L_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(true,false))))))))))))))))))))))))) => CEIL_L_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(false,(true,true))))))))))))))))))))))))) => FLOOR_L_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(false,false))))))))))))))))))))))))) => ROUND_W_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(false,true))))))))))))))))))))))))) => TRUNC_W_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(true,false))))))))))))))))))))))))) => CEIL_W_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(false,(true,(true,(true,true))))))))))))))))))))))))) => FLOOR_W_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (cc'2, (cc'1, (cc'0, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => MOVF_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) | (true, (false, (false, (false, (true, (cc'2, (cc'1, (cc'0, (false, (true, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(false,true))))))))))))))))))))))))) => MOVT_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([cc'2,cc'1,cc'0],3))) | (true, (false, (false, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(true,false))))))))))))))))))))))))) => MOVZ_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (true, (false, (false, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(false,(true,(false,(false,(true,true))))))))))))))))))))))))) => MOVN_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (true, (false, (false, (false, (true, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (cc'2, (cc'1, (cc'0, (false, (false, (true,(true,(false,(cnd'2,(cnd'1,cnd'0))))))))))))))))))))))))) => C_cond_D (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), (BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5), (BitsN.fromBitstring([cnd'2,cnd'1,cnd'0],3), BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => CVT_S_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (true, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => CVT_S_W (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (true, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => CVT_S_L (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => CVT_D_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (true, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => CVT_D_W (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (true, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => CVT_D_L (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(true,(false,false))))))))))))))))))))))))) => CVT_W_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(true,(false,false))))))))))))))))))))))))) => CVT_W_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(true,(false,true))))))))))))))))))))))))) => CVT_L_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | (true, (false, (false, (false, (true, (false, (false, (false, (false, (false, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(true,(false,true))))))))))))))))))))))))) => CVT_L_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5)) | _ => UnknownFPInstruction); fun LDC1Decode (base,(offset,ft)) = COP1(LDC1(base,(offset,ft))); fun LWC1Decode (base,(offset,ft)) = COP1(LWC1(base,(offset,ft))); fun SDC1Decode (base,(offset,ft)) = COP1(SDC1(base,(offset,ft))); fun SWC1Decode (base,(offset,ft)) = COP1(SWC1(base,(offset,ft))); fun MOVCIDecode (rs,(rt,rd)) = case boolify'5 rt of (cc'2,(cc'1,(cc'0,(false,false)))) => COP1(MOVF(rd,(rs,BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) | (cc'2,(cc'1,(cc'0,(false,true)))) => COP1(MOVT(rd,(rs,BitsN.fromBitstring([cc'2,cc'1,cc'0],3)))) | _ => ReservedInstruction; fun COP3Decode v = COP1 (case boolify'26 v of (base'4, (base'3, (base'2, (base'1, (base'0, (index'4, (index'3, (index'2, (index'1, (index'0, (false, (false, (false, (false, (false, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,false))))))))))))))))))))))))) => LWXC1 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring ([index'4,index'3,index'2,index'1,index'0],5), BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) | (base'4, (base'3, (base'2, (base'1, (base'0, (index'4, (index'3, (index'2, (index'1, (index'0, (false, (false, (false, (false, (false, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (false,(false,(false,(false,(false,true))))))))))))))))))))))))) => LDXC1 (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring ([index'4,index'3,index'2,index'1,index'0],5), BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) | (base'4, (base'3, (base'2, (base'1, (base'0, (index'4, (index'3, (index'2, (index'1, (index'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(true,(false,(false,false))))))))))))))))))))))))) => SWXC1 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), (BitsN.fromBitstring ([index'4,index'3,index'2,index'1,index'0],5), BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) | (base'4, (base'3, (base'2, (base'1, (base'0, (index'4, (index'3, (index'2, (index'1, (index'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (false, (false, (false, (false, (false, (false,(false,(true,(false,(false,true))))))))))))))))))))))))) => SDXC1 (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), (BitsN.fromBitstring ([index'4,index'3,index'2,index'1,index'0],5), BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5))) | (fr'4, (fr'3, (fr'2, (fr'1, (fr'0, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0, (true,(false,(false,(false,(false,false))))))))))))))))))))))))) => MADD_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) | (fr'4, (fr'3, (fr'2, (fr'1, (fr'0, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(false,(false,(false,true))))))))))))))))))))))))) => MADD_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) | (fr'4, (fr'3, (fr'2, (fr'1, (fr'0, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(true,(false,(false,false))))))))))))))))))))))))) => MSUB_S (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) | (fr'4, (fr'3, (fr'2, (fr'1, (fr'0, (ft'4, (ft'3, (ft'2, (ft'1, (ft'0, (fs'4, (fs'3, (fs'2, (fs'1, (fs'0, (fd'4, (fd'3, (fd'2, (fd'1, (fd'0,(true,(false,(true,(false,(false,true))))))))))))))))))))))))) => MSUB_D (BitsN.fromBitstring([fd'4,fd'3,fd'2,fd'1,fd'0],5), (BitsN.fromBitstring([fr'4,fr'3,fr'2,fr'1,fr'0],5), (BitsN.fromBitstring([fs'4,fs'3,fs'2,fs'1,fs'0],5), BitsN.fromBitstring([ft'4,ft'3,ft'2,ft'1,ft'0],5)))) | _ => UnknownFPInstruction); fun Decode w = case boolify'32 w of (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => MOVCIDecode (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (false,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => Shift (SLL(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => Shift (SRL(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => Shift (SRA(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => Shift (SLLV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => Shift (SRLV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => Shift (SRAV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (hint'4, (hint'3, (hint'2, (hint'1, (hint'0, (false,(false,(true,(false,(false,false))))))))))))))))))))))))))))))) => Branch(JR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (hint'4, (hint'3, (hint'2, (hint'1, (hint'0, (false,(false,(true,(false,(false,true))))))))))))))))))))))))))))))) => Branch (JALR (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(true,(false,(true,false))))))))))))))))))))))))))))))) => ArithR (MOVZ (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => ArithR (MOVN (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (code'14, (code'13, (code'12, (code'11, (code'10, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (false,(false,(true,(true,(false,false))))))))))))))))))))))))))))))) => SYSCALL | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (code'14, (code'13, (code'12, (code'11, (code'10, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (false,(false,(true,(true,(false,true))))))))))))))))))))))))))))))) => BREAK | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => SYNC(BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(true,(false,(false,(false,false))))))))))))))))))))))))))))))) => MultDiv(MFHI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(false,(false,(false,true))))))))))))))))))))))))))))))) => MultDiv(MTHI(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(true,(false,(false,(true,false))))))))))))))))))))))))))))))) => MultDiv(MFLO(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => MultDiv(MTLO(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(true,(false,(true,(false,false))))))))))))))))))))))))))))))) => Shift (DSLLV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(true,(false,(true,(true,false))))))))))))))))))))))))))))))) => Shift (DSRLV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => Shift (DSRAV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => MultDiv (MULT (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(false,(false,true))))))))))))))))))))))))))))))) => MultDiv (MULTU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(false,(true,false))))))))))))))))))))))))))))))) => MultDiv (DIV(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => MultDiv (DIVU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(true,(false,false))))))))))))))))))))))))))))))) => MultDiv (DMULT (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(true,(false,true))))))))))))))))))))))))))))))) => MultDiv (DMULTU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(true,(true,false))))))))))))))))))))))))))))))) => MultDiv (DDIV (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(true,(true,true))))))))))))))))))))))))))))))) => MultDiv (DDIVU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => ArithR (ADD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => ArithR (ADDU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => ArithR (SUB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => ArithR (SUBU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => ArithR (AND(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(true,(false,true))))))))))))))))))))))))))))))) => ArithR (OR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => ArithR (XOR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => ArithR (NOR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(false,(true,false))))))))))))))))))))))))))))))) => ArithR (SLT(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => ArithR (SLTU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(true,(false,false))))))))))))))))))))))))))))))) => ArithR (DADD (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(true,(false,true))))))))))))))))))))))))))))))) => ArithR (DADDU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(true,(true,false))))))))))))))))))))))))))))))) => ArithR (DSUB (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => ArithR (DSUBU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(false,(false,false))))))))))))))))))))))))))))))) => Trap (TGE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(false,(false,true))))))))))))))))))))))))))))))) => Trap (TGEU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(false,(true,false))))))))))))))))))))))))))))))) => Trap (TLT(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => Trap (TLTU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(true,(false,false))))))))))))))))))))))))))))))) => Trap (TEQ(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (code'9, (code'8, (code'7, (code'6, (code'5, (code'4, (code'3, (code'2, (code'1, (code'0, (true,(true,(false,(true,(true,false))))))))))))))))))))))))))))))) => Trap (TNE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => Shift (DSLL (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(false,(true,false))))))))))))))))))))))))))))))) => Shift (DSRL (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => Shift (DSRA (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(true,(false,false))))))))))))))))))))))))))))))) => Shift (DSLL32 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(true,(true,false))))))))))))))))))))))))))))))) => Shift (DSRL32 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (imm5'4, (imm5'3, (imm5'2, (imm5'1, (imm5'0, (true,(true,(true,(true,(true,true))))))))))))))))))))))))))))))) => Shift (DSRA32 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([imm5'4,imm5'3,imm5'2,imm5'1,imm5'0],5)))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLTZ (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGEZ (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (true, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLTZL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (true, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGEZL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TGEI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (false, (false, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TGEIU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (false, (true, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TLTI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (false, (true, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TLTIU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (true, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TEQI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (true, (true, (true, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Trap (TNEI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (true, (true, (true, (true, (true, (true, (false, (false, (_, (_, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Unpredictable | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (true, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLTZAL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (true, (false, (false, (false, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGEZAL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (true, (false, (false, (true, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLTZALL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (true, (false, (false, (true, (true, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGEZALL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (false, (true, (false, (immediate'25, (immediate'24, (immediate'23, (immediate'22, (immediate'21, (immediate'20, (immediate'19, (immediate'18, (immediate'17, (immediate'16, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (J(BitsN.fromBitstring ([immediate'25,immediate'24,immediate'23,immediate'22, immediate'21,immediate'20,immediate'19,immediate'18, immediate'17,immediate'16,immediate'15,immediate'14, immediate'13,immediate'12,immediate'11,immediate'10, immediate'9,immediate'8,immediate'7,immediate'6,immediate'5, immediate'4,immediate'3,immediate'2,immediate'1,immediate'0], 26))) | (false, (false, (false, (false, (true, (true, (immediate'25, (immediate'24, (immediate'23, (immediate'22, (immediate'21, (immediate'20, (immediate'19, (immediate'18, (immediate'17, (immediate'16, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (JAL(BitsN.fromBitstring ([immediate'25,immediate'24,immediate'23,immediate'22, immediate'21,immediate'20,immediate'19,immediate'18, immediate'17,immediate'16,immediate'15,immediate'14, immediate'13,immediate'12,immediate'11,immediate'10, immediate'9,immediate'8,immediate'7,immediate'6, immediate'5,immediate'4,immediate'3,immediate'2, immediate'1,immediate'0],26))) | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => TLBR | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => TLBWI | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(true,(true,false))))))))))))))))))))))))))))))) => TLBWR | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(true,(false,(false,false))))))))))))))))))))))))))))))) => TLBP | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(true,(true,(false,(false,false))))))))))))))))))))))))))))))) => ERET | (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => CP(MFC0 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) | (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => CP(DMFC0 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) | (false, (true, (false, (false, (false, (false, (false, (false, (true, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => CP(MTC0 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) | (false, (true, (false, (false, (false, (false, (false, (false, (true, (false, (true, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(sel'2,(sel'1,sel'0))))))))))))))))))))))))))))))) => CP(DMTC0 (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), BitsN.fromBitstring([sel'2,sel'1,sel'0],3)))) | (false, (false, (false, (true, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLEZ (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (false, (true, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGTZ (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (false, (true, (true, (true, (true, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (LUI(BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (true, (false, (true, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BLEZL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (true, (false, (true, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (false, (false, (false, (false, (false, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BGTZL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16))) | (false, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => MultDiv (MADD (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(false,(false,true))))))))))))))))))))))))))))))) => MultDiv (MADDU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(true,(false,false))))))))))))))))))))))))))))))) => MultDiv (MSUB (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false,(false,(false,(true,(false,true))))))))))))))))))))))))))))))) => MultDiv (MSUBU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5))) | (false, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (false,(false,(false,(false,(true,false))))))))))))))))))))))))))))))) => MultDiv (MUL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)))) | (false, (false, (false, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BEQ(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (false, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BNE(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (ADDI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (ADDIU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (false, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (SLTI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (false, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (SLTIU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (ANDI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (ORI(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (false, (true, (true, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (XORI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (false, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BEQL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (false, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Branch (BNEL (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (true, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (DADDI (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (true, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => ArithI (DADDIU (BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (true, (false, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LDL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (false, (true, (true, (false, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LDR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LH(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (false, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LWL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (false, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LW(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LBU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LHU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (true, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LWR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (false, (true, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LWU(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SB(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SH(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (false, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SWL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (false, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SW(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SDL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SDR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (true, (true, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SWR(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (false, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LL(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (false, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LLD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (false, (true, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Load (LD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (true, (false, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SC(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (true, (true, (false, (false, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SCD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (true, (true, (true, (true, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => Store (SD(BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5), (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4, immediate'3,immediate'2,immediate'1,immediate'0],16)))) | (true, (false, (true, (true, (true, (true, (base'4, (base'3, (base'2, (base'1, (base'0, (opn'4, (opn'3, (opn'2, (opn'1, (opn'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => CACHE (BitsN.fromBitstring([base'4,base'3,base'2,base'1,base'0],5), (BitsN.fromBitstring([opn'4,opn'3,opn'2,opn'1,opn'0],5), BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, immediate'2,immediate'1,immediate'0],16))) | (false, (true, (true, (true, (true, (true, (false, (false, (false, (false, (false, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (rd'4, (rd'3, (rd'2, (rd'1, (rd'0, (false, (false, (false, (false, (false, (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => RDHWR (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5)) | (false, (true, (false, (false, (false, (false, (true, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (false, (true,(false,(false,(false,(false,false))))))))))))))))))))))))))))))) => WAIT | (false, (true, (false, (false, (false, (true, (v'25, (v'24, (v'23, (v'22, (v'21, (v'20, (v'19, (v'18, (v'17, (v'16, (v'15, (v'14, (v'13, (v'12, (v'11, (v'10, (v'9, (v'8, (v'7,(v'6,(v'5,(v'4,(v'3,(v'2,(v'1,v'0))))))))))))))))))))))))))))))) => COP1Decode (BitsN.fromBitstring ([v'25,v'24,v'23,v'22,v'21,v'20,v'19,v'18,v'17,v'16,v'15,v'14, v'13,v'12,v'11,v'10,v'9,v'8,v'7,v'6,v'5,v'4,v'3,v'2,v'1,v'0], 26)) | (false, (true, (false, (false, (true, (true, (v'25, (v'24, (v'23, (v'22, (v'21, (v'20, (v'19, (v'18, (v'17, (v'16, (v'15, (v'14, (v'13, (v'12, (v'11, (v'10, (v'9, (v'8, (v'7,(v'6,(v'5,(v'4,(v'3,(v'2,(v'1,v'0))))))))))))))))))))))))))))))) => COP3Decode (BitsN.fromBitstring ([v'25,v'24,v'23,v'22,v'21,v'20,v'19,v'18,v'17,v'16,v'15,v'14, v'13,v'12,v'11,v'10,v'9,v'8,v'7,v'6,v'5,v'4,v'3,v'2,v'1,v'0], 26)) | (true, (true, (false, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => LWC1Decode (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, immediate'2,immediate'1,immediate'0],16), BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (true, (true, (true, (false, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => SWC1Decode (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, immediate'2,immediate'1,immediate'0],16), BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (true, (true, (false, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => LDC1Decode (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, immediate'2,immediate'1,immediate'0],16), BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | (true, (true, (true, (true, (false, (true, (rs'4, (rs'3, (rs'2, (rs'1, (rs'0, (rt'4, (rt'3, (rt'2, (rt'1, (rt'0, (immediate'15, (immediate'14, (immediate'13, (immediate'12, (immediate'11, (immediate'10, (immediate'9, (immediate'8, (immediate'7, (immediate'6, (immediate'5, (immediate'4, (immediate'3, (immediate'2,(immediate'1,immediate'0))))))))))))))))))))))))))))))) => SDC1Decode (BitsN.fromBitstring([rt'4,rt'3,rt'2,rt'1,rt'0],5), (BitsN.fromBitstring ([immediate'15,immediate'14,immediate'13,immediate'12, immediate'11,immediate'10,immediate'9,immediate'8, immediate'7,immediate'6,immediate'5,immediate'4,immediate'3, immediate'2,immediate'1,immediate'0],16), BitsN.fromBitstring([rs'4,rs'3,rs'2,rs'1,rs'0],5))) | _ => ReservedInstruction; fun Next () = ( case Fetch () of Option.SOME w => Run(Decode w) | NONE => () ; case ((!BranchDelay),(!BranchTo)) of (NONE,NONE) => PC := (BitsN.+((!PC),BitsN.B(0x4,64))) | (NONE,Option.SOME(true,addr)) => ( BranchDelay := (Option.SOME NONE); BranchTo := NONE; PC := addr ) | (NONE,Option.SOME(false,addr)) => ( BranchDelay := (Option.SOME(Option.SOME addr)) ; BranchTo := NONE ; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) | (Option.SOME NONE,NONE) => ( BranchDelay := NONE; PC := (BitsN.+((!PC),BitsN.B(0x4,64))) ) | (Option.SOME(Option.SOME addr),NONE) => ( BranchDelay := NONE; PC := addr ) | _ => raise UNPREDICTABLE "Branch follows branch" ; exceptionSignalled := false ; CP0 := (CP0_Count_rupd((!CP0),BitsN.+(#Count((!CP0) : CP0),BitsN.B(0x1,32)))) ); fun cpr r = "c0_" ^ (case r of BitsN.B(0x0,_) => "index" | BitsN.B(0x1,_) => "random" | BitsN.B(0x2,_) => "entrylo0" | BitsN.B(0x3,_) => "entrylo1" | BitsN.B(0x4,_) => "context" | BitsN.B(0x5,_) => "pagemask" | BitsN.B(0x6,_) => "wired" | BitsN.B(0x7,_) => "hwrena" | BitsN.B(0x8,_) => "badvaddr" | BitsN.B(0x9,_) => "count" | BitsN.B(0xA,_) => "entryhi" | BitsN.B(0xB,_) => "compare" | BitsN.B(0xC,_) => "status" | BitsN.B(0xD,_) => "cause" | BitsN.B(0xE,_) => "epc" | BitsN.B(0xF,_) => "prid" | BitsN.B(0x10,_) => "config" | BitsN.B(0x11,_) => "lladdr" | BitsN.B(0x12,_) => "watchlo" | BitsN.B(0x13,_) => "watchhi" | BitsN.B(0x14,_) => "xcontext" | BitsN.B(0x15,_) => "21" | BitsN.B(0x16,_) => "22" | BitsN.B(0x17,_) => "debug" | BitsN.B(0x18,_) => "depc" | BitsN.B(0x19,_) => "perfcnt" | BitsN.B(0x1A,_) => "errctl" | BitsN.B(0x1B,_) => "cacheerr" | BitsN.B(0x1C,_) => "taglo" | BitsN.B(0x1D,_) => "taghi" | BitsN.B(0x1E,_) => "errorepc" | BitsN.B(0x1F,_) => "kscratch" | _ => raise General.Bind); fun reg_name n = "$" ^ (case n of BitsN.B(0x0,_) => "zero" | BitsN.B(0x1,_) => "at" | BitsN.B(0x2,_) => "v0" | BitsN.B(0x3,_) => "v1" | BitsN.B(0x4,_) => "a0" | BitsN.B(0x5,_) => "a1" | BitsN.B(0x6,_) => "a2" | BitsN.B(0x7,_) => "a3" | BitsN.B(0x8,_) => "t0" | BitsN.B(0x9,_) => "t1" | BitsN.B(0xA,_) => "t2" | BitsN.B(0xB,_) => "t3" | BitsN.B(0xC,_) => "t4" | BitsN.B(0xD,_) => "t5" | BitsN.B(0xE,_) => "t6" | BitsN.B(0xF,_) => "t7" | BitsN.B(0x10,_) => "s0" | BitsN.B(0x11,_) => "s1" | BitsN.B(0x12,_) => "s2" | BitsN.B(0x13,_) => "s3" | BitsN.B(0x14,_) => "s4" | BitsN.B(0x15,_) => "s5" | BitsN.B(0x16,_) => "s6" | BitsN.B(0x17,_) => "s7" | BitsN.B(0x18,_) => "t8" | BitsN.B(0x19,_) => "t9" | BitsN.B(0x1A,_) => "k0" | BitsN.B(0x1B,_) => "k1" | BitsN.B(0x1C,_) => "gp" | BitsN.B(0x1D,_) => "sp" | BitsN.B(0x1E,_) => "fp" | BitsN.B(0x1F,_) => "ra" | _ => raise General.Bind); fun op1i N (s,n) = String.concat [L3.padRightString(#" ",(12,s ^ " ")), if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x",BitsN.toHexString n]; fun op1ai N (s,n) = String.concat [L3.padRightString(#" ",(12,s ^ " ")), if BitsN.<+ (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; fun op1lai N (s,n) = String.concat [L3.padRightString(#" ",(12,s ^ " ")), if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; fun op1r (s,n) = (L3.padRightString(#" ",(12,s ^ " "))) ^ (reg_name n); fun op1ri N (s,(r1,n)) = String.concat [op1r(s,r1),", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", BitsN.toHexString n]; fun op1rai N (s,(r1,n)) = String.concat [op1r(s,r1),", ", if BitsN.<+ (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; fun op1rlai N (s,(r1,n)) = String.concat [op1r(s,r1),", ", if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; fun op2r (s,(r1,r2)) = String.concat[op1r(s,r1),", ",reg_name r2]; fun op2ri N (s,(r1,(r2,n))) = String.concat [op2r(s,(r1,r2)),", ", if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x",BitsN.toHexString n]; fun op2rai N (s,(r1,(r2,n))) = String.concat [op2r(s,(r1,r2)),", ", if BitsN.<+ (BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString(BitsN.<<(BitsN.fromNat(BitsN.toNat n,32),2))]; fun op2rlai N (s,(r1,(r2,n))) = String.concat [op2r(s,(r1,r2)),", ", if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2), BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(n,BitsN.BV(0x1,N))),32),2))]; fun op3r (s,(r1,(r2,r3))) = String.concat[op2r(s,(r1,r2)),", ",reg_name r3]; fun op2roi N (s,(r1,(r2,n))) = String.concat [op1r(s,r1),", ",cpr r2, if n = (BitsN.BV(0x0,N)) then "" else String.concat [", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", BitsN.toHexString n]]; fun opmem N (s,(r1,(r2,n))) = String.concat[op1ri N (s,(r1,n)),"(",reg_name r2,")"]; fun op1fpr (s,n) = String.concat [L3.padRightString(#" ",(12,s ^ " ")),"$f",Nat.toString(BitsN.toNat n)]; fun op1fpri N (s,(r1,n)) = String.concat [op1fpr(s,r1),", ",if BitsN.<+(n,BitsN.BV(0xA,N)) then "" else "0x", BitsN.toHexString n]; fun op2fpr (s,(r1,r2)) = String.concat[op1fpr(s,r1),", ","$f",Nat.toString(BitsN.toNat r2)]; fun op2rfpr (s,(r1,r2)) = String.concat[op1r(s,r1),", ","$f",Nat.toString(BitsN.toNat r2)]; fun op2rcfpr (s,(r1,r2)) = String.concat[op1r(s,r1),", $",Nat.toString(BitsN.toNat r2)]; fun op2ccfpr (s,(r1,(r2,n))) = String.concat [L3.padRightString(#" ",(12,s ^ " ")), if n = (BitsN.B(0x0,3)) then "" else String.concat["$fcc",Nat.toString(BitsN.toNat n),", "], "$f" ^ (Nat.toString(BitsN.toNat r1)),", ","$f", Nat.toString(BitsN.toNat r2)]; fun op3fpr (s,(r1,(r2,r3))) = String.concat[op2fpr(s,(r1,r2)),", ","$f",Nat.toString(BitsN.toNat r3)]; fun op4fpr (s,(r1,(r2,(r3,r4)))) = String.concat [op3fpr(s,(r1,(r2,r3))),", ","$f",Nat.toString(BitsN.toNat r4)]; fun opfpmem N (s,(r1,(r2,n))) = String.concat[op1fpri N (s,(r1,n)),"(",reg_name r2,")"]; fun opfpmem2 (s,(r1,(r2,r3))) = String.concat[op1fpr(s,r1),", ",reg_name r3,"(",reg_name r2,")"]; fun COP1Encode j = case j of MFC1(rt,fs) => BitsN.concat[BitsN.B(0x220,11),rt,fs,BitsN.B(0x0,11)] | DMFC1(rt,fs) => BitsN.concat[BitsN.B(0x221,11),rt,fs,BitsN.B(0x0,11)] | CFC1(rt,fs) => BitsN.concat[BitsN.B(0x222,11),rt,fs,BitsN.B(0x0,11)] | MTC1(rt,fs) => BitsN.concat[BitsN.B(0x224,11),rt,fs,BitsN.B(0x0,11)] | DMTC1(rt,fs) => BitsN.concat[BitsN.B(0x225,11),rt,fs,BitsN.B(0x0,11)] | CTC1(rt,fs) => BitsN.concat[BitsN.B(0x226,11),rt,fs,BitsN.B(0x0,11)] | BC1F(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x0,2),i] | BC1T(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x1,2),i] | BC1FL(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x2,2),i] | BC1TL(i,cc) => BitsN.concat[BitsN.B(0x228,11),cc,BitsN.B(0x3,2),i] | ADD_S(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x0,6)] | SUB_S(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x1,6)] | MUL_S(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x2,6)] | DIV_S(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x230,11),ft,fs,fd,BitsN.B(0x3,6)] | SQRT_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x4,6)] | ABS_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x5,6)] | MOV_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x6,6)] | NEG_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x7,6)] | ROUND_L_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x8,6)] | TRUNC_L_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x9,6)] | CEIL_L_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xA,6)] | FLOOR_L_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xB,6)] | ROUND_W_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xC,6)] | TRUNC_W_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xD,6)] | CEIL_W_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xE,6)] | FLOOR_W_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0xF,6)] | MOVF_S(fd,(fs,cc)) => BitsN.concat [BitsN.B(0x230,11),cc,BitsN.B(0x0,2),fs,fd,BitsN.B(0x11,6)] | MOVT_S(fd,(fs,cc)) => BitsN.concat [BitsN.B(0x230,11),cc,BitsN.B(0x1,2),fs,fd,BitsN.B(0x11,6)] | MOVZ_S(fd,(fs,rt)) => BitsN.concat[BitsN.B(0x230,11),rt,fs,fd,BitsN.B(0x12,6)] | MOVN_S(fd,(fs,rt)) => BitsN.concat[BitsN.B(0x230,11),rt,fs,fd,BitsN.B(0x13,6)] | C_cond_S(fs,(ft,(cnd,cc))) => BitsN.concat[BitsN.B(0x230,11),ft,fs,cc,BitsN.B(0x6,5),cnd] | ADD_D(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x0,6)] | SUB_D(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x1,6)] | MUL_D(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x2,6)] | DIV_D(fd,(fs,ft)) => BitsN.concat[BitsN.B(0x231,11),ft,fs,fd,BitsN.B(0x3,6)] | SQRT_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x4,6)] | ABS_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x5,6)] | MOV_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x6,6)] | NEG_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x7,6)] | ROUND_L_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x8,6)] | TRUNC_L_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x9,6)] | CEIL_L_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xA,6)] | FLOOR_L_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xB,6)] | ROUND_W_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xC,6)] | TRUNC_W_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xD,6)] | CEIL_W_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xE,6)] | FLOOR_W_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0xF,6)] | MOVF_D(fd,(fs,cc)) => BitsN.concat [BitsN.B(0x231,11),cc,BitsN.B(0x0,2),fs,fd,BitsN.B(0x11,6)] | MOVT_D(fd,(fs,cc)) => BitsN.concat [BitsN.B(0x231,11),cc,BitsN.B(0x1,2),fs,fd,BitsN.B(0x11,6)] | MOVZ_D(fd,(fs,rt)) => BitsN.concat[BitsN.B(0x231,11),rt,fs,fd,BitsN.B(0x12,6)] | MOVN_D(fd,(fs,rt)) => BitsN.concat[BitsN.B(0x231,11),rt,fs,fd,BitsN.B(0x13,6)] | C_cond_D(fs,(ft,(cnd,cc))) => BitsN.concat[BitsN.B(0x231,11),ft,fs,cc,BitsN.B(0x6,5),cnd] | CVT_S_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x20,6)] | CVT_S_W(fd,fs) => BitsN.concat[BitsN.B(0x4680,16),fs,fd,BitsN.B(0x20,6)] | CVT_S_L(fd,fs) => BitsN.concat[BitsN.B(0x46A0,16),fs,fd,BitsN.B(0x20,6)] | CVT_D_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x21,6)] | CVT_D_W(fd,fs) => BitsN.concat[BitsN.B(0x4680,16),fs,fd,BitsN.B(0x21,6)] | CVT_D_L(fd,fs) => BitsN.concat[BitsN.B(0x46A0,16),fs,fd,BitsN.B(0x21,6)] | CVT_W_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x24,6)] | CVT_W_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x24,6)] | CVT_L_S(fd,fs) => BitsN.concat[BitsN.B(0x4600,16),fs,fd,BitsN.B(0x25,6)] | CVT_L_D(fd,fs) => BitsN.concat[BitsN.B(0x4620,16),fs,fd,BitsN.B(0x25,6)] | LDC1(base,(offset,ft)) => BitsN.concat[BitsN.B(0x35,6),base,ft,offset] | LWC1(base,(offset,ft)) => BitsN.concat[BitsN.B(0x31,6),base,ft,offset] | SDC1(base,(offset,ft)) => BitsN.concat[BitsN.B(0x3D,6),base,ft,offset] | SWC1(base,(offset,ft)) => BitsN.concat[BitsN.B(0x39,6),base,ft,offset] | LWXC1(fd,(index,base)) => BitsN.concat [BitsN.B(0x13,6),base,index,BitsN.B(0x0,5),fd,BitsN.B(0x0,6)] | LDXC1(fd,(index,base)) => BitsN.concat [BitsN.B(0x13,6),base,index,BitsN.B(0x0,5),fd,BitsN.B(0x1,6)] | SWXC1(fs,(index,base)) => BitsN.concat[BitsN.B(0x13,6),base,index,fs,BitsN.B(0x8,11)] | SDXC1(fs,(index,base)) => BitsN.concat[BitsN.B(0x13,6),base,index,fs,BitsN.B(0x9,11)] | MADD_S(fd,(fr,(fs,ft))) => BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x20,6)] | MADD_D(fd,(fr,(fs,ft))) => BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x21,6)] | MSUB_S(fd,(fr,(fs,ft))) => BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x28,6)] | MSUB_D(fd,(fr,(fs,ft))) => BitsN.concat[BitsN.B(0x13,6),fr,ft,fs,fd,BitsN.B(0x29,6)] | MOVF(rd,(rs,cc)) => BitsN.concat[BitsN.B(0x0,6),rs,cc,BitsN.B(0x0,2),rd,BitsN.B(0x1,11)] | MOVT(rd,(rs,cc)) => BitsN.concat[BitsN.B(0x0,6),rs,cc,BitsN.B(0x1,2),rd,BitsN.B(0x1,11)] | UnknownFPInstruction => BitsN.B(0x0,32); fun form1 (rs,(rt,(rd,(imm5,function)))) = BitsN.concat[BitsN.B(0x0,6),rs,rt,rd,imm5,function]; fun form2 (rs,(function,imm)) = BitsN.concat[BitsN.B(0x1,6),rs,function,imm]; fun form3 (function,(rt,(rd,sel))) = BitsN.concat[BitsN.B(0x10,6),function,rt,rd,BitsN.B(0x0,8),sel]; fun form4 (function,(rs,(rt,imm))) = BitsN.concat[function,rs,rt,imm]; fun form5 (rs,(rt,(rd,function))) = BitsN.concat[BitsN.B(0x1C,6),rs,rt,rd,BitsN.B(0x0,5),function]; fun form6 (rt,(rd,function)) = BitsN.concat [BitsN.B(0x1F,6),BitsN.B(0x0,5),rt,rd,BitsN.B(0x0,5),function]; fun Encode i = case i of Shift(SLL(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x0,6))))) | Shift(SRL(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x2,6))))) | Shift(SRA(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3,6))))) | Shift(SLLV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x4,6))))) | Shift(SRLV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x6,6))))) | Shift(SRAV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x7,6))))) | Branch(JR rs) => form1 (rs, (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x8,6))))) | Branch(JALR(rs,rd)) => form1(rs,(BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x9,6))))) | MultDiv(MFHI rd) => form1 (BitsN.B(0x0,5), (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x10,6))))) | MultDiv(MTHI rs) => form1 (rs, (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x11,6))))) | MultDiv(MFLO rd) => form1 (BitsN.B(0x0,5), (BitsN.B(0x0,5),(rd,(BitsN.B(0x0,5),BitsN.B(0x12,6))))) | MultDiv(MTLO rs) => form1 (rs, (BitsN.B(0x0,5),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x13,6))))) | Shift(DSLLV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x14,6))))) | Shift(DSRLV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x16,6))))) | Shift(DSRAV(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x17,6))))) | MultDiv(MADD(rs,rt)) => form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x0,6)))) | MultDiv(MADDU(rs,rt)) => form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x1,6)))) | MultDiv(MSUB(rs,rt)) => form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x4,6)))) | MultDiv(MSUBU(rs,rt)) => form5(rs,(rt,(BitsN.B(0x0,5),BitsN.B(0x5,6)))) | MultDiv(MUL(rs,(rt,rd))) => form5(rs,(rt,(rd,BitsN.B(0x2,6)))) | MultDiv(MULT(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x18,6))))) | MultDiv(MULTU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x19,6))))) | MultDiv(DIV(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1A,6))))) | MultDiv(DIVU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1B,6))))) | MultDiv(DMULT(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1C,6))))) | MultDiv(DMULTU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1D,6))))) | MultDiv(DDIV(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1E,6))))) | MultDiv(DDIVU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1F,6))))) | ArithR(MOVZ(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0xA,6))))) | ArithR(MOVN(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0xB,6))))) | ArithR(ADD(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x20,6))))) | ArithR(ADDU(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x21,6))))) | ArithR(SUB(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x22,6))))) | ArithR(SUBU(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x23,6))))) | ArithR(AND(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x24,6))))) | ArithR(OR(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x25,6))))) | ArithR(XOR(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x26,6))))) | ArithR(NOR(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x27,6))))) | ArithR(SLT(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2A,6))))) | ArithR(SLTU(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2B,6))))) | ArithR(DADD(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2C,6))))) | ArithR(DADDU(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2D,6))))) | ArithR(DSUB(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2E,6))))) | ArithR(DSUBU(rs,(rt,rd))) => form1(rs,(rt,(rd,(BitsN.B(0x0,5),BitsN.B(0x2F,6))))) | Trap(TGE(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x30,6))))) | Trap(TGEU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x31,6))))) | Trap(TLT(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x32,6))))) | Trap(TLTU(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x33,6))))) | Trap(TEQ(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x34,6))))) | Trap(TNE(rs,rt)) => form1(rs,(rt,(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x36,6))))) | Shift(DSLL(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x38,6))))) | Shift(DSRL(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3A,6))))) | Shift(DSRA(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3B,6))))) | Shift(DSLL32(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3C,6))))) | Shift(DSRL32(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3E,6))))) | Shift(DSRA32(rt,(rd,imm5))) => form1(BitsN.B(0x0,5),(rt,(rd,(imm5,BitsN.B(0x3F,6))))) | Branch(BLTZ(rs,imm)) => form2(rs,(BitsN.B(0x0,5),imm)) | Branch(BGEZ(rs,imm)) => form2(rs,(BitsN.B(0x1,5),imm)) | Branch(BLTZL(rs,imm)) => form2(rs,(BitsN.B(0x2,5),imm)) | Branch(BGEZL(rs,imm)) => form2(rs,(BitsN.B(0x3,5),imm)) | Trap(TGEI(rs,imm)) => form2(rs,(BitsN.B(0x8,5),imm)) | Trap(TGEIU(rs,imm)) => form2(rs,(BitsN.B(0x9,5),imm)) | Trap(TLTI(rs,imm)) => form2(rs,(BitsN.B(0xA,5),imm)) | Trap(TLTIU(rs,imm)) => form2(rs,(BitsN.B(0xB,5),imm)) | Trap(TEQI(rs,imm)) => form2(rs,(BitsN.B(0xC,5),imm)) | Trap(TNEI(rs,imm)) => form2(rs,(BitsN.B(0xE,5),imm)) | Branch(BLTZAL(rs,imm)) => form2(rs,(BitsN.B(0x10,5),imm)) | Branch(BGEZAL(rs,imm)) => form2(rs,(BitsN.B(0x11,5),imm)) | Branch(BLTZALL(rs,imm)) => form2(rs,(BitsN.B(0x12,5),imm)) | Branch(BGEZALL(rs,imm)) => form2(rs,(BitsN.B(0x13,5),imm)) | Branch(J imm) => BitsN.@@(BitsN.B(0x2,6),imm) | Branch(JAL imm) => BitsN.@@(BitsN.B(0x3,6),imm) | CP(MFC0(rt,(rd,sel))) => form3(BitsN.B(0x0,5),(rt,(rd,sel))) | CP(DMFC0(rt,(rd,sel))) => form3(BitsN.B(0x1,5),(rt,(rd,sel))) | CP(MTC0(rt,(rd,sel))) => form3(BitsN.B(0x4,5),(rt,(rd,sel))) | CP(DMTC0(rt,(rd,sel))) => form3(BitsN.B(0x5,5),(rt,(rd,sel))) | Branch(BEQ(rs,(rt,imm))) => form4(BitsN.B(0x4,6),(rs,(rt,imm))) | Branch(BNE(rs,(rt,imm))) => form4(BitsN.B(0x5,6),(rs,(rt,imm))) | Branch(BLEZ(rs,imm)) => form4(BitsN.B(0x6,6),(rs,(BitsN.B(0x0,5),imm))) | Branch(BGTZ(rs,imm)) => form4(BitsN.B(0x7,6),(rs,(BitsN.B(0x0,5),imm))) | ArithI(ADDI(rs,(rt,imm))) => form4(BitsN.B(0x8,6),(rs,(rt,imm))) | ArithI(ADDIU(rs,(rt,imm))) => form4(BitsN.B(0x9,6),(rs,(rt,imm))) | ArithI(SLTI(rs,(rt,imm))) => form4(BitsN.B(0xA,6),(rs,(rt,imm))) | ArithI(SLTIU(rs,(rt,imm))) => form4(BitsN.B(0xB,6),(rs,(rt,imm))) | ArithI(ANDI(rs,(rt,imm))) => form4(BitsN.B(0xC,6),(rs,(rt,imm))) | ArithI(ORI(rs,(rt,imm))) => form4(BitsN.B(0xD,6),(rs,(rt,imm))) | ArithI(XORI(rs,(rt,imm))) => form4(BitsN.B(0xE,6),(rs,(rt,imm))) | ArithI(LUI(rt,imm)) => form4(BitsN.B(0xF,6),(BitsN.B(0x0,5),(rt,imm))) | Branch(BEQL(rs,(rt,imm))) => form4(BitsN.B(0x14,6),(rs,(rt,imm))) | Branch(BNEL(rs,(rt,imm))) => form4(BitsN.B(0x15,6),(rs,(rt,imm))) | Branch(BLEZL(rs,imm)) => form4(BitsN.B(0x16,6),(rs,(BitsN.B(0x0,5),imm))) | Branch(BGTZL(rs,imm)) => form4(BitsN.B(0x17,6),(rs,(BitsN.B(0x0,5),imm))) | ArithI(DADDI(rs,(rt,imm))) => form4(BitsN.B(0x18,6),(rs,(rt,imm))) | ArithI(DADDIU(rs,(rt,imm))) => form4(BitsN.B(0x19,6),(rs,(rt,imm))) | Load(LDL(rs,(rt,imm))) => form4(BitsN.B(0x1A,6),(rs,(rt,imm))) | Load(LDR(rs,(rt,imm))) => form4(BitsN.B(0x1B,6),(rs,(rt,imm))) | Load(LB(rs,(rt,imm))) => form4(BitsN.B(0x20,6),(rs,(rt,imm))) | Load(LH(rs,(rt,imm))) => form4(BitsN.B(0x21,6),(rs,(rt,imm))) | Load(LWL(rs,(rt,imm))) => form4(BitsN.B(0x22,6),(rs,(rt,imm))) | Load(LW(rs,(rt,imm))) => form4(BitsN.B(0x23,6),(rs,(rt,imm))) | Load(LBU(rs,(rt,imm))) => form4(BitsN.B(0x24,6),(rs,(rt,imm))) | Load(LHU(rs,(rt,imm))) => form4(BitsN.B(0x25,6),(rs,(rt,imm))) | Load(LWR(rs,(rt,imm))) => form4(BitsN.B(0x26,6),(rs,(rt,imm))) | Load(LWU(rs,(rt,imm))) => form4(BitsN.B(0x27,6),(rs,(rt,imm))) | Store(SB(rs,(rt,imm))) => form4(BitsN.B(0x28,6),(rs,(rt,imm))) | Store(SH(rs,(rt,imm))) => form4(BitsN.B(0x29,6),(rs,(rt,imm))) | Store(SWL(rs,(rt,imm))) => form4(BitsN.B(0x2A,6),(rs,(rt,imm))) | Store(SW(rs,(rt,imm))) => form4(BitsN.B(0x2B,6),(rs,(rt,imm))) | Store(SDL(rs,(rt,imm))) => form4(BitsN.B(0x2C,6),(rs,(rt,imm))) | Store(SDR(rs,(rt,imm))) => form4(BitsN.B(0x2D,6),(rs,(rt,imm))) | Store(SWR(rs,(rt,imm))) => form4(BitsN.B(0x2E,6),(rs,(rt,imm))) | Load(LL(rs,(rt,imm))) => form4(BitsN.B(0x30,6),(rs,(rt,imm))) | Load(LLD(rs,(rt,imm))) => form4(BitsN.B(0x34,6),(rs,(rt,imm))) | Load(LD(rs,(rt,imm))) => form4(BitsN.B(0x37,6),(rs,(rt,imm))) | Store(SC(rs,(rt,imm))) => form4(BitsN.B(0x38,6),(rs,(rt,imm))) | Store(SCD(rs,(rt,imm))) => form4(BitsN.B(0x3C,6),(rs,(rt,imm))) | Store(SD(rs,(rt,imm))) => form4(BitsN.B(0x3F,6),(rs,(rt,imm))) | CACHE(rs,(opn,imm)) => form4(BitsN.B(0x2F,6),(rs,(opn,imm))) | SYSCALL => BitsN.fromNat(BitsN.toNat(BitsN.B(0xC,6)),32) | BREAK => BitsN.fromNat(BitsN.toNat(BitsN.B(0xD,6)),32) | SYNC imm5 => BitsN.fromNat(BitsN.toNat(BitsN.@@(imm5,BitsN.B(0xF,6))),32) | TLBR => BitsN.B(0x42000001,32) | TLBWI => BitsN.B(0x42000002,32) | TLBWR => BitsN.B(0x42000006,32) | TLBP => BitsN.B(0x42000008,32) | ERET => BitsN.B(0x42000018,32) | RDHWR(rt,rd) => form6(rt,(rd,BitsN.B(0x3B,6))) | WAIT => BitsN.B(0x42000020,32) | Unpredictable => BitsN.B(0x7F00000,32) | COP1 j => COP1Encode j | ReservedInstruction => BitsN.B(0x0,32); fun COP1InstructionToString j = case j of ABS_D(fd,fs) => op2fpr("abs.d",(fd,fs)) | ABS_S(fd,fs) => op2fpr("abs.s",(fd,fs)) | ADD_D(fd,(fs,ft)) => op3fpr("add.d",(fd,(fs,ft))) | ADD_S(fd,(fs,ft)) => op3fpr("add.s",(fd,(fs,ft))) | BC1F(i,cc) => String.concat [L3.padRightString(#" ",(12,"bc1f" ^ " ")), if cc = (BitsN.B(0x0,3)) then "" else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] | BC1FL(i,cc) => String.concat [L3.padRightString(#" ",(12,"bc1fl" ^ " ")), if cc = (BitsN.B(0x0,3)) then "" else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] | BC1T(i,cc) => String.concat [L3.padRightString(#" ",(12,"bc1t" ^ " ")), if cc = (BitsN.B(0x0,3)) then "" else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] | BC1TL(i,cc) => String.concat [L3.padRightString(#" ",(12,"bc1tl" ^ " ")), if cc = (BitsN.B(0x0,3)) then "" else String.concat["$fcc",Nat.toString(BitsN.toNat cc),", "], if BitsN.<+ (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32), 2),BitsN.B(0xA,32)) then "" else "0x", BitsN.toHexString (BitsN.<< (BitsN.fromNat(BitsN.toNat(BitsN.+(i,BitsN.B(0x1,16))),32),2))] | C_cond_D(fs,(ft,(BitsN.B(0x0,3),cc))) => op2ccfpr("c.f.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x1,3),cc))) => op2ccfpr("c.un.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x2,3),cc))) => op2ccfpr("c.eq.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x3,3),cc))) => op2ccfpr("c.ueq.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x4,3),cc))) => op2ccfpr("c.olt.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x5,3),cc))) => op2ccfpr("c.ult.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x6,3),cc))) => op2ccfpr("c.ole.d",(fs,(ft,cc))) | C_cond_D(fs,(ft,(BitsN.B(0x7,3),cc))) => op2ccfpr("c.ule.d",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x0,3),cc))) => op2ccfpr("c.f.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x1,3),cc))) => op2ccfpr("c.un.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x2,3),cc))) => op2ccfpr("c.eq.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x3,3),cc))) => op2ccfpr("c.ueq.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x4,3),cc))) => op2ccfpr("c.olt.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x5,3),cc))) => op2ccfpr("c.ult.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x6,3),cc))) => op2ccfpr("c.ole.s",(fs,(ft,cc))) | C_cond_S(fs,(ft,(BitsN.B(0x7,3),cc))) => op2ccfpr("c.ule.s",(fs,(ft,cc))) | CEIL_L_D(fd,fs) => op2fpr("ceil.l.d",(fd,fs)) | CEIL_L_S(fd,fs) => op2fpr("ceil.l.s",(fd,fs)) | CEIL_W_D(fd,fs) => op2fpr("ceil.w.d",(fd,fs)) | CEIL_W_S(fd,fs) => op2fpr("ceil.w.s",(fd,fs)) | CFC1(rt,fs) => op2rcfpr("cfc1",(rt,fs)) | CTC1(rt,fs) => op2rcfpr("ctc1",(rt,fs)) | CVT_D_L(fd,fs) => op2fpr("cvt.d.l",(fd,fs)) | CVT_D_S(fd,fs) => op2fpr("cvt.d.s",(fd,fs)) | CVT_D_W(fd,fs) => op2fpr("cvt.d.w",(fd,fs)) | CVT_L_D(fd,fs) => op2fpr("cvt.l.d",(fd,fs)) | CVT_L_S(fd,fs) => op2fpr("cvt.l.s",(fd,fs)) | CVT_S_L(fd,fs) => op2fpr("cvt.s.l",(fd,fs)) | CVT_S_D(fd,fs) => op2fpr("cvt.s.d",(fd,fs)) | CVT_S_W(fd,fs) => op2fpr("cvt.s.w",(fd,fs)) | CVT_W_D(fd,fs) => op2fpr("cvt.w.d",(fd,fs)) | CVT_W_S(fd,fs) => op2fpr("cvt.w.s",(fd,fs)) | DIV_D(fd,(fs,ft)) => op3fpr("div.d",(fd,(fs,ft))) | DIV_S(fd,(fs,ft)) => op3fpr("div.s",(fd,(fs,ft))) | DMFC1(rt,fs) => op2rfpr("dmfc1",(rt,fs)) | DMTC1(rt,fs) => op2rfpr("dmtc1",(rt,fs)) | FLOOR_L_D(fd,fs) => op2fpr("floor.l.d",(fd,fs)) | FLOOR_L_S(fd,fs) => op2fpr("floor.l.s",(fd,fs)) | FLOOR_W_D(fd,fs) => op2fpr("floor.w.d",(fd,fs)) | FLOOR_W_S(fd,fs) => op2fpr("floor.w.s",(fd,fs)) | LDC1(ft,(offset,base)) => opfpmem 16 ("ldc1",(ft,(base,offset))) | LDXC1(fs,(index,base)) => opfpmem2("ldxc1",(fs,(base,index))) | LWC1(ft,(offset,base)) => opfpmem 16 ("lwc1",(ft,(base,offset))) | LWXC1(ft,(index,base)) => opfpmem2("lwxc1",(ft,(base,index))) | MFC1(rt,fs) => op2rfpr("mfc1",(rt,fs)) | MADD_D(fd,(fr,(fs,ft))) => op4fpr("madd.d",(fd,(fr,(fs,ft)))) | MADD_S(fd,(fr,(fs,ft))) => op4fpr("madd.s",(fd,(fr,(fs,ft)))) | MSUB_D(fd,(fr,(fs,ft))) => op4fpr("msub.d",(fd,(fr,(fs,ft)))) | MSUB_S(fd,(fr,(fs,ft))) => op4fpr("msub.s",(fd,(fr,(fs,ft)))) | MOV_D(fd,fs) => op2fpr("mov.d",(fd,fs)) | MOV_S(fd,fs) => op2fpr("mov.s",(fd,fs)) | MOVF(rd,(rs,cc)) => String.concat [op2r("movf",(rd,rs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVF_D(fd,(fs,cc)) => String.concat [op2fpr("movf.d",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVF_S(fd,(fs,cc)) => String.concat [op2fpr("movf.s",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVN_D(fd,(fs,rt)) => String.concat[op2fpr("movn.d",(fd,fs)),", ",reg_name rt] | MOVN_S(fd,(fs,rt)) => String.concat[op2fpr("movn.s",(fd,fs)),", ",reg_name rt] | MOVT(rd,(rs,cc)) => String.concat [op2r("movt",(rd,rs)),", ",", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVT_D(fd,(fs,cc)) => String.concat [op2fpr("movt.d",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVT_S(fd,(fs,cc)) => String.concat [op2fpr("movt.s",(fd,fs)),", ","$fcc",Nat.toString(BitsN.toNat cc)] | MOVZ_D(fd,(fs,rt)) => String.concat[op2fpr("movz.d",(fd,fs)),", ",reg_name rt] | MOVZ_S(fd,(fs,rt)) => String.concat[op2fpr("movz.s",(fd,fs)),", ",reg_name rt] | MTC1(rt,fs) => op2rfpr("mtc1",(rt,fs)) | MUL_D(fd,(fs,ft)) => op3fpr("mul.d",(fd,(fs,ft))) | MUL_S(fd,(fs,ft)) => op3fpr("mul.s",(fd,(fs,ft))) | NEG_D(fd,fs) => op2fpr("neg.d",(fd,fs)) | NEG_S(fd,fs) => op2fpr("neg.s",(fd,fs)) | ROUND_L_D(fd,fs) => op2fpr("round.l.d",(fd,fs)) | ROUND_L_S(fd,fs) => op2fpr("round.l.s",(fd,fs)) | ROUND_W_D(fd,fs) => op2fpr("round.w.d",(fd,fs)) | ROUND_W_S(fd,fs) => op2fpr("round.w.s",(fd,fs)) | SDC1(ft,(offset,base)) => opfpmem 16 ("sdc1",(ft,(base,offset))) | SDXC1(fs,(index,base)) => opfpmem2("sdxc1",(fs,(base,index))) | SWC1(ft,(offset,base)) => opfpmem 16 ("swc1",(ft,(base,offset))) | SWXC1(ft,(offset,base)) => opfpmem2("swxc1",(ft,(base,offset))) | SUB_D(fd,(fs,ft)) => op3fpr("sub.d",(fd,(fs,ft))) | SUB_S(fd,(fs,ft)) => op3fpr("sub.s",(fd,(fs,ft))) | SQRT_D(fd,fs) => op2fpr("sqrt.d",(fd,fs)) | SQRT_S(fd,fs) => op2fpr("sqrt.s",(fd,fs)) | TRUNC_L_D(fd,fs) => op2fpr("trunc.l.d",(fd,fs)) | TRUNC_L_S(fd,fs) => op2fpr("trunc.l.s",(fd,fs)) | TRUNC_W_D(fd,fs) => op2fpr("trunc.w.d",(fd,fs)) | TRUNC_W_S(fd,fs) => op2fpr("trunc.w.s",(fd,fs)) | UnknownFPInstruction => "Unknown floating point instruction"; fun instructionToString i = case i of Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,5)))) => "nop" | Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,5)))) => "ssnop" | Shift(SLL(rt,(rd,imm5))) => op2ri 5 ("sll",(rd,(rt,imm5))) | Shift(SRL(rt,(rd,imm5))) => op2ri 5 ("srl",(rd,(rt,imm5))) | Shift(SRA(rt,(rd,imm5))) => op2ri 5 ("sra",(rd,(rt,imm5))) | Shift(SLLV(rs,(rt,rd))) => op3r("sllv",(rd,(rt,rs))) | Shift(SRLV(rs,(rt,rd))) => op3r("srlv",(rd,(rt,rs))) | Shift(SRAV(rs,(rt,rd))) => op3r("srav",(rd,(rt,rs))) | Branch(JR rs) => op1r("jr",rs) | Branch(JALR(rs,rd)) => op2r("jalr",(rd,rs)) | MultDiv(MFHI rd) => op1r("mfhi",rd) | MultDiv(MTHI rd) => op1r("mthi",rd) | MultDiv(MFLO rs) => op1r("mflo",rs) | MultDiv(MTLO rs) => op1r("mtlo",rs) | Shift(DSLLV(rs,(rt,rd))) => op3r("dsllv",(rd,(rt,rs))) | Shift(DSRLV(rs,(rt,rd))) => op3r("dsrlv",(rd,(rt,rs))) | Shift(DSRAV(rs,(rt,rd))) => op3r("dsrav",(rd,(rt,rs))) | MultDiv(MADD(rs,rt)) => op2r("madd",(rs,rt)) | MultDiv(MADDU(rs,rt)) => op2r("maddu",(rs,rt)) | MultDiv(MSUB(rs,rt)) => op2r("msub",(rs,rt)) | MultDiv(MSUBU(rs,rt)) => op2r("msubu",(rs,rt)) | MultDiv(MUL(rs,(rt,rd))) => op3r("mul",(rd,(rs,rt))) | MultDiv(MULT(rs,rt)) => op2r("mult",(rs,rt)) | MultDiv(MULTU(rs,rt)) => op2r("multu",(rs,rt)) | MultDiv(DIV(rs,rt)) => op2r("div",(rs,rt)) | MultDiv(DIVU(rs,rt)) => op2r("divu",(rs,rt)) | MultDiv(DMULT(rs,rt)) => op2r("dmult",(rs,rt)) | MultDiv(DMULTU(rs,rt)) => op2r("dmultu",(rs,rt)) | MultDiv(DDIV(rs,rt)) => op2r("ddiv",(rs,rt)) | MultDiv(DDIVU(rs,rt)) => op2r("ddivu",(rs,rt)) | ArithR(MOVN(rs,(rt,rd))) => op3r("movn",(rd,(rs,rt))) | ArithR(MOVZ(rs,(rt,rd))) => op3r("movz",(rd,(rs,rt))) | ArithR(ADD(rs,(rt,rd))) => op3r("add",(rd,(rs,rt))) | ArithR(ADDU(rs,(rt,rd))) => op3r("addu",(rd,(rs,rt))) | ArithR(SUB(rs,(rt,rd))) => op3r("sub",(rd,(rs,rt))) | ArithR(SUBU(rs,(rt,rd))) => op3r("subu",(rd,(rs,rt))) | ArithR(AND(rs,(rt,rd))) => op3r("and",(rd,(rs,rt))) | ArithR(OR(rs,(rt,rd))) => op3r("or",(rd,(rs,rt))) | ArithR(XOR(rs,(rt,rd))) => op3r("xor",(rd,(rs,rt))) | ArithR(NOR(rs,(rt,rd))) => op3r("nor",(rd,(rs,rt))) | ArithR(SLT(rs,(rt,rd))) => op3r("slt",(rd,(rs,rt))) | ArithR(SLTU(rs,(rt,rd))) => op3r("sltu",(rd,(rs,rt))) | ArithR(DADD(rs,(rt,rd))) => op3r("dadd",(rd,(rs,rt))) | ArithR(DADDU(rs,(rt,rd))) => op3r("daddu",(rd,(rs,rt))) | ArithR(DSUB(rs,(rt,rd))) => op3r("dsub",(rd,(rs,rt))) | ArithR(DSUBU(rs,(rt,rd))) => op3r("dsubu",(rd,(rs,rt))) | Trap(TGE(rs,rt)) => op2r("tge",(rs,rt)) | Trap(TGEU(rs,rt)) => op2r("tgeu",(rs,rt)) | Trap(TLT(rs,rt)) => op2r("tlt",(rs,rt)) | Trap(TLTU(rs,rt)) => op2r("tltu",(rs,rt)) | Trap(TEQ(rs,rt)) => op2r("teq",(rs,rt)) | Trap(TNE(rs,rt)) => op2r("tne",(rs,rt)) | Shift(DSLL(rt,(rd,imm5))) => op2ri 5 ("dsll",(rd,(rt,imm5))) | Shift(DSRL(rt,(rd,imm5))) => op2ri 5 ("dsrl",(rd,(rt,imm5))) | Shift(DSRA(rt,(rd,imm5))) => op2ri 5 ("dsra",(rd,(rt,imm5))) | Shift(DSLL32(rt,(rd,imm5))) => op2ri 5 ("dsll32",(rd,(rt,imm5))) | Shift(DSRL32(rt,(rd,imm5))) => op2ri 5 ("dsrl32",(rd,(rt,imm5))) | Shift(DSRA32(rt,(rd,imm5))) => op2ri 5 ("dsra32",(rd,(rt,imm5))) | Branch(BLTZ(rs,imm)) => op1rai 16 ("bltz",(rs,imm)) | Branch(BGEZ(rs,imm)) => op1rai 16 ("bgez",(rs,imm)) | Branch(BLTZL(rs,imm)) => op1rlai 16 ("bltzl",(rs,imm)) | Branch(BGEZL(rs,imm)) => op1rlai 16 ("bgezl",(rs,imm)) | Trap(TGEI(rs,imm)) => op1ri 16 ("tgei",(rs,imm)) | Trap(TGEIU(rs,imm)) => op1ri 16 ("tgeiu",(rs,imm)) | Trap(TLTI(rs,imm)) => op1ri 16 ("tlti",(rs,imm)) | Trap(TLTIU(rs,imm)) => op1ri 16 ("tltiu",(rs,imm)) | Trap(TEQI(rs,imm)) => op1ri 16 ("teqi",(rs,imm)) | Trap(TNEI(rs,imm)) => op1ri 16 ("tnei",(rs,imm)) | Branch(BLTZAL(rs,imm)) => op1rai 16 ("bltzal",(rs,imm)) | Branch(BGEZAL(rs,imm)) => op1rai 16 ("bgezal",(rs,imm)) | Branch(BLTZALL(rs,imm)) => op1rlai 16 ("bltzall",(rs,imm)) | Branch(BGEZALL(rs,imm)) => op1rlai 16 ("bgezall",(rs,imm)) | Branch(J imm) => op1ai 26 ("j",imm) | Branch(JAL imm) => op1ai 26 ("jal",imm) | CP(MFC0(rt,(rd,sel))) => op2roi 3 ("mfc0",(rt,(rd,sel))) | CP(DMFC0(rt,(rd,sel))) => op2roi 3 ("dmfc0",(rt,(rd,sel))) | CP(MTC0(rt,(rd,sel))) => op2roi 3 ("mtc0",(rt,(rd,sel))) | CP(DMTC0(rt,(rd,sel))) => op2roi 3 ("dmtc0",(rt,(rd,sel))) | Branch(BEQ(BitsN.B(0x0,5),(BitsN.B(0x0,5),imm))) => op1ai 16 ("b",imm) | Branch(BEQ(rs,(rt,imm))) => op2rai 16 ("beq",(rs,(rt,imm))) | Branch(BNE(rs,(rt,imm))) => op2rai 16 ("bne",(rs,(rt,imm))) | Branch(BLEZ(rs,imm)) => op1rai 16 ("blez",(rs,imm)) | Branch(BGTZ(rs,imm)) => op1rai 16 ("bgtz",(rs,imm)) | ArithI(ADDI(rs,(rt,imm))) => op2ri 16 ("addi",(rt,(rs,imm))) | ArithI(ADDIU(rs,(rt,imm))) => op2ri 16 ("addiu",(rt,(rs,imm))) | ArithI(SLTI(rs,(rt,imm))) => op2ri 16 ("slti",(rt,(rs,imm))) | ArithI(SLTIU(rs,(rt,imm))) => op2ri 16 ("sltiu",(rt,(rs,imm))) | ArithI(ANDI(rs,(rt,imm))) => op2ri 16 ("andi",(rt,(rs,imm))) | ArithI(ORI(rs,(rt,imm))) => op2ri 16 ("ori",(rt,(rs,imm))) | ArithI(XORI(rs,(rt,imm))) => op2ri 16 ("xori",(rt,(rs,imm))) | ArithI(LUI(rt,imm)) => op1ri 16 ("lui",(rt,imm)) | Branch(BEQL(rs,(rt,imm))) => op2rlai 16 ("beql",(rs,(rt,imm))) | Branch(BNEL(rs,(rt,imm))) => op2rlai 16 ("bnel",(rs,(rt,imm))) | Branch(BLEZL(rs,imm)) => op1rlai 16 ("blezl",(rs,imm)) | Branch(BGTZL(rs,imm)) => op1rlai 16 ("bgtzl",(rs,imm)) | ArithI(DADDI(rs,(rt,imm))) => op2ri 16 ("daddi",(rt,(rs,imm))) | ArithI(DADDIU(rs,(rt,imm))) => op2ri 16 ("daddiu",(rt,(rs,imm))) | Load(LDL(rs,(rt,imm))) => opmem 16 ("ldl",(rt,(rs,imm))) | Load(LDR(rs,(rt,imm))) => opmem 16 ("ldr",(rt,(rs,imm))) | Load(LB(rs,(rt,imm))) => opmem 16 ("lb",(rt,(rs,imm))) | Load(LH(rs,(rt,imm))) => opmem 16 ("lh",(rt,(rs,imm))) | Load(LWL(rs,(rt,imm))) => opmem 16 ("lwl",(rt,(rs,imm))) | Load(LW(rs,(rt,imm))) => opmem 16 ("lw",(rt,(rs,imm))) | Load(LBU(rs,(rt,imm))) => opmem 16 ("lbu",(rt,(rs,imm))) | Load(LHU(rs,(rt,imm))) => opmem 16 ("lhu",(rt,(rs,imm))) | Load(LWR(rs,(rt,imm))) => opmem 16 ("lwr",(rt,(rs,imm))) | Load(LWU(rs,(rt,imm))) => opmem 16 ("lwu",(rt,(rs,imm))) | Store(SB(rs,(rt,imm))) => opmem 16 ("sb",(rt,(rs,imm))) | Store(SH(rs,(rt,imm))) => opmem 16 ("sh",(rt,(rs,imm))) | Store(SWL(rs,(rt,imm))) => opmem 16 ("swl",(rt,(rs,imm))) | Store(SW(rs,(rt,imm))) => opmem 16 ("sw",(rt,(rs,imm))) | Store(SDL(rs,(rt,imm))) => opmem 16 ("sdl",(rt,(rs,imm))) | Store(SDR(rs,(rt,imm))) => opmem 16 ("sdr",(rt,(rs,imm))) | Store(SWR(rs,(rt,imm))) => opmem 16 ("swr",(rt,(rs,imm))) | Load(LL(rs,(rt,imm))) => opmem 16 ("ll",(rt,(rs,imm))) | Load(LLD(rs,(rt,imm))) => opmem 16 ("lld",(rt,(rs,imm))) | Load(LD(rs,(rt,imm))) => opmem 16 ("ld",(rt,(rs,imm))) | Store(SC(rs,(rt,imm))) => opmem 16 ("sc",(rt,(rs,imm))) | Store(SCD(rs,(rt,imm))) => opmem 16 ("scd",(rt,(rs,imm))) | Store(SD(rs,(rt,imm))) => opmem 16 ("sd",(rt,(rs,imm))) | CACHE(rs,(opn,imm)) => String.concat ["cache ", (if BitsN.<+(opn,BitsN.B(0xA,5)) then "" else "0x") ^ (BitsN.toHexString opn),", ", (if BitsN.<+(imm,BitsN.B(0xA,16)) then "" else "0x") ^ (BitsN.toHexString imm),"(",reg_name rs,")"] | COP1 x => COP1InstructionToString x | SYSCALL => "syscall" | BREAK => "break" | SYNC imm5 => String.concat ["sync ",if BitsN.<+(imm5,BitsN.B(0xA,5)) then "" else "0x", BitsN.toHexString imm5] | TLBR => "tlbr" | TLBWI => "tlbwi" | TLBWR => "tlbwr" | TLBP => "tlbp" | ERET => "eret" | RDHWR(rt,rd) => op2r("rdhwr",(rt,rd)) | WAIT => "wait" | Unpredictable => "???" | ReservedInstruction => "???"; fun skipSpaces s = L3.snd(L3.splitl(fn c => Char.isSpace c,s)); fun stripSpaces s = L3.fst(L3.splitr(fn c => Char.isSpace c,skipSpaces s)); fun p_number s = case String.explode(stripSpaces s) of #"0" :: (#"b" :: t) => Nat.fromBinString(String.implode t) | #"0" :: (#"x" :: t) => Nat.fromHexString(String.implode t) | _ => Nat.fromString s; fun p_tokens s = let val (l,r) = L3.splitl (fn c => not(Char.isSpace c), L3.lowercase(L3.snd(L3.splitl(fn c => Char.isSpace c,s)))) val r = L3.uncurry String.fields (fn c => c = #",",r) val r = if ((L3.length r) = 1) andalso ((stripSpaces(List.hd r)) = "") then [] else r in l :: r end; fun p_fp_cc s = case String.explode(stripSpaces s) of #"$" :: (#"f" :: (#"c" :: (#"c" :: r))) => (case Nat.fromString(String.implode r) of Option.SOME n => (if Nat.<(n,8) then Option.SOME(BitsN.fromNat(n,3)) else NONE) | NONE => NONE) | _ => NONE; fun p_fp_reg s = case String.explode(stripSpaces s) of #"$" :: (#"f" :: r) => (case Nat.fromString(String.implode r) of Option.SOME n => (if Nat.<(n,32) then Option.SOME(BitsN.fromNat(n,5)) else NONE) | NONE => NONE) | _ => NONE; fun p_cfp_reg s = case String.explode(stripSpaces s) of #"$" :: r => (case Nat.fromString(String.implode r) of Option.SOME n => (if Nat.<(n,32) then Option.SOME(BitsN.fromNat(n,5)) else NONE) | NONE => NONE) | _ => NONE; fun p_reg s = case String.explode(stripSpaces s) of #"$" :: n => (case String.explode(String.implode n) of [#"z",#"e",#"r",#"o"] => Option.SOME(BitsN.B(0x0,5)) | [#"a",#"t"] => Option.SOME(BitsN.B(0x1,5)) | [#"v",#"0"] => Option.SOME(BitsN.B(0x2,5)) | [#"v",#"1"] => Option.SOME(BitsN.B(0x3,5)) | [#"a",#"0"] => Option.SOME(BitsN.B(0x4,5)) | [#"a",#"1"] => Option.SOME(BitsN.B(0x5,5)) | [#"a",#"2"] => Option.SOME(BitsN.B(0x6,5)) | [#"a",#"3"] => Option.SOME(BitsN.B(0x7,5)) | [#"t",#"0"] => Option.SOME(BitsN.B(0x8,5)) | [#"t",#"1"] => Option.SOME(BitsN.B(0x9,5)) | [#"t",#"2"] => Option.SOME(BitsN.B(0xA,5)) | [#"t",#"3"] => Option.SOME(BitsN.B(0xB,5)) | [#"t",#"4"] => Option.SOME(BitsN.B(0xC,5)) | [#"t",#"5"] => Option.SOME(BitsN.B(0xD,5)) | [#"t",#"6"] => Option.SOME(BitsN.B(0xE,5)) | [#"t",#"7"] => Option.SOME(BitsN.B(0xF,5)) | [#"s",#"0"] => Option.SOME(BitsN.B(0x10,5)) | [#"s",#"1"] => Option.SOME(BitsN.B(0x11,5)) | [#"s",#"2"] => Option.SOME(BitsN.B(0x12,5)) | [#"s",#"3"] => Option.SOME(BitsN.B(0x13,5)) | [#"s",#"4"] => Option.SOME(BitsN.B(0x14,5)) | [#"s",#"5"] => Option.SOME(BitsN.B(0x15,5)) | [#"s",#"6"] => Option.SOME(BitsN.B(0x16,5)) | [#"s",#"7"] => Option.SOME(BitsN.B(0x17,5)) | [#"t",#"8"] => Option.SOME(BitsN.B(0x18,5)) | [#"t",#"9"] => Option.SOME(BitsN.B(0x19,5)) | [#"k",#"0"] => Option.SOME(BitsN.B(0x1A,5)) | [#"k",#"1"] => Option.SOME(BitsN.B(0x1B,5)) | [#"g",#"p"] => Option.SOME(BitsN.B(0x1C,5)) | [#"s",#"p"] => Option.SOME(BitsN.B(0x1D,5)) | [#"f",#"p"] => Option.SOME(BitsN.B(0x1E,5)) | [#"r",#"a"] => Option.SOME(BitsN.B(0x1F,5)) | #"r" :: r => (case Nat.fromString(String.implode r) of Option.SOME n => (if Nat.<(n,32) then Option.SOME(BitsN.fromNat(n,5)) else NONE) | NONE => NONE) | _ => NONE) | _ => NONE; fun p_reg2 l = case l of [r1,r2] => (case (p_reg r1,p_reg r2) of (Option.SOME a,Option.SOME b) => Option.SOME(a,b) | _ => NONE) | _ => NONE; fun p_address s = let val (l,r) = L3.splitl(fn c => not(c = #"("),stripSpaces s) in case (p_number l,String.explode r) of (Option.SOME n,#"(" :: r) => let val i = BitsN.fromNat(n,16) val (r,e) = L3.splitr(fn c => c = #")",String.implode r) in if (n = (BitsN.toNat i)) andalso (e = ")") then case p_reg r of Option.SOME x => Option.SOME(i,x) | NONE => NONE else NONE end | _ => NONE end; fun p_index_address s = let val (l,r) = L3.splitl(fn c => not(c = #"("),stripSpaces s) in case (p_reg l,String.explode r) of (Option.SOME r1,#"(" :: r) => let val (r,e) = L3.splitr(fn c => c = #")",String.implode r) in if e = ")" then case p_reg r of Option.SOME r2 => Option.SOME(r1,r2) | NONE => NONE else NONE end | _ => NONE end; fun p_arg0 s = case s of "nop" => OK(Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,5))))) | "ssnop" => OK(Shift(SLL(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,5))))) | "syscall" => OK SYSCALL | "break" => OK BREAK | "tlbr" => OK TLBR | "tlbwi" => OK TLBWI | "tlbwr" => OK TLBWR | "tlbp" => OK TLBP | "eret" => OK ERET | "wait" => OK WAIT | _ => FAIL("Unrecognised 0-arg mnemonic: " ^ s); fun p_r1 (x,(s,r)) = case x of "jr" => OK(Branch(JR r)) | "mfhi" => OK(MultDiv(MFHI r)) | "mthi" => OK(MultDiv(MTHI r)) | "mflo" => OK(MultDiv(MFLO r)) | "mtlo" => OK(MultDiv(MTLO r)) | _ => FAIL("Syntax error: " ^ s); fun p_r2 (x,(s,(rs,rt))) = case x of "jalr" => OK(Branch(JALR(rt,rs))) | "madd" => OK(MultDiv(MADD(rs,rt))) | "maddu" => OK(MultDiv(MADDU(rs,rt))) | "msub" => OK(MultDiv(MSUB(rs,rt))) | "msubu" => OK(MultDiv(MSUBU(rs,rt))) | "mult" => OK(MultDiv(MULT(rs,rt))) | "multu" => OK(MultDiv(MULTU(rs,rt))) | "div" => OK(MultDiv(DIV(rs,rt))) | "divu" => OK(MultDiv(DIVU(rs,rt))) | "dmult" => OK(MultDiv(DMULT(rs,rt))) | "dmultu" => OK(MultDiv(DMULTU(rs,rt))) | "ddiv" => OK(MultDiv(DDIV(rs,rt))) | "ddivu" => OK(MultDiv(DDIVU(rs,rt))) | "tge" => OK(Trap(TGE(rs,rt))) | "tgeu" => OK(Trap(TGEU(rs,rt))) | "tlt" => OK(Trap(TLT(rs,rt))) | "tltu" => OK(Trap(TLTU(rs,rt))) | "teq" => OK(Trap(TEQ(rs,rt))) | "tne" => OK(Trap(TNE(rs,rt))) | "rdhwr" => OK(RDHWR(rs,rt)) | _ => FAIL("Syntax error: " ^ s); fun p_rcfpr (x,(s,(rt,fs))) = case x of "cfc1" => OK(COP1(CFC1(rt,fs))) | "ctc1" => OK(COP1(CTC1(rt,fs))) | _ => FAIL("Syntax error: " ^ s); fun p_rfpr2 (x,(s,(rt,fs))) = case x of "mfc1" => OK(COP1(MFC1(rt,fs))) | "mtc1" => OK(COP1(MTC1(rt,fs))) | "dmfc1" => OK(COP1(DMFC1(rt,fs))) | "dmtc1" => OK(COP1(DMTC1(rt,fs))) | _ => FAIL("Syntax error: " ^ s); fun p_fpr2 (x,(s,(fd,fs))) = case x of "abs.d" => OK(COP1(ABS_D(fd,fs))) | "abs.s" => OK(COP1(ABS_S(fd,fs))) | "c.f.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x0,3),BitsN.B(0x0,3)))))) | "c.un.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x1,3),BitsN.B(0x0,3)))))) | "c.eq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x2,3),BitsN.B(0x0,3)))))) | "c.ueq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x3,3),BitsN.B(0x0,3)))))) | "c.olt.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x4,3),BitsN.B(0x0,3)))))) | "c.ult.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x5,3),BitsN.B(0x0,3)))))) | "c.ole.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x6,3),BitsN.B(0x0,3)))))) | "c.ule.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x7,3),BitsN.B(0x0,3)))))) | "c.f.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x0,3),BitsN.B(0x0,3)))))) | "c.un.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x1,3),BitsN.B(0x0,3)))))) | "c.eq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x2,3),BitsN.B(0x0,3)))))) | "c.ueq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x3,3),BitsN.B(0x0,3)))))) | "c.olt.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x4,3),BitsN.B(0x0,3)))))) | "c.ult.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x5,3),BitsN.B(0x0,3)))))) | "c.ole.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x6,3),BitsN.B(0x0,3)))))) | "c.ule.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x7,3),BitsN.B(0x0,3)))))) | "ceil.l.d" => OK(COP1(CEIL_L_D(fd,fs))) | "ceil.l.s" => OK(COP1(CEIL_L_S(fd,fs))) | "ceil.w.d" => OK(COP1(CEIL_W_D(fd,fs))) | "ceil.w.s" => OK(COP1(CEIL_W_S(fd,fs))) | "cvt.d.l" => OK(COP1(CVT_D_L(fd,fs))) | "cvt.d.s" => OK(COP1(CVT_D_S(fd,fs))) | "cvt.d.w" => OK(COP1(CVT_D_W(fd,fs))) | "cvt.l.d" => OK(COP1(CVT_L_D(fd,fs))) | "cvt.l.s" => OK(COP1(CVT_L_S(fd,fs))) | "cvt.s.l" => OK(COP1(CVT_S_L(fd,fs))) | "cvt.s.d" => OK(COP1(CVT_S_D(fd,fs))) | "cvt.s.w" => OK(COP1(CVT_S_W(fd,fs))) | "cvt.w.d" => OK(COP1(CVT_W_D(fd,fs))) | "cvt.w.s" => OK(COP1(CVT_W_S(fd,fs))) | "floor.l.d" => OK(COP1(FLOOR_L_D(fd,fs))) | "floor.l.s" => OK(COP1(FLOOR_L_S(fd,fs))) | "floor.w.d" => OK(COP1(FLOOR_W_D(fd,fs))) | "floor.w.s" => OK(COP1(FLOOR_W_S(fd,fs))) | "mov.d" => OK(COP1(MOV_D(fd,fs))) | "mov.s" => OK(COP1(MOV_S(fd,fs))) | "neg.d" => OK(COP1(NEG_D(fd,fs))) | "neg.s" => OK(COP1(NEG_S(fd,fs))) | "round.l.d" => OK(COP1(ROUND_L_D(fd,fs))) | "round.l.s" => OK(COP1(ROUND_L_S(fd,fs))) | "round.w.d" => OK(COP1(ROUND_W_D(fd,fs))) | "round.w.s" => OK(COP1(ROUND_W_S(fd,fs))) | "sqrt.d" => OK(COP1(SQRT_D(fd,fs))) | "sqrt.s" => OK(COP1(SQRT_S(fd,fs))) | "trunc.l.d" => OK(COP1(TRUNC_L_D(fd,fs))) | "trunc.l.s" => OK(COP1(TRUNC_L_S(fd,fs))) | "trunc.w.d" => OK(COP1(TRUNC_W_D(fd,fs))) | "trunc.w.s" => OK(COP1(TRUNC_W_S(fd,fs))) | _ => FAIL("Syntax error: " ^ s); fun p_ccfpr2 (x,(s,(cc,(fd,fs)))) = case x of "c.f.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x0,3),cc))))) | "c.un.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x1,3),cc))))) | "c.eq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x2,3),cc))))) | "c.ueq.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x3,3),cc))))) | "c.olt.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x4,3),cc))))) | "c.ult.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x5,3),cc))))) | "c.ole.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x6,3),cc))))) | "c.ule.d" => OK(COP1(C_cond_D(fd,(fs,(BitsN.B(0x7,3),cc))))) | "c.f.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x0,3),cc))))) | "c.un.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x1,3),cc))))) | "c.eq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x2,3),cc))))) | "c.ueq.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x3,3),cc))))) | "c.olt.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x4,3),cc))))) | "c.ult.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x5,3),cc))))) | "c.ole.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x6,3),cc))))) | "c.ule.s" => OK(COP1(C_cond_S(fd,(fs,(BitsN.B(0x7,3),cc))))) | _ => FAIL("Syntax error: " ^ s); fun p_r2cc (x,(s,(rd,(rs,cc)))) = case x of "movf" => OK(COP1(MOVF(rd,(rs,cc)))) | "movt" => OK(COP1(MOVT(rd,(rs,cc)))) | _ => FAIL("Syntax error: " ^ s); fun p_fpr2r (x,(s,(fd,(fs,rt)))) = case x of "movn.d" => OK(COP1(MOVN_D(fd,(fs,rt)))) | "movn.s" => OK(COP1(MOVN_S(fd,(fs,rt)))) | "movz.d" => OK(COP1(MOVZ_D(fd,(fs,rt)))) | "movz.s" => OK(COP1(MOVZ_S(fd,(fs,rt)))) | _ => FAIL("Syntax error: " ^ s); fun p_fpr2cc (x,(s,(fd,(fs,cc)))) = case x of "movf.d" => OK(COP1(MOVF_D(fd,(fs,cc)))) | "movf.s" => OK(COP1(MOVF_S(fd,(fs,cc)))) | "movt.d" => OK(COP1(MOVT_D(fd,(fs,cc)))) | "movt.s" => OK(COP1(MOVT_S(fd,(fs,cc)))) | _ => FAIL("Syntax error: " ^ s); fun p_r3 (x,(s,(rd,(rs,rt)))) = case x of "sllv" => OK(Shift(SLLV(rt,(rs,rd)))) | "srlv" => OK(Shift(SRLV(rt,(rs,rd)))) | "srav" => OK(Shift(SRAV(rt,(rs,rd)))) | "dsllv" => OK(Shift(DSLLV(rt,(rs,rd)))) | "dsrlv" => OK(Shift(DSRLV(rt,(rs,rd)))) | "dsrav" => OK(Shift(DSRAV(rt,(rs,rd)))) | "mul" => OK(MultDiv(MUL(rs,(rt,rd)))) | "movn" => OK(ArithR(MOVN(rs,(rt,rd)))) | "movz" => OK(ArithR(MOVZ(rs,(rt,rd)))) | "add" => OK(ArithR(ADD(rs,(rt,rd)))) | "addu" => OK(ArithR(ADDU(rs,(rt,rd)))) | "sub" => OK(ArithR(SUB(rs,(rt,rd)))) | "subu" => OK(ArithR(SUBU(rs,(rt,rd)))) | "and" => OK(ArithR(AND(rs,(rt,rd)))) | "or" => OK(ArithR(OR(rs,(rt,rd)))) | "xor" => OK(ArithR(XOR(rs,(rt,rd)))) | "nor" => OK(ArithR(NOR(rs,(rt,rd)))) | "slt" => OK(ArithR(SLT(rs,(rt,rd)))) | "sltu" => OK(ArithR(SLTU(rs,(rt,rd)))) | "dadd" => OK(ArithR(DADD(rs,(rt,rd)))) | "daddu" => OK(ArithR(DADDU(rs,(rt,rd)))) | "dsub" => OK(ArithR(DSUB(rs,(rt,rd)))) | "dsubu" => OK(ArithR(DSUBU(rs,(rt,rd)))) | _ => FAIL("Syntax error: " ^ s); fun p_fpr3 (x,(s,(fd,(fs,ft)))) = case x of "add.d" => OK(COP1(ADD_D(fd,(fs,ft)))) | "add.s" => OK(COP1(ADD_S(fd,(fs,ft)))) | "div.d" => OK(COP1(DIV_D(fd,(fs,ft)))) | "div.s" => OK(COP1(DIV_S(fd,(fs,ft)))) | "mul.d" => OK(COP1(MUL_D(fd,(fs,ft)))) | "mul.s" => OK(COP1(MUL_S(fd,(fs,ft)))) | "sub.d" => OK(COP1(SUB_D(fd,(fs,ft)))) | "sub.s" => OK(COP1(SUB_S(fd,(fs,ft)))) | _ => FAIL("Syntax error: " ^ s); fun p_fpr4 (x,(s,(fd,(fr,(fs,ft))))) = case x of "madd.d" => OK(COP1(MADD_D(fd,(fr,(fs,ft))))) | "madd.s" => OK(COP1(MADD_S(fd,(fr,(fs,ft))))) | "msub.d" => OK(COP1(MSUB_D(fd,(fr,(fs,ft))))) | "msub.s" => OK(COP1(MSUB_S(fd,(fr,(fs,ft))))) | _ => FAIL("Syntax error: " ^ s); fun imm_ok N (t,(n,s)) = let val (n,valid) = case t of NONE => (n,true) | Option.SOME false => (Nat.div(n,4),(Nat.mod(n,4)) = 0) | Option.SOME true => (Nat.-(Nat.div(n,4),1),((Nat.mod(n,4)) = 0) andalso (Nat.<=(4,n))) in if valid then let val imm = BitsN.fromNat(n,N) in if n = (BitsN.toNat imm) then (imm,"") else (BitsN.BV(0x0,N),"Immediate too large: " ^ s) end else (BitsN.BV(0x0,N),"Immediate not aligned or too small: " ^ s) end; fun p_1i (x,(s,n)) = case x of "j" => let val (i,e) = imm_ok 26 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(J i)) else FAIL e end | "jal" => let val (i,e) = imm_ok 26 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(JAL i)) else FAIL e end | "beq" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BEQ(BitsN.B(0x0,5),(BitsN.B(0x0,5),i)))) else FAIL e end | "bc1f" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1F(i,BitsN.B(0x0,3)))) else FAIL e end | "bc1fl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1FL(i,BitsN.B(0x0,3)))) else FAIL e end | "bc1t" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1T(i,BitsN.B(0x0,3)))) else FAIL e end | "bc1tl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1TL(i,BitsN.B(0x0,3)))) else FAIL e end | "word" => let val i = BitsN.fromNat(n,32) in if n = (BitsN.toNat i) then WORD32 i else FAIL("Immediate too large: " ^ s) end | _ => FAIL("Syntax error: " ^ s); fun p_cc1i (x,(s,(cc,n))) = case x of "bc1f" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1F(i,cc))) else FAIL e end | "bc1fl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1FL(i,cc))) else FAIL e end | "bc1t" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1T(i,cc))) else FAIL e end | "bc1tl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(COP1(BC1TL(i,cc))) else FAIL e end | _ => FAIL("Syntax error: " ^ s); fun p_r1i (x,(s,(r,n))) = case x of "bltz" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BLTZ(r,i))) else FAIL e end | "bgez" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BGEZ(r,i))) else FAIL e end | "blez" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BLEZ(r,i))) else FAIL e end | "bgtz" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BGTZ(r,i))) else FAIL e end | "bltzl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BLTZL(r,i))) else FAIL e end | "bgezl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BGEZL(r,i))) else FAIL e end | "blezl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BLEZL(r,i))) else FAIL e end | "bgtzl" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BGTZL(r,i))) else FAIL e end | "tgei" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TGEI(r,i))) else FAIL e end | "tgeiu" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TGEIU(r,i))) else FAIL e end | "tlti" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TLTI(r,i))) else FAIL e end | "tltiu" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TLTIU(r,i))) else FAIL e end | "teqi" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TEQI(r,i))) else FAIL e end | "tnei" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(Trap(TNEI(r,i))) else FAIL e end | "bltzal" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BLTZAL(r,i))) else FAIL e end | "bgezal" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BGEZAL(r,i))) else FAIL e end | "bltzall" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BLTZALL(r,i))) else FAIL e end | "bgezall" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BGEZALL(r,i))) else FAIL e end | "lui" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(LUI(r,i))) else FAIL e end | _ => FAIL("Syntax error: " ^ s); fun p_r2i (x,(s,(r1,(r2,n)))) = case x of "sll" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(SLL(r2,(r1,i)))) else FAIL e end | "srl" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(SRL(r2,(r1,i)))) else FAIL e end | "sra" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(SRA(r2,(r1,i)))) else FAIL e end | "dsll" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSLL(r2,(r1,i)))) else FAIL e end | "dsrl" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSRL(r2,(r1,i)))) else FAIL e end | "dsra" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSRA(r2,(r1,i)))) else FAIL e end | "dsll32" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSLL32(r2,(r1,i)))) else FAIL e end | "dsrl32" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSRL32(r2,(r1,i)))) else FAIL e end | "dsra32" => let val (i,e) = imm_ok 5 (NONE,(n,s)) in if e = "" then OK(Shift(DSRA32(r2,(r1,i)))) else FAIL e end | "beq" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BEQ(r1,(r2,i)))) else FAIL e end | "bne" => let val (i,e) = imm_ok 16 (Option.SOME false,(n,s)) in if e = "" then OK(Branch(BNE(r1,(r2,i)))) else FAIL e end | "beql" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BEQL(r1,(r2,i)))) else FAIL e end | "bnel" => let val (i,e) = imm_ok 16 (Option.SOME true,(n,s)) in if e = "" then OK(Branch(BNEL(r1,(r2,i)))) else FAIL e end | "addi" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(ADDI(r2,(r1,i)))) else FAIL e end | "addiu" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(ADDIU(r2,(r1,i)))) else FAIL e end | "daddi" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(DADDI(r2,(r1,i)))) else FAIL e end | "daddiu" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(DADDIU(r2,(r1,i)))) else FAIL e end | "slti" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(SLTI(r2,(r1,i)))) else FAIL e end | "sltiu" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(SLTIU(r2,(r1,i)))) else FAIL e end | "andi" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(ANDI(r2,(r1,i)))) else FAIL e end | "ori" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(ORI(r2,(r1,i)))) else FAIL e end | "xori" => let val (i,e) = imm_ok 16 (NONE,(n,s)) in if e = "" then OK(ArithI(XORI(r2,(r1,i)))) else FAIL e end | _ => FAIL("Syntax error: " ^ s); fun p_opmem (x,(s,(rt,(rs,imm)))) = case x of "ldl" => OK(Load(LDL(rs,(rt,imm)))) | "ldr" => OK(Load(LDR(rs,(rt,imm)))) | "lb" => OK(Load(LB(rs,(rt,imm)))) | "lh" => OK(Load(LH(rs,(rt,imm)))) | "lwl" => OK(Load(LWL(rs,(rt,imm)))) | "lw" => OK(Load(LW(rs,(rt,imm)))) | "lbu" => OK(Load(LBU(rs,(rt,imm)))) | "lhu" => OK(Load(LHU(rs,(rt,imm)))) | "lwr" => OK(Load(LWR(rs,(rt,imm)))) | "lwu" => OK(Load(LWU(rs,(rt,imm)))) | "sb" => OK(Store(SB(rs,(rt,imm)))) | "sh" => OK(Store(SH(rs,(rt,imm)))) | "swl" => OK(Store(SWL(rs,(rt,imm)))) | "sw" => OK(Store(SW(rs,(rt,imm)))) | "sdl" => OK(Store(SDL(rs,(rt,imm)))) | "sdr" => OK(Store(SDR(rs,(rt,imm)))) | "swr" => OK(Store(SWR(rs,(rt,imm)))) | "ll" => OK(Load(LL(rs,(rt,imm)))) | "lld" => OK(Load(LLD(rs,(rt,imm)))) | "ld" => OK(Load(LD(rs,(rt,imm)))) | "sc" => OK(Store(SC(rs,(rt,imm)))) | "scd" => OK(Store(SCD(rs,(rt,imm)))) | "sd" => OK(Store(SD(rs,(rt,imm)))) | _ => FAIL("Syntax error: " ^ s); fun p_opfpmem (x,(s,(ft,(rs,imm)))) = case x of "ldc1" => OK(COP1(LDC1(ft,(imm,rs)))) | "lwc1" => OK(COP1(LWC1(ft,(imm,rs)))) | "sdc1" => OK(COP1(SDC1(ft,(imm,rs)))) | "swc1" => OK(COP1(SWC1(ft,(imm,rs)))) | _ => FAIL("Syntax error: " ^ s); fun p_opfpmem2 (x,(s,(ft,(rs,index)))) = case x of "ldxc1" => OK(COP1(LDXC1(ft,(index,rs)))) | "lwxc1" => OK(COP1(LWXC1(ft,(index,rs)))) | "sdxc1" => OK(COP1(SDXC1(ft,(index,rs)))) | "swxc1" => OK(COP1(SWXC1(ft,(index,rs)))) | _ => FAIL("Syntax error: " ^ s); fun instructionFromString s = case p_tokens s of [x] => p_arg0 x | [x,a] => (case p_reg a of Option.SOME r => p_r1(x,(s,r)) | NONE => (case p_number a of Option.SOME n => p_1i(x,(s,n)) | _ => FAIL("Syntax error: " ^ s))) | [x,a,b] => (case (p_reg a,p_reg b) of (Option.SOME r1,Option.SOME r2) => p_r2(x,(s,(r1,r2))) | (Option.SOME r1,NONE) => (case p_number b of Option.SOME n => p_r1i(x,(s,(r1,n))) | _ => (case p_address b of Option.SOME(i,r2) => p_opmem(x,(s,(r1,(r2,i)))) | NONE => (case p_fp_reg b of Option.SOME r2 => p_rfpr2(x,(s,(r1,r2))) | NONE => (case p_cfp_reg b of Option.SOME r2 => p_rcfpr(x,(s,(r1,r2))) | NONE => FAIL("Syntax error: " ^ s))))) | _ => (case (p_fp_reg a,p_fp_reg b) of (Option.SOME r1,Option.SOME r2) => p_fpr2(x,(s,(r1,r2))) | (Option.SOME r1,NONE) => (case p_address b of Option.SOME(i,r2) => p_opfpmem(x,(s,(r1,(r2,i)))) | NONE => (case p_index_address b of Option.SOME(r2,r3) => p_opfpmem2(x,(s,(r1,(r2,r3)))) | NONE => FAIL("Syntax error: " ^ s))) | _ => (case (p_fp_cc a,p_number b) of (Option.SOME cc,Option.SOME n) => p_cc1i(x,(s,(cc,n))) | _ => FAIL("Syntax error: " ^ s)))) | [x,a,b,c] => (case (p_reg2[a,b],p_reg c) of (Option.SOME(r1,r2),Option.SOME r3) => p_r3(x,(s,(r1,(r2,r3)))) | (Option.SOME(r1,r2),NONE) => (case p_number c of Option.SOME n => p_r2i(x,(s,(r1,(r2,n)))) | _ => (case p_fp_cc c of Option.SOME cc => p_r2cc(x,(s,(r1,(r2,cc)))) | NONE => FAIL("Syntax error: " ^ s))) | (NONE,Option.SOME r3) => (case (p_fp_reg a,p_fp_reg b) of (Option.SOME r1,Option.SOME r2) => p_fpr2r(x,(s,(r1,(r2,r3)))) | _ => FAIL("Syntax error: " ^ s)) | _ => (case (p_fp_reg a,(p_fp_reg b,p_fp_reg c)) of (Option.SOME r1,(Option.SOME r2,Option.SOME r3)) => p_fpr3(x,(s,(r1,(r2,r3)))) | (Option.SOME r1,(Option.SOME r2,NONE)) => (case p_fp_cc c of Option.SOME cc => p_fpr2cc(x,(s,(r1,(r2,cc)))) | NONE => FAIL("Syntax error: " ^ s)) | (NONE,(Option.SOME r1,Option.SOME r2)) => (case p_fp_cc a of Option.SOME cc => p_ccfpr2(x,(s,(cc,(r1,r2)))) | NONE => FAIL("Syntax error: " ^ s)) | _ => FAIL("Syntax error: " ^ s))) | [x,a,b,c,d] => (case (p_fp_reg a,(p_fp_reg b,(p_fp_reg c,p_fp_reg d))) of (Option.SOME r1,(Option.SOME r2,(Option.SOME r3,Option.SOME r4))) => p_fpr4(x,(s,(r1,(r2,(r3,r4))))) | _ => FAIL("Syntax error: " ^ s)) | _ => FAIL("Syntax error: " ^ s); fun encodeInstruction s = case instructionFromString s of OK i => L3.padLeftString(#"0",(8,BitsN.toHexString(Encode i))) | WORD32 w => L3.padLeftString(#"0",(8,BitsN.toHexString w)) | FAIL s => s; end