/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma ident "%Z%%M% %I% %E% SMI" #pragma dictionary "SUN4V" /* * Define FITrates for different types of errors. For the ultrSPARC-T2plus * interconnect, they are all defined to provide relative likelihood as * actual FITrates are unavailable. We define them here in case more * accurate values become available in future. */ #define CPU_CHIP_FIT 400 #define FPGA_FIT 400 #define FIRMWARE_HYPERVISOR_FIT 400 #define FIRMWARE_VBSC_FIT 400 #define INTERCONNECT_OPU_FIT 400 #define INTERCONNECT_LFU_F_FIT 400 #define INTERCONNECT_LFU_U_FIT 400 #define INTERCONNECT_LFU_C_FIT 400 #define INTERCONNECT_GPD_FIT 400 #define INTERCONNECT_ASU_FIT 400 /* * Define propogation delays for the ereports. * * For immediate processing, we specify a very short delay, which seems to * work better than 0. For ereports that are to be ignored, we delay longer, * 1 second. */ #define IGNORE_DELAY 1s #define IMMEDIATE_DELAY 5ms #define SERD_DELAY 1ms #define RETRAIN_DELAY 5s /* * Test for primary or secondary ereports */ #define IS_PRIMARY (payloadprop("primary")) #define IS_SECONDARY (! payloadprop("primary")) /* * Tests to determine what CHIP is associated with an ereport */ #define MATCH_CPUID(n) (payloadprop("cpu-nodeid") == n) /* * SERD values used by the LFU subsystem */ #define LFU_CRC_SERD_N 22 #define LFU_CRC_SERD_T 30 min /* * ASRU and FRU definitions used by this diagnosis engine. */ asru motherboard; asru interconnect; asru chip; fru motherboard; fru cpuboard; /* * Define the errors that propogate to a CHIP fault. */ event error.cpu.ultraSPARC-T2plus.opu.protocol@chip; event error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip; event error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip; event error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip; event error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip; event error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip; event error.cpu.ultraSPARC-T2plus.asu.protocol@chip; event fault.cpu.ultraSPARC-T2plus.chip@chip FITrate=CPU_CHIP_FIT, ASRU=chip, FRU=cpuboard; prop fault.cpu.ultraSPARC-T2plus.chip@chip -> error.cpu.ultraSPARC-T2plus.opu.protocol@chip, error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip, error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip, error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip, error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip, error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip, error.cpu.ultraSPARC-T2plus.asu.protocol@chip; /* * OPU Subsystem */ event ereport.asic.zambezi.opu.ods-ctrl-parity@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ods-data-coherent-read@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ods-data-coherent-writeback@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ods-data-destid@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ods-data-parity@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.oqs-request-bad-nc-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.oqs-request-bad-read-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.oqs-request-bad-writeback-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.oqs-request-duplicate@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-bad-nc-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-bad-read-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-bad-writeback-type@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-duplicate@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-inconsistent@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-response-unexpected@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-timeout-read@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.opu.ors-timeout-writeback@interconnect {within (IMMEDIATE_DELAY)}; /* * Declare the intermediate errors that will be generated by the ereports * in this subsystem. These errors will, in turn, propogate to the * appropriate fault. */ event error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect; /* * This fault is diagnosed for uncorrectible OPU errors */ event fault.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect FITrate=INTERCONNECT_OPU_FIT, ASRU=interconnect, FRU=motherboard; prop error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect -> ereport.asic.zambezi.opu.ods-ctrl-parity@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.opu-u@interconnect; /* * This fault is diagnosed for correctible OPU errors. */ event fault.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect FITrate=INTERCONNECT_OPU_FIT, ASRU=interconnect, FRU=motherboard; prop error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect -> ereport.asic.zambezi.opu.ods-data-parity@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.opu-c@interconnect; /* * All of the following ereports are associated with a CHIP. Propogate * them to the appropriate error for diagnosis to a CHIP fault, above. */ prop error.cpu.ultraSPARC-T2plus.opu.protocol@chip[chip_num] (0) -> ereport.asic.zambezi.opu.ods-data-destid@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ods-data-coherent-read@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ods-data-coherent-writeback@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.oqs-request-bad-read-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.oqs-request-bad-writeback-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.oqs-request-bad-nc-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.oqs-request-duplicate@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-unexpected@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-duplicate@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-inconsistent@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-bad-read-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-bad-writeback-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-response-bad-nc-type@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-timeout-read@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.opu.ors-timeout-writeback@interconnect {MATCH_CPUID(chip_num)}; /* * LFU Subsystem */ event ereport.asic.zambezi.lfu.crc-error@interconnect {within (SERD_DELAY)}; event ereport.asic.zambezi.lfu.data-invalid-or-unmapped@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.electric-idle@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.irq-overflow@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.irq-parity@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.irq-underflow@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.lane-failure-slf@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.link-down-retrain@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.link-down-second-replay@interconnect {within (SERD_DELAY)}; event ereport.asic.zambezi.lfu.link-training-l05@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.link-training-config@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.link-training-state@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.link-training-testing@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.replay-lcf-rcvd-error@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.replay-lcf-sent-error@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.replay-parity@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.reply-invalid-or-unmapped@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.reply-tid-release-set@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.retrain-error-disabled@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.retrain-error-resume-timeout@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.retrain-error-second-crc@interconnect {within (RETRAIN_DELAY)}; event ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect {within (IMMEDIATE_DELAY)}; event ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect {within (IMMEDIATE_DELAY)}; /* * Declare the intermediate errors that will be generated by the ereports * in this subsystem. These errors will, in turn, propogate to the * appropriate fault. */ event error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; /* * Declare the upsets that may be diagnosed for the LFU subsystem */ event upset.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; /* * Declare the faults that may be generated for the LFU subsystem. */ event fault.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect FITrate=INTERCONNECT_LFU_C_FIT, ASRU=interconnect, FRU=motherboard; event fault.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect FITrate=INTERCONNECT_LFU_F_FIT, ASRU=interconnect, FRU=motherboard; event fault.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect FITrate=INTERCONNECT_LFU_U_FIT, ASRU=interconnect, FRU=motherboard; /* * Define how the intermediate errors propogate to faults for the LFU * subsystem. */ prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect; /* * We want to count CRC errors on each connection between an interconnect * and a CHIP. Each interconnect is connected to each CHIP, so we need 16 * SERD engines (4 interconnects, and 4 CHIPs). * * The topology does not include interconnect/chip, so we cannot do this * automatically. Instead, we explicitly declare 4 sets of serd engine * propogations, one for each CHIP, and let eversholt expand to all available * interconnects. */ event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect; event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect; event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect; event ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; prop error.asic.ultraSPARC-T2plus.interconnect.lfu-c@interconnect -> ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; /* * CHIP0 SERD rules * * These rules create a SERD engine for the connection between each * interconnect and CHIP 0. */ engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect, N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip0@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip0@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip0@interconnect -> ereport.asic.zambezi.lfu.crc-error@interconnect {MATCH_CPUID(0)}; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip0@interconnect -> ereport.asic.zambezi.lfu.link-down-second-replay@interconnect {MATCH_CPUID(0)}; /* * CHIP1 SERD rules * * These rules create a SERD engine for the connection between each * interconnect and CHIP 1. */ engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect, N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip1@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip1@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip1@interconnect -> ereport.asic.zambezi.lfu.crc-error@interconnect {MATCH_CPUID(1)}; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip1@interconnect -> ereport.asic.zambezi.lfu.link-down-second-replay@interconnect {MATCH_CPUID(1)}; /* * CHIP2 SERD rules * * These rules create a SERD engine for the connection between each * interconnect and CHIP 2. */ engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect, N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip2@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip2@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip2@interconnect -> ereport.asic.zambezi.lfu.crc-error@interconnect {MATCH_CPUID(2)}; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip2@interconnect -> ereport.asic.zambezi.lfu.link-down-second-replay@interconnect {MATCH_CPUID(2)}; /* * CHIP3 SERD rules * * These rules create a SERD engine for the connection between each * interconnect and CHIP 3. */ engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect, N=LFU_CRC_SERD_N, T=LFU_CRC_SERD_T, method=persistent, trip=ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip3@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect; event upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip3@interconnect, engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip3@interconnect; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.crc.chip3@interconnect -> ereport.asic.zambezi.lfu.crc-error@interconnect {MATCH_CPUID(3)}; prop upset.asic.ultraSPARC-T2plus.interconnect.lfu.replay.chip3@interconnect -> ereport.asic.zambezi.lfu.link-down-second-replay@interconnect {MATCH_CPUID(3)}; /* * LFU propogations that generate * error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect */ prop error.asic.ultraSPARC-T2plus.interconnect.lfu-f@interconnect -> ereport.asic.zambezi.lfu.lane-failure-slf@interconnect; /* * LFU propogations that generate * error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip */ prop error.cpu.ultraSPARC-T2plus.lfu-f.chip@chip[chip_num] (0) -> ereport.asic.zambezi.lfu.lane-failure-slf@interconnect {MATCH_CPUID(chip_num)}; /* * LFU propogations that generate * error.cpu.ultrSPARC-T2plus.lfu-u.chip */ prop error.cpu.ultraSPARC-T2plus.lfu-u.chip@chip[chip_num] (0) -> ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.link-training-state@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.link-training-testing@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.link-training-config@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.link-training-l05@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect {MATCH_CPUID(chip_num)}; /* * LFU propogations that generate * error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect */ prop error.asic.ultraSPARC-T2plus.interconnect.lfu-u@interconnect -> ereport.asic.zambezi.lfu.lane-failure-mlf@interconnect, ereport.asic.zambezi.lfu.link-training-state@interconnect, ereport.asic.zambezi.lfu.link-training-testing@interconnect, ereport.asic.zambezi.lfu.link-training-config@interconnect, ereport.asic.zambezi.lfu.link-training-l05@interconnect, ereport.asic.zambezi.lfu.link-down-retrain-failed@interconnect, ereport.asic.zambezi.lfu.retrain-failed-second-crc@interconnect, ereport.asic.zambezi.lfu.retrain-failed-resume-timeout@interconnect, ereport.asic.zambezi.lfu.retrain-failed-disabled@interconnect, ereport.asic.zambezi.lfu.replay-parity@interconnect, ereport.asic.zambezi.lfu.irq-parity@interconnect, ereport.asic.zambezi.lfu.irq-underflow@interconnect; /* * LFU propogations that generate * error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect */ prop error.asic.ultraSPARC-T2plus.interconnect.lfu.ignore@interconnect -> ereport.asic.zambezi.lfu.link-down-retrain@interconnect, ereport.asic.zambezi.lfu.electric-idle@interconnect, ereport.asic.zambezi.lfu.retrain-error-resume-timeout@interconnect, ereport.asic.zambezi.lfu.retrain-error-second-crc@interconnect, ereport.asic.zambezi.lfu.retrain-error-disabled@interconnect, ereport.asic.zambezi.lfu.replay-lcf-rcvd-error@interconnect, ereport.asic.zambezi.lfu.replay-lcf-sent-error@interconnect; /* * LFU propogations that generate * error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip */ prop error.cpu.ultraSPARC-T2plus.lfu-c.chip@chip[chip_num] (0) -> ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip0@interconnect {chip_num == 0}, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip1@interconnect {chip_num == 1}, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip2@interconnect {chip_num == 2}, ereport.asic.ultraSPARC-T2plus.interconnect.lfu.crc-trip3@interconnect {chip_num == 3}, ereport.asic.zambezi.lfu.data-invalid-or-unmapped@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.reply-invalid-or-unmapped@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.reply-tid-release-set@interconnect {MATCH_CPUID(chip_num)}, ereport.asic.zambezi.lfu.irq-overflow@interconnect {MATCH_CPUID(chip_num)}; /* * GPD Subsystem */ event ereport.asic.zambezi.gpd.jtag-access-violation@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.jtag-mapped-timeout@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-access-violation@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-access-violation@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-mapped-timeout@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.gpd.lpc-rw-interleave-error@interconnect {within(IMMEDIATE_DELAY)}; /* * Declare the intermediate errors that will be generated by the ereports * in this subsystem. These errors will, in turn, propogate to the * appropriate fault. */ event error.asic.fpga@motherboard; event error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect; /* * Declare the upsets that may be diagnosed for this subsystem */ event upset.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; /* * Declare the faults that may be generated for this subsystem. */ event fault.asic.fpga@motherboard FITrate=FPGA_FIT, ASRU=motherboard, FRU=motherboard; event fault.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect FITrate=INTERCONNECT_GPD_FIT, ASRU=interconnect, FRU=motherboard; event fault.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect FITrate=INTERCONNECT_GPD_FIT, ASRU=interconnect, FRU=motherboard; /* * Define how the intermediate errors propogate to faults for this subsystem. */ prop fault.asic.fpga@motherboard -> error.asic.fpga@motherboard; prop upset.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect, error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect; /* * GPD suspect list * fault.asic.ultraSPARC-T2plus.interconnect.gpd-u * fault.cpu.ultraSPARC-T2plus.chip * * Events in this list are diagnosed only if they are primary errors. * The necessary information is unavailable for secondary errors, so * they are logged but not diagnosed. */ prop error.cpu.ultraSPARC-T2plus.gpd-u.chip@chip[chip_num] (0) -> ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}; prop error.cpu.ultraSPARC-T2plus.gpd-c.chip@chip[chip_num] (0) -> ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-access-violation@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}; prop error.asic.ultraSPARC-T2plus.interconnect.gpd-u@interconnect -> ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect {IS_PRIMARY}; prop error.asic.ultraSPARC-T2plus.interconnect.gpd.ignore@interconnect -> ereport.asic.zambezi.gpd.link-write-request-timeout@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-data-timeout@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-request-tid-invalid@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-unexpected-data-rcvd@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-unexpected-request-rcvd@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-access-violation@interconnect {IS_SECONDARY}, ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect {IS_SECONDARY}; prop error.asic.ultraSPARC-T2plus.interconnect.gpd-c@interconnect -> ereport.asic.zambezi.gpd.link-write-tid-invalid@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-data-chunk-error@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-data-c2c-set@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-data-error-bit-set@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-invalid-write-request@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-write-data-bytemask-error@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-mapped-timeout@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-access-violation@interconnect {IS_PRIMARY}, ereport.asic.zambezi.gpd.link-invalid-read-request@interconnect {IS_PRIMARY}; prop error.asic.ultraSPARC-T2plus.interconnect.gpd@interconnect -> ereport.asic.zambezi.gpd.jtag-access-violation@interconnect, ereport.asic.zambezi.gpd.jtag-mapped-timeout@interconnect, ereport.asic.zambezi.gpd.lpc-mapped-timeout@interconnect, ereport.asic.zambezi.gpd.lpc-access-violation@interconnect, ereport.asic.zambezi.gpd.lpc-rw-interleave-error@interconnect, ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect, ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect, ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect; prop error.asic.fpga@motherboard (0) -> ereport.asic.zambezi.gpd.lpc-invalid-abort@interconnect, ereport.asic.zambezi.gpd.lpc-invalid-start@interconnect, ereport.asic.zambezi.gpd.lpc-invalid-cycle-type@interconnect; /* * ASU Subsystem */ event ereport.asic.zambezi.asu.cam-parity-error@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.invalid-nc-destid@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.invalid-wb-destid@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.malformed-wb@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.pending-ram-parity-error@interconnect {within(IMMEDIATE_DELAY)}; event ereport.asic.zambezi.asu.pending-tid-ram-parity-error@interconnect {within(IMMEDIATE_DELAY)}; /* * Declare the intermediate errors that will be generated by the ereports * in this subsystem. These errors will, in turn, propogate to the * appropriate fault. */ event error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; event error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect; /* * Declare the upsets that may be diagnosed for this subsystem */ event upset.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; /* * Declare the faults that may be generated for this subsystem. */ event fault.asic.ultraSPARC-T2plus.interconnect.asu@interconnect FITrate=INTERCONNECT_ASU_FIT, ASRU=interconnect, FRU=motherboard; /* * Define how the intermediate errors propogate to faults for this subsystem. */ prop upset.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect; prop fault.asic.ultraSPARC-T2plus.interconnect.asu@interconnect -> error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect; prop error.cpu.ultraSPARC-T2plus.asu.protocol@chip[chip_num] (0) -> ereport.asic.zambezi.asu.invalid-nc-destid@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.asu.invalid-wb-destid@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.asu.malformed-wb@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}, ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect {IS_PRIMARY && MATCH_CPUID(chip_num)}; prop error.asic.ultraSPARC-T2plus.interconnect.asu.ignore@interconnect -> ereport.asic.zambezi.asu.invalid-nc-destid@interconnect {IS_SECONDARY}, ereport.asic.zambezi.asu.invalid-tid-non-cacheable@interconnect {IS_SECONDARY}, ereport.asic.zambezi.asu.invalid-wb-destid@interconnect {IS_SECONDARY}, ereport.asic.zambezi.asu.malformed-wb@interconnect {IS_SECONDARY}, ereport.asic.zambezi.asu.invalid-tid-cacheable@interconnect {IS_SECONDARY}; prop error.asic.ultraSPARC-T2plus.interconnect.asu@interconnect -> ereport.asic.zambezi.asu.pending-ram-parity-error@interconnect, ereport.asic.zambezi.asu.pending-tid-ram-parity-error@interconnect, ereport.asic.zambezi.asu.cam-parity-error@interconnect;