/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _nbio_4_3_0_OFFSET_HEADER #define _nbio_4_3_0_OFFSET_HEADER // addressBlock: nbio_nbif0_bif_bx_SYSDEC // base address: 0x0 #define regBIF_BX0_PCIE_INDEX 0x000c #define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 #define regBIF_BX0_PCIE_DATA 0x000d #define regBIF_BX0_PCIE_DATA_BASE_IDX 0 #define regBIF_BX0_PCIE_INDEX2 0x000e #define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 #define regBIF_BX0_PCIE_DATA2 0x000f #define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 #define regBIF_BX0_PCIE_INDEX_HI 0x0010 #define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 #define regBIF_BX0_PCIE_INDEX2_HI 0x0011 #define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 #define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 #define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 #define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 #define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 #define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_0 0x0038 #define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_1 0x0039 #define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_2 0x003a #define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_4 0x003c #define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_5 0x003d #define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_7 0x003f #define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_8 0x0040 #define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_9 0x0041 #define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_10 0x0042 #define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_11 0x0043 #define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_12 0x0044 #define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_13 0x0045 #define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_14 0x0046 #define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 #define regBIF_BX0_BIOS_SCRATCH_15 0x0047 #define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 #define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c #define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 #define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d #define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 #define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e #define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 #define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 #define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 #define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 #define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 #define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 #define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 #define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 #define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 #define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 #define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_10 0x008a #define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_11 0x008b #define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_12 0x008c #define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_13 0x008d #define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_14 0x008e #define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 #define regBIF_BX0_DRIVER_SCRATCH_15 0x008f #define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_0 0x0090 #define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_1 0x0091 #define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_2 0x0092 #define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_3 0x0093 #define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_4 0x0094 #define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_5 0x0095 #define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_6 0x0096 #define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_7 0x0097 #define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_8 0x0098 #define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_9 0x0099 #define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_10 0x009a #define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_11 0x009b #define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_12 0x009c #define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_13 0x009d #define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_14 0x009e #define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 #define regBIF_BX0_FW_SCRATCH_15 0x009f #define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 #define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 #define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 #define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 #define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 #define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 #define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 #define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 #define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 #define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 #define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa #define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 #define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab #define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 // base address: 0x0 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 // base address: 0x0 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 // base address: 0x0 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_PF0_MM_INDEX 0x0000 #define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 #define regBIF_BX_PF0_MM_DATA 0x0001 #define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 #define regBIF_BX_PF0_MM_INDEX_HI 0x0006 #define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 #define regBIF_BX_PF0_RSMU_INDEX 0x0000 #define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 #define regBIF_BX_PF0_RSMU_DATA 0x0001 #define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 #define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 #define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 // base address: 0x0 #define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 #define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 #define regBIF_BX0_BUS_CNTL 0x00e7 #define regBIF_BX0_BUS_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_SCRATCH0 0x00e8 #define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 #define regBIF_BX0_BIF_SCRATCH1 0x00e9 #define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 #define regBIF_BX0_BX_RESET_EN 0x00ed #define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 #define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee #define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 #define regBIF_BX0_BX_RESET_CNTL 0x00f0 #define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 #define regBIF_BX0_INTERRUPT_CNTL 0x00f1 #define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 #define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 #define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 #define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 #define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 #define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd #define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe #define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_FB_EN 0x0100 #define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 #define regBIF_BX0_BIF_INTR_CNTL 0x0101 #define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 #define regBIF_BX0_MEM_TYPE_CNTL 0x0111 #define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_RB_CNTL 0x012f #define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 #define regBIF_BX0_BIF_RB_BASE 0x0130 #define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 #define regBIF_BX0_BIF_RB_RPTR 0x0131 #define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 #define regBIF_BX0_BIF_RB_WPTR 0x0132 #define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 #define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 #define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 // base address: 0x0 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 #define regRCC_DEV0_0_RCC_RESET_EN 0x0088 #define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 #define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 #define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 #define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c #define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 #define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 #define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 #define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 #define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 #define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca #define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd #define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce #define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 #define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 #define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 // base address: 0x0 #define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 #define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 #define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 #define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 #define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 #define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 #define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 #define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 #define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0023 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0024 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0025 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0031 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0032 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0033 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0034 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0035 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0036 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0037 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0038 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0039 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003a #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003b #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003c #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb #define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] // base address: 0x3480 #define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_gdc_GDCDEC // base address: 0x0 #define regGDC0_SHUB_REGS_IF_CTL 0x01c3 #define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 #define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x01cf #define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 #define regGDC0_ATDMA_MISC_CNTL 0x01dd #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 2 #define regGDC0_S2A_MISC_CNTL 0x01df #define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb #define regBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec #define regBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define regBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define regBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa #define regBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 #define regBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 #define regBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define regBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f #define regBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 #define regBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC // base address: 0x0 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 #define regBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 #define regBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0x0 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 #define regRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 #define regRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 #define regRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define regRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 // base address: 0x0 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f #define regRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 #define regRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp // base address: 0xfffe00000000 #define cfgPSWUSCFG0_0_VENDOR_ID 0xfffe00000000 #define cfgPSWUSCFG0_0_DEVICE_ID 0xfffe00000002 #define cfgPSWUSCFG0_0_COMMAND 0xfffe00000004 #define cfgPSWUSCFG0_0_STATUS 0xfffe00000006 #define cfgPSWUSCFG0_0_REVISION_ID 0xfffe00000008 #define cfgPSWUSCFG0_0_PROG_INTERFACE 0xfffe00000009 #define cfgPSWUSCFG0_0_SUB_CLASS 0xfffe0000000a #define cfgPSWUSCFG0_0_BASE_CLASS 0xfffe0000000b #define cfgPSWUSCFG0_0_CACHE_LINE 0xfffe0000000c #define cfgPSWUSCFG0_0_LATENCY 0xfffe0000000d #define cfgPSWUSCFG0_0_HEADER 0xfffe0000000e #define cfgPSWUSCFG0_0_BIST 0xfffe0000000f #define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0xfffe00000018 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0xfffe0000001c #define cfgPSWUSCFG0_0_SECONDARY_STATUS 0xfffe0000001e #define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0xfffe00000020 #define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0xfffe00000024 #define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0xfffe00000028 #define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0xfffe0000002c #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0xfffe00000030 #define cfgPSWUSCFG0_0_CAP_PTR 0xfffe00000034 #define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0xfffe00000038 #define cfgPSWUSCFG0_0_INTERRUPT_LINE 0xfffe0000003c #define cfgPSWUSCFG0_0_INTERRUPT_PIN 0xfffe0000003d #define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0xfffe00000048 #define cfgPSWUSCFG0_0_ADAPTER_ID_W 0xfffe0000004c #define cfgPSWUSCFG0_0_PMI_CAP_LIST 0xfffe00000050 #define cfgPSWUSCFG0_0_PMI_CAP 0xfffe00000052 #define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0xfffe00000054 #define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0xfffe00000058 #define cfgPSWUSCFG0_0_PCIE_CAP 0xfffe0000005a #define cfgPSWUSCFG0_0_DEVICE_CAP 0xfffe0000005c #define cfgPSWUSCFG0_0_DEVICE_CNTL 0xfffe00000060 #define cfgPSWUSCFG0_0_DEVICE_STATUS 0xfffe00000062 #define cfgPSWUSCFG0_0_LINK_CAP 0xfffe00000064 #define cfgPSWUSCFG0_0_LINK_CNTL 0xfffe00000068 #define cfgPSWUSCFG0_0_LINK_STATUS 0xfffe0000006a #define cfgPSWUSCFG0_0_DEVICE_CAP2 0xfffe0000007c #define cfgPSWUSCFG0_0_DEVICE_CNTL2 0xfffe00000080 #define cfgPSWUSCFG0_0_DEVICE_STATUS2 0xfffe00000082 #define cfgPSWUSCFG0_0_LINK_CAP2 0xfffe00000084 #define cfgPSWUSCFG0_0_LINK_CNTL2 0xfffe00000088 #define cfgPSWUSCFG0_0_LINK_STATUS2 0xfffe0000008a #define cfgPSWUSCFG0_0_MSI_CAP_LIST 0xfffe000000a0 #define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0xfffe000000a2 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0xfffe000000a4 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0xfffe000000a8 #define cfgPSWUSCFG0_0_MSI_MSG_DATA 0xfffe000000a8 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0xfffe000000ac #define cfgPSWUSCFG0_0_SSID_CAP_LIST 0xfffe000000c0 #define cfgPSWUSCFG0_0_SSID_CAP 0xfffe000000c4 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0xfffe00000108 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c #define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0xfffe00000110 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0xfffe00000114 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0xfffe00000118 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0xfffe0000011c #define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0xfffe0000011e #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0xfffe00000120 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0xfffe00000154 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0xfffe00000158 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0xfffe00000160 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0xfffe00000164 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0xfffe0000016c #define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0xfffe00000170 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0xfffe00000174 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0xfffe00000178 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0xfffe00000188 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0xfffe00000190 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0xfffe00000194 #define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270 #define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0xfffe00000274 #define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0xfffe00000278 #define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c #define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e #define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280 #define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282 #define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 #define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a #define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c #define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e #define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290 #define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292 #define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294 #define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296 #define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298 #define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a #define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0 #define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0xfffe000002a4 #define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0xfffe000002a6 #define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0 #define cfgPSWUSCFG0_0_PCIE_MC_CAP 0xfffe000002f4 #define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0xfffe000002f6 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0xfffe000002f8 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0xfffe000002fc #define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0xfffe00000300 #define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0xfffe00000304 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0xfffe00000308 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0xfffe0000030c #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314 #define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320 #define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0xfffe00000324 #define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328 #define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0xfffe0000032c #define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0xfffe0000032e #define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0xfffe00000404 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0xfffe00000408 #define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410 #define cfgPSWUSCFG0_0_LINK_CAP_16GT 0xfffe00000414 #define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0xfffe00000418 #define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0xfffe0000041c #define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420 #define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424 #define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428 #define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430 #define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431 #define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432 #define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433 #define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434 #define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435 #define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436 #define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437 #define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438 #define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439 #define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a #define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b #define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c #define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d #define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e #define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f #define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440 #define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0xfffe00000444 #define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0xfffe00000446 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486 #define cfgPSWUSCFG0_0_LINK_CAP_32GT 0xfffe00000504 #define cfgPSWUSCFG0_0_LINK_CNTL_32GT 0xfffe00000508 #define cfgPSWUSCFG0_0_LINK_STATUS_32GT 0xfffe0000050c // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp // base address: 0xfffe10100000 #define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0xfffe10100000 #define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0xfffe10100002 #define cfgBIF_CFG_DEV0_RC0_COMMAND 0xfffe10100004 #define cfgBIF_CFG_DEV0_RC0_STATUS 0xfffe10100006 #define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0xfffe10100008 #define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0xfffe10100009 #define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0xfffe1010000a #define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0xfffe1010000b #define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0xfffe1010000c #define cfgBIF_CFG_DEV0_RC0_LATENCY 0xfffe1010000d #define cfgBIF_CFG_DEV0_RC0_HEADER 0xfffe1010000e #define cfgBIF_CFG_DEV0_RC0_BIST 0xfffe1010000f #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0xfffe10100010 #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_2 0xfffe10100014 #define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0xfffe10100018 #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0xfffe1010001c #define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0xfffe1010001e #define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0xfffe10100020 #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0xfffe10100024 #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0xfffe10100028 #define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0xfffe1010002c #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0xfffe10100030 #define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0xfffe10100034 #define cfgBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0xfffe10100038 #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0xfffe1010003c #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0xfffe1010003d #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0xfffe10100050 #define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0xfffe10100052 #define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0xfffe10100054 #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0xfffe10100058 #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0xfffe1010005a #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0xfffe1010005c #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0xfffe10100060 #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0xfffe10100062 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0xfffe10100064 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0xfffe10100068 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0xfffe1010006a #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0xfffe1010006c #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0xfffe10100070 #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0xfffe10100072 #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0xfffe1010007c #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0xfffe10100080 #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0xfffe10100082 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0xfffe10100084 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0xfffe10100088 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0xfffe1010008a #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0xfffe1010008c #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0xfffe10100090 #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0xfffe10100092 #define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0xfffe101000a0 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0xfffe101000a2 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0xfffe101000a4 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0xfffe101000a8 #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0xfffe101000a8 #define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0xfffe101000aa #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0xfffe101000ac #define cfgBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0xfffe101000ae #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0xfffe101000c0 #define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0xfffe101000c4 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0xfffe10100108 #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c #define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0xfffe10100110 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0xfffe10100114 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0xfffe10100118 #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0xfffe1010011c #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0xfffe1010011e #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0xfffe10100120 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130 #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144 #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148 #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0xfffe10100154 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0xfffe10100158 #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0xfffe10100160 #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0xfffe10100164 #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0xfffe1010016c #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0xfffe10100170 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0xfffe10100174 #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0xfffe10100178 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0xfffe10100188 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0xfffe10100190 #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0xfffe10100194 #define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270 #define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0xfffe10100274 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0xfffe10100278 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0 #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0xfffe101002a4 #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0xfffe101002a6 #define cfgBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400 #define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0xfffe10100404 #define cfgBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0xfffe10100408 #define cfgBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0xfffe10100414 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0xfffe10100418 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0xfffe1010041c #define cfgBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420 #define cfgBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424 #define cfgBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428 #define cfgBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430 #define cfgBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431 #define cfgBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432 #define cfgBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433 #define cfgBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434 #define cfgBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435 #define cfgBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436 #define cfgBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437 #define cfgBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438 #define cfgBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439 #define cfgBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a #define cfgBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b #define cfgBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c #define cfgBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d #define cfgBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e #define cfgBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f #define cfgBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100450 #define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0xfffe10100454 #define cfgBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0xfffe10100456 #define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0xfffe10100458 #define cfgBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0xfffe1010045a #define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0xfffe1010045c #define cfgBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0xfffe1010045e #define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0xfffe10100460 #define cfgBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0xfffe10100462 #define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0xfffe10100464 #define cfgBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0xfffe10100466 #define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0xfffe10100468 #define cfgBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0xfffe1010046a #define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0xfffe1010046c #define cfgBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0xfffe1010046e #define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0xfffe10100470 #define cfgBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0xfffe10100472 #define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0xfffe10100474 #define cfgBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0xfffe10100476 #define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0xfffe10100478 #define cfgBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0xfffe1010047a #define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0xfffe1010047c #define cfgBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0xfffe1010047e #define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0xfffe10100480 #define cfgBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0xfffe10100482 #define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0xfffe10100484 #define cfgBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0xfffe10100486 #define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0xfffe10100488 #define cfgBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0xfffe1010048a #define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0xfffe1010048c #define cfgBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0xfffe1010048e #define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0xfffe10100490 #define cfgBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0xfffe10100492 #define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0xfffe10100494 #define cfgBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0xfffe10100496 #define cfgBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0xfffe10100504 #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0xfffe10100508 #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0xfffe1010050c // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp // base address: 0xfffe10200000 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0xfffe10200000 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0xfffe10200002 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0xfffe10200004 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0xfffe10200006 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0xfffe10200008 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0xfffe10200009 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0xfffe1020000a #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0xfffe1020000b #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0xfffe1020000c #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0xfffe1020000d #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0xfffe1020000e #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0xfffe1020000f #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0xfffe10200010 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0xfffe10200014 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0xfffe10200018 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0xfffe1020001c #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0xfffe10200020 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0xfffe10200024 #define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0xfffe10200028 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0xfffe1020002c #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0xfffe10200030 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0xfffe10200034 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0xfffe1020003c #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0xfffe1020003d #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0xfffe1020003e #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0xfffe1020003f #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0xfffe10200048 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0xfffe1020004c #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0xfffe10200050 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0xfffe10200052 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0xfffe10200054 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0xfffe10200064 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0xfffe10200066 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0xfffe10200068 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0xfffe1020006c #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0xfffe1020006e #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0xfffe10200070 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0xfffe10200074 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0xfffe10200076 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0xfffe10200088 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0xfffe1020008c #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0xfffe1020008e #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0xfffe10200090 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0xfffe10200094 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0xfffe10200096 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0xfffe102000a0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0xfffe102000a2 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0xfffe102000a4 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0xfffe102000a8 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0xfffe102000a8 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0xfffe102000aa #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0xfffe102000ac #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0xfffe102000ac #define cfgBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0xfffe102000ae #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0xfffe102000b0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0xfffe102000b0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0xfffe102000b4 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0xfffe102000c0 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0xfffe102000c2 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0xfffe102000c4 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0xfffe102000c8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10200108 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0xfffe10200110 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0xfffe10200114 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0xfffe10200118 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0xfffe1020011c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0xfffe1020011e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0xfffe10200120 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10200154 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10200158 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0xfffe10200160 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0xfffe10200164 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0xfffe1020016c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0xfffe10200170 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0xfffe10200174 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0xfffe10200178 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10200188 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10200190 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10200194 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0xfffe10200204 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0xfffe10200208 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0xfffe1020020c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0xfffe10200210 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0xfffe10200214 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0xfffe10200218 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0xfffe1020021c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0xfffe10200220 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0xfffe10200224 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0xfffe10200228 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0xfffe1020022c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0xfffe10200230 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0xfffe10200248 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0xfffe1020024c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0xfffe10200254 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0xfffe1020025c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0xfffe1020025e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0xfffe10200274 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0xfffe10200278 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0xfffe102002a4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0xfffe102002a6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0xfffe102002d4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0xfffe102002d6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0xfffe102002f4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0xfffe102002f6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0xfffe102002f8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0xfffe102002fc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0xfffe10200300 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0xfffe10200304 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0xfffe10200308 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0xfffe1020030c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0xfffe10200324 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0xfffe1020032c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0xfffe1020032e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0xfffe10200334 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0xfffe10200338 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0xfffe1020033a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0xfffe10200340 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0xfffe10200346 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020036c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0xfffe10200404 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0xfffe10200408 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0xfffe10200414 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0xfffe10200418 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0xfffe1020041c #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200450 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0xfffe10200454 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0xfffe10200456 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0xfffe10200458 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0xfffe1020045a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0xfffe1020045c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0xfffe1020045e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0xfffe10200460 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0xfffe10200462 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0xfffe10200464 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0xfffe10200466 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0xfffe10200468 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0xfffe1020046a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0xfffe1020046c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0xfffe1020046e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0xfffe10200470 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0xfffe10200472 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0xfffe10200474 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0xfffe10200476 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0xfffe10200478 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0xfffe1020047a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0xfffe1020047c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0xfffe1020047e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0xfffe10200480 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0xfffe10200482 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0xfffe10200484 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0xfffe10200486 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0xfffe10200488 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0xfffe1020048a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0xfffe1020048c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0xfffe1020048e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0xfffe10200490 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0xfffe10200492 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0xfffe10200494 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0xfffe10200496 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0xfffe10200504 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0xfffe10200508 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0xfffe1020050c // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp // base address: 0xfffe10201000 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0xfffe10201000 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0xfffe10201002 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0xfffe10201004 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0xfffe10201006 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0xfffe10201008 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0xfffe10201009 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0xfffe1020100a #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0xfffe1020100b #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0xfffe1020100c #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0xfffe1020100d #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0xfffe1020100e #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0xfffe1020100f #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0xfffe10201010 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0xfffe10201014 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0xfffe10201018 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0xfffe1020101c #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0xfffe10201020 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0xfffe10201024 #define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0xfffe10201028 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0xfffe1020102c #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0xfffe10201030 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0xfffe10201034 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0xfffe1020103c #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0xfffe1020103d #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0xfffe1020103e #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0xfffe1020103f #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0xfffe10201048 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0xfffe1020104c #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0xfffe10201050 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0xfffe10201052 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0xfffe10201054 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0xfffe10201064 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0xfffe10201066 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0xfffe10201068 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0xfffe1020106c #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0xfffe1020106e #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0xfffe10201070 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0xfffe10201074 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0xfffe10201076 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0xfffe10201088 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0xfffe1020108c #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0xfffe1020108e #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0xfffe10201090 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0xfffe10201094 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0xfffe10201096 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0xfffe102010a0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0xfffe102010a2 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0xfffe102010a4 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0xfffe102010a8 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0xfffe102010a8 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0xfffe102010aa #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0xfffe102010ac #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0xfffe102010ac #define cfgBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0xfffe102010ae #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0xfffe102010b0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0xfffe102010b0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0xfffe102010b4 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0xfffe102010c0 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0xfffe102010c2 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0xfffe102010c4 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0xfffe102010c8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10201108 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10201154 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10201158 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0xfffe10201160 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0xfffe10201164 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0xfffe1020116c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0xfffe10201170 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0xfffe10201174 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0xfffe10201178 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10201188 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10201190 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10201194 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0xfffe10201204 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0xfffe10201208 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0xfffe1020120c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0xfffe10201210 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0xfffe10201214 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0xfffe10201218 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0xfffe1020121c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0xfffe10201220 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0xfffe10201224 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0xfffe10201228 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0xfffe1020122c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0xfffe10201230 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0xfffe10201248 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0xfffe1020124c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0xfffe10201254 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0xfffe1020125c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0xfffe1020125e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0xfffe10201274 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0xfffe10201278 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0xfffe102012a4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0xfffe102012a6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0xfffe102012d4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0xfffe102012d6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0xfffe102012f4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0xfffe102012f6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0xfffe102012f8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0xfffe102012fc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0xfffe10201300 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0xfffe10201304 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0xfffe10201308 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0xfffe1020130c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0xfffe10201324 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0xfffe1020132c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0xfffe1020132e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0xfffe10201334 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0xfffe10201338 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0xfffe1020133a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0xfffe10201340 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0xfffe10201346 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020136c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp // base address: 0xfffe10202000 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0xfffe10202000 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0xfffe10202002 #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0xfffe10202004 #define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0xfffe10202006 #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0xfffe10202008 #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0xfffe10202009 #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0xfffe1020200a #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0xfffe1020200b #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0xfffe1020200c #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0xfffe1020200d #define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0xfffe1020200e #define cfgBIF_CFG_DEV0_EPF2_0_BIST 0xfffe1020200f #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0xfffe10202010 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0xfffe10202014 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0xfffe10202018 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0xfffe1020201c #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0xfffe10202020 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0xfffe10202024 #define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0xfffe10202028 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0xfffe1020202c #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0xfffe10202030 #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0xfffe10202034 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0xfffe1020203c #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0xfffe1020203d #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0xfffe1020203e #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0xfffe1020203f #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0xfffe10202048 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0xfffe1020204c #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0xfffe10202050 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0xfffe10202052 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0xfffe10202054 #define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0xfffe10202060 #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0xfffe10202061 #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0xfffe10202062 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0xfffe10202064 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0xfffe10202066 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0xfffe10202068 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0xfffe1020206c #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0xfffe1020206e #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0xfffe10202070 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0xfffe10202074 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0xfffe10202076 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0xfffe10202088 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0xfffe1020208c #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0xfffe1020208e #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0xfffe10202090 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0xfffe10202094 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0xfffe10202096 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0xfffe102020a0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0xfffe102020a2 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0xfffe102020a4 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0xfffe102020a8 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0xfffe102020a8 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA 0xfffe102020aa #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0xfffe102020ac #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0xfffe102020ac #define cfgBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 0xfffe102020ae #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0xfffe102020b0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0xfffe102020b0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0xfffe102020b4 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0xfffe102020c0 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0xfffe102020c2 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0xfffe102020c4 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0xfffe102020c8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10202108 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10202154 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10202158 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0xfffe10202160 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0xfffe10202164 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0xfffe1020216c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0xfffe10202170 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0xfffe10202174 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0xfffe10202178 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10202188 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10202190 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10202194 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0xfffe10202204 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0xfffe10202208 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0xfffe1020220c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0xfffe10202210 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0xfffe10202214 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0xfffe10202218 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0xfffe1020221c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0xfffe10202220 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0xfffe10202224 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0xfffe10202228 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0xfffe1020222c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0xfffe10202230 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0xfffe10202248 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0xfffe1020224c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0xfffe10202254 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0xfffe1020225c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0xfffe1020225e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0xfffe102022a4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0xfffe102022a6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0xfffe102022d4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0xfffe102022d6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0xfffe1020232c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0xfffe1020232e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp // base address: 0xfffe10203000 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0xfffe10203000 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0xfffe10203002 #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0xfffe10203004 #define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0xfffe10203006 #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0xfffe10203008 #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0xfffe10203009 #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0xfffe1020300a #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0xfffe1020300b #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0xfffe1020300c #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0xfffe1020300d #define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0xfffe1020300e #define cfgBIF_CFG_DEV0_EPF3_0_BIST 0xfffe1020300f #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0xfffe10203010 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0xfffe10203014 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0xfffe10203018 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0xfffe1020301c #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0xfffe10203020 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0xfffe10203024 #define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0xfffe10203028 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0xfffe1020302c #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0xfffe10203030 #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0xfffe10203034 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0xfffe1020303c #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0xfffe1020303d #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0xfffe1020303e #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0xfffe1020303f #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0xfffe10203048 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0xfffe1020304c #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0xfffe10203050 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0xfffe10203052 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0xfffe10203054 #define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0xfffe10203060 #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0xfffe10203061 #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0xfffe10203062 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0xfffe10203064 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0xfffe10203066 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0xfffe10203068 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0xfffe1020306c #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0xfffe1020306e #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0xfffe10203070 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0xfffe10203074 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0xfffe10203076 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0xfffe10203088 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0xfffe1020308c #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0xfffe1020308e #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0xfffe10203090 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0xfffe10203094 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0xfffe10203096 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0xfffe102030a0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0xfffe102030a2 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0xfffe102030a4 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0xfffe102030a8 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0xfffe102030a8 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA 0xfffe102030aa #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0xfffe102030ac #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0xfffe102030ac #define cfgBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 0xfffe102030ae #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0xfffe102030b0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0xfffe102030b0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0xfffe102030b4 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0xfffe102030c0 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0xfffe102030c2 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0xfffe102030c4 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0xfffe102030c8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10203108 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10203154 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10203158 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0xfffe10203160 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0xfffe10203164 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0xfffe1020316c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0xfffe10203170 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0xfffe10203174 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0xfffe10203178 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10203188 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10203190 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10203194 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0xfffe10203204 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0xfffe10203208 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0xfffe1020320c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0xfffe10203210 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0xfffe10203214 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0xfffe10203218 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0xfffe1020321c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0xfffe10203220 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0xfffe10203224 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0xfffe10203228 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0xfffe1020322c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0xfffe10203230 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0xfffe10203248 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0xfffe1020324c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0xfffe10203254 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0xfffe1020325c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0xfffe1020325e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0xfffe102032a4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0xfffe102032a6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0xfffe102032d4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0xfffe102032d6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0xfffe1020332c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0xfffe1020332e // addressBlock: nbio_nbif0_bif_bx_SYSDEC // base address: 0x30200000 #define cfgPCIE_INDEX 0x30200030 #define cfgPCIE_DATA 0x30200034 #define cfgPCIE_INDEX2 0x30200038 #define cfgPCIE_DATA2 0x3020003c #define cfgPCIE_INDEX_HI 0x30200040 #define cfgPCIE_INDEX2_HI 0x30200044 #define cfgSBIOS_SCRATCH_0 0x30200120 #define cfgSBIOS_SCRATCH_1 0x30200124 #define cfgSBIOS_SCRATCH_2 0x30200128 #define cfgSBIOS_SCRATCH_3 0x3020012c #define cfgBIOS_SCRATCH_0 0x30200130 #define cfgBIOS_SCRATCH_1 0x30200134 #define cfgBIOS_SCRATCH_2 0x30200138 #define cfgBIOS_SCRATCH_3 0x3020013c #define cfgBIOS_SCRATCH_4 0x30200140 #define cfgBIOS_SCRATCH_5 0x30200144 #define cfgBIOS_SCRATCH_6 0x30200148 #define cfgBIOS_SCRATCH_7 0x3020014c #define cfgBIOS_SCRATCH_8 0x30200150 #define cfgBIOS_SCRATCH_9 0x30200154 #define cfgBIOS_SCRATCH_10 0x30200158 #define cfgBIOS_SCRATCH_11 0x3020015c #define cfgBIOS_SCRATCH_12 0x30200160 #define cfgBIOS_SCRATCH_13 0x30200164 #define cfgBIOS_SCRATCH_14 0x30200168 #define cfgBIOS_SCRATCH_15 0x3020016c #define cfgBIF_RLC_INTR_CNTL 0x30200180 #define cfgBIF_VCE_INTR_CNTL 0x30200184 #define cfgBIF_UVD_INTR_CNTL 0x30200188 #define cfgGFX_MMIOREG_CAM_ADDR0 0x30200200 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30200204 #define cfgGFX_MMIOREG_CAM_ADDR1 0x30200208 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3020020c #define cfgGFX_MMIOREG_CAM_ADDR2 0x30200210 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30200214 #define cfgGFX_MMIOREG_CAM_ADDR3 0x30200218 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3020021c #define cfgGFX_MMIOREG_CAM_ADDR4 0x30200220 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30200224 #define cfgGFX_MMIOREG_CAM_ADDR5 0x30200228 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3020022c #define cfgGFX_MMIOREG_CAM_ADDR6 0x30200230 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30200234 #define cfgGFX_MMIOREG_CAM_ADDR7 0x30200238 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3020023c #define cfgGFX_MMIOREG_CAM_CNTL 0x30200240 #define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30200244 #define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30200248 #define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3020024c #define cfgDRIVER_SCRATCH_0 0x30200250 #define cfgDRIVER_SCRATCH_1 0x30200254 #define cfgDRIVER_SCRATCH_2 0x30200258 #define cfgDRIVER_SCRATCH_3 0x3020025c #define cfgDRIVER_SCRATCH_4 0x30200260 #define cfgDRIVER_SCRATCH_5 0x30200264 #define cfgDRIVER_SCRATCH_6 0x30200268 #define cfgDRIVER_SCRATCH_7 0x3020026c #define cfgDRIVER_SCRATCH_8 0x30200270 #define cfgDRIVER_SCRATCH_9 0x30200274 #define cfgDRIVER_SCRATCH_10 0x30200278 #define cfgDRIVER_SCRATCH_11 0x3020027c #define cfgDRIVER_SCRATCH_12 0x30200280 #define cfgDRIVER_SCRATCH_13 0x30200284 #define cfgDRIVER_SCRATCH_14 0x30200288 #define cfgDRIVER_SCRATCH_15 0x3020028c #define cfgFW_SCRATCH_0 0x30200290 #define cfgFW_SCRATCH_1 0x30200294 #define cfgFW_SCRATCH_2 0x30200298 #define cfgFW_SCRATCH_3 0x3020029c #define cfgFW_SCRATCH_4 0x302002a0 #define cfgFW_SCRATCH_5 0x302002a4 #define cfgFW_SCRATCH_6 0x302002a8 #define cfgFW_SCRATCH_7 0x302002ac #define cfgFW_SCRATCH_8 0x302002b0 #define cfgFW_SCRATCH_9 0x302002b4 #define cfgFW_SCRATCH_10 0x302002b8 #define cfgFW_SCRATCH_11 0x302002bc #define cfgFW_SCRATCH_12 0x302002c0 #define cfgFW_SCRATCH_13 0x302002c4 #define cfgFW_SCRATCH_14 0x302002c8 #define cfgFW_SCRATCH_15 0x302002cc #define cfgSBIOS_SCRATCH_4 0x302002d0 #define cfgSBIOS_SCRATCH_5 0x302002d4 #define cfgSBIOS_SCRATCH_6 0x302002d8 #define cfgSBIOS_SCRATCH_7 0x302002dc #define cfgSBIOS_SCRATCH_8 0x302002e0 #define cfgSBIOS_SCRATCH_9 0x302002e4 #define cfgSBIOS_SCRATCH_10 0x302002e8 #define cfgSBIOS_SCRATCH_11 0x302002ec #define cfgSBIOS_SCRATCH_12 0x302002f0 #define cfgSBIOS_SCRATCH_13 0x302002f4 #define cfgSBIOS_SCRATCH_14 0x302002f8 #define cfgSBIOS_SCRATCH_15 0x302002fc // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 // base address: 0x30200000 #define cfgDN_PCIE_RESERVED 0x30203600 #define cfgDN_PCIE_SCRATCH 0x30203604 #define cfgDN_PCIE_CNTL 0x3020360c #define cfgDN_PCIE_CONFIG_CNTL 0x30203610 #define cfgDN_PCIE_RX_CNTL2 0x30203614 #define cfgDN_PCIE_BUS_CNTL 0x30203618 #define cfgDN_PCIE_CFG_CNTL 0x3020361c #define cfgDN_PCIE_STRAP_F0 0x30203620 #define cfgDN_PCIE_STRAP_MISC 0x30203624 #define cfgDN_PCIE_STRAP_MISC2 0x30203628 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 // base address: 0x30200000 #define cfgPCIE_ERR_CNTL 0x30203630 #define cfgPCIE_RX_CNTL 0x30203634 #define cfgPCIE_LC_SPEED_CNTL 0x30203638 #define cfgPCIE_LC_CNTL2 0x3020363c #define cfgPCIEP_STRAP_MISC 0x30203640 #define cfgLTR_MSG_INFO_FROM_EP 0x30203644 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 // base address: 0x30200000 #define cfgEP_PCIE_SCRATCH 0x30203580 #define cfgEP_PCIE_CNTL 0x30203588 #define cfgEP_PCIE_INT_CNTL 0x3020358c #define cfgEP_PCIE_INT_STATUS 0x30203590 #define cfgEP_PCIE_RX_CNTL2 0x30203594 #define cfgEP_PCIE_BUS_CNTL 0x30203598 #define cfgEP_PCIE_CFG_CNTL 0x3020359c #define cfgEP_PCIE_TX_LTR_CNTL 0x302035a4 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x302035a8 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x302035a9 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x302035aa #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x302035ab #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x302035ac #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x302035ad #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x302035ae #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x302035af #define cfgEP_PCIE_STRAP_MISC 0x302035b0 #define cfgEP_PCIE_STRAP_MISC2 0x302035b4 #define cfgEP_PCIE_F0_DPA_CAP 0x302035bc #define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x302035c0 #define cfgEP_PCIE_F0_DPA_CNTL 0x302035c1 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x302035c3 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x302035c4 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x302035c5 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x302035c6 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x302035c7 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x302035c8 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x302035c9 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x302035ca #define cfgEP_PCIE_PME_CONTROL 0x302035cb #define cfgEP_PCIEP_RESERVED 0x302035cc #define cfgEP_PCIE_TX_CNTL 0x302035d4 #define cfgEP_PCIE_TX_REQUESTER_ID 0x302035d8 #define cfgEP_PCIE_ERR_CNTL 0x302035dc #define cfgEP_PCIE_RX_CNTL 0x302035e0 #define cfgEP_PCIE_LC_SPEED_CNTL 0x302035e4 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC // base address: 0x30200000 #define cfgBIF_BX_PF0_MM_INDEX 0x30200000 #define cfgBIF_BX_PF0_MM_DATA 0x30200004 #define cfgBIF_BX_PF0_MM_INDEX_HI 0x30200018 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 // base address: 0x30200000 #define cfgCC_BIF_BX_STRAP0 0x30203808 #define cfgCC_BIF_BX_PINSTRAP0 0x30203810 #define cfgBIF_MM_INDACCESS_CNTL 0x30203818 #define cfgBUS_CNTL 0x3020381c #define cfgBIF_SCRATCH0 0x30203820 #define cfgBIF_SCRATCH1 0x30203824 #define cfgBX_RESET_EN 0x30203834 #define cfgMM_CFGREGS_CNTL 0x30203838 #define cfgBX_RESET_CNTL 0x30203840 #define cfgINTERRUPT_CNTL 0x30203844 #define cfgINTERRUPT_CNTL2 0x30203848 #define cfgCLKREQB_PAD_CNTL 0x30203860 #define cfgBIF_FEATURES_CONTROL_MISC 0x3020386c #define cfgHDP_ATOMIC_CONTROL_MISC 0x30203870 #define cfgBIF_DOORBELL_CNTL 0x30203874 #define cfgBIF_DOORBELL_INT_CNTL 0x30203878 #define cfgBIF_FB_EN 0x30203880 #define cfgBIF_INTR_CNTL 0x30203884 #define cfgBIF_MST_TRANS_PENDING_VF 0x302038a4 #define cfgBIF_SLV_TRANS_PENDING_VF 0x302038a8 #define cfgBACO_CNTL 0x302038ac #define cfgBIF_BACO_EXIT_TIME0 0x302038b0 #define cfgBIF_BACO_EXIT_TIMER1 0x302038b4 #define cfgBIF_BACO_EXIT_TIMER2 0x302038b8 #define cfgBIF_BACO_EXIT_TIMER3 0x302038bc #define cfgBIF_BACO_EXIT_TIMER4 0x302038c0 #define cfgMEM_TYPE_CNTL 0x302038c4 #define cfgNBIF_GFX_ADDR_LUT_CNTL 0x302038cc #define cfgNBIF_GFX_ADDR_LUT_0 0x302038d0 #define cfgNBIF_GFX_ADDR_LUT_1 0x302038d4 #define cfgNBIF_GFX_ADDR_LUT_2 0x302038d8 #define cfgNBIF_GFX_ADDR_LUT_3 0x302038dc #define cfgNBIF_GFX_ADDR_LUT_4 0x302038e0 #define cfgNBIF_GFX_ADDR_LUT_5 0x302038e4 #define cfgNBIF_GFX_ADDR_LUT_6 0x302038e8 #define cfgNBIF_GFX_ADDR_LUT_7 0x302038ec #define cfgNBIF_GFX_ADDR_LUT_8 0x302038f0 #define cfgNBIF_GFX_ADDR_LUT_9 0x302038f4 #define cfgNBIF_GFX_ADDR_LUT_10 0x302038f8 #define cfgNBIF_GFX_ADDR_LUT_11 0x302038fc #define cfgNBIF_GFX_ADDR_LUT_12 0x30203900 #define cfgNBIF_GFX_ADDR_LUT_13 0x30203904 #define cfgNBIF_GFX_ADDR_LUT_14 0x30203908 #define cfgNBIF_GFX_ADDR_LUT_15 0x3020390c #define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30203934 #define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30203938 #define cfgBIF_RB_CNTL 0x3020393c #define cfgBIF_RB_BASE 0x30203940 #define cfgBIF_RB_RPTR 0x30203944 #define cfgBIF_RB_WPTR 0x30203948 #define cfgBIF_RB_WPTR_ADDR_HI 0x3020394c #define cfgBIF_RB_WPTR_ADDR_LO 0x30203950 #define cfgMAILBOX_INDEX 0x30203954 #define cfgBIF_MP1_INTR_CTRL 0x30203988 #define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30203994 #define cfgBIF_PERSTB_PAD_CNTL 0x302039a0 #define cfgBIF_PX_EN_PAD_CNTL 0x302039a4 #define cfgBIF_REFPADKIN_PAD_CNTL 0x302039a8 #define cfgBIF_CLKREQB_PAD_CNTL 0x302039ac #define cfgBIF_PWRBRK_PAD_CNTL 0x302039b0 #define cfgBIF_WAKEB_PAD_CNTL 0x302039b4 #define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x302039b8 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 // base address: 0x30200000 #define cfgRCC_ERR_INT_CNTL 0x30203698 #define cfgRCC_BACO_CNTL_MISC 0x3020369c #define cfgRCC_RESET_EN 0x302036a0 #define cfgRCC_VDM_SUPPORT 0x302036a4 #define cfgRCC_MARGIN_PARAM_CNTL0 0x302036a8 #define cfgRCC_MARGIN_PARAM_CNTL1 0x302036ac #define cfgRCC_GPUIOV_REGION 0x302036b0 #define cfgRCC_PEER_REG_RANGE0 0x30203778 #define cfgRCC_PEER_REG_RANGE1 0x3020377c #define cfgRCC_BUS_CNTL 0x30203784 #define cfgRCC_CONFIG_CNTL 0x30203788 #define cfgRCC_CONFIG_F0_BASE 0x30203798 #define cfgRCC_CONFIG_APER_SIZE 0x3020379c #define cfgRCC_CONFIG_REG_APER_SIZE 0x302037a0 #define cfgRCC_XDMA_LO 0x302037a4 #define cfgRCC_XDMA_HI 0x302037a8 #define cfgRCC_FEATURES_CONTROL_MISC 0x302037ac #define cfgRCC_BUSNUM_CNTL1 0x302037b0 #define cfgRCC_BUSNUM_LIST0 0x302037b4 #define cfgRCC_BUSNUM_LIST1 0x302037b8 #define cfgRCC_BUSNUM_CNTL2 0x302037bc #define cfgRCC_CAPTURE_HOST_BUSNUM 0x302037c0 #define cfgRCC_HOST_BUSNUM 0x302037c4 #define cfgRCC_PEER0_FB_OFFSET_HI 0x302037c8 #define cfgRCC_PEER0_FB_OFFSET_LO 0x302037cc #define cfgRCC_PEER1_FB_OFFSET_HI 0x302037d0 #define cfgRCC_PEER1_FB_OFFSET_LO 0x302037d4 #define cfgRCC_PEER2_FB_OFFSET_HI 0x302037d8 #define cfgRCC_PEER2_FB_OFFSET_LO 0x302037dc #define cfgRCC_PEER3_FB_OFFSET_HI 0x302037e0 #define cfgRCC_PEER3_FB_OFFSET_LO 0x302037e4 #define cfgRCC_DEVFUNCNUM_LIST0 0x302037e8 #define cfgRCC_DEVFUNCNUM_LIST1 0x302037ec #define cfgRCC_DEV0_LINK_CNTL 0x302037f4 #define cfgRCC_CMN_LINK_CNTL 0x302037f8 #define cfgRCC_EP_REQUESTERID_RESTORE 0x302037fc #define cfgRCC_LTR_LSWITCH_CNTL 0x30203800 #define cfgRCC_MH_ARB_CNTL 0x30203804 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 // base address: 0x30200000 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30242000 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30242004 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30242008 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3024200c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30242010 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30242014 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30242018 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3024201c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30242020 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30242024 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30242028 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3024202c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30242030 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30242034 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30242038 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3024203c #define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30243000 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 // base address: 0x30200000 #define cfgRCC_BIF_STRAP0 0x30203480 #define cfgRCC_BIF_STRAP1 0x30203484 #define cfgRCC_BIF_STRAP2 0x30203488 #define cfgRCC_BIF_STRAP3 0x3020348c #define cfgRCC_BIF_STRAP4 0x30203490 #define cfgRCC_BIF_STRAP5 0x30203494 #define cfgRCC_BIF_STRAP6 0x30203498 #define cfgRCC_DEV0_PORT_STRAP0 0x3020349c #define cfgRCC_DEV0_PORT_STRAP1 0x302034a0 #define cfgRCC_DEV0_PORT_STRAP10 0x302034a4 #define cfgRCC_DEV0_PORT_STRAP11 0x302034a8 #define cfgRCC_DEV0_PORT_STRAP12 0x302034ac #define cfgRCC_DEV0_PORT_STRAP13 0x302034b0 #define cfgRCC_DEV0_PORT_STRAP14 0x302034b4 #define cfgRCC_DEV0_PORT_STRAP2 0x302034b8 #define cfgRCC_DEV0_PORT_STRAP3 0x302034bc #define cfgRCC_DEV0_PORT_STRAP4 0x302034c0 #define cfgRCC_DEV0_PORT_STRAP5 0x302034c4 #define cfgRCC_DEV0_PORT_STRAP6 0x302034c8 #define cfgRCC_DEV0_PORT_STRAP7 0x302034cc #define cfgRCC_DEV0_PORT_STRAP8 0x302034d0 #define cfgRCC_DEV0_PORT_STRAP9 0x302034d4 #define cfgRCC_DEV0_EPF0_STRAP0 0x302034d8 #define cfgRCC_DEV0_EPF0_STRAP1 0x302034dc #define cfgRCC_DEV0_EPF0_STRAP13 0x302034e0 #define cfgRCC_DEV0_EPF0_STRAP14 0x302034e4 #define cfgRCC_DEV0_EPF0_STRAP15 0x302034e8 #define cfgRCC_DEV0_EPF0_STRAP16 0x302034ec #define cfgRCC_DEV0_EPF0_STRAP17 0x302034f0 #define cfgRCC_DEV0_EPF0_STRAP18 0x302034f4 #define cfgRCC_DEV0_EPF0_STRAP2 0x302034f8 #define cfgRCC_DEV0_EPF0_STRAP26 0x302034fc #define cfgRCC_DEV0_EPF0_STRAP3 0x30203500 #define cfgRCC_DEV0_EPF0_STRAP4 0x30203504 #define cfgRCC_DEV0_EPF0_STRAP5 0x30203508 #define cfgRCC_DEV0_EPF0_STRAP8 0x3020350c #define cfgRCC_DEV0_EPF0_STRAP9 0x30203510 #define cfgRCC_DEV0_EPF1_STRAP0 0x30203514 #define cfgRCC_DEV0_EPF1_STRAP2 0x30203544 #define cfgRCC_DEV0_EPF1_STRAP20 0x30203548 #define cfgRCC_DEV0_EPF1_STRAP21 0x3020354c #define cfgRCC_DEV0_EPF1_STRAP22 0x30203550 #define cfgRCC_DEV0_EPF1_STRAP23 0x30203554 #define cfgRCC_DEV0_EPF1_STRAP24 0x30203558 #define cfgRCC_DEV0_EPF1_STRAP25 0x3020355c #define cfgRCC_DEV0_EPF1_STRAP3 0x30203560 #define cfgRCC_DEV0_EPF1_STRAP4 0x30203564 #define cfgRCC_DEV0_EPF1_STRAP5 0x30203568 #define cfgRCC_DEV0_EPF1_STRAP6 0x3020356c #define cfgRCC_DEV0_EPF1_STRAP7 0x30203570 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 // base address: 0x30200000 #define cfgBIF_BX_PF_BIF_BME_STATUS 0x3020382c #define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30203830 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3020384c #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30203850 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30203854 #define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30203858 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3020385c #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x30203864 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x30203868 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30203898 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3020389c #define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x302038a0 #define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x302038c8 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30203958 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3020395c #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30203960 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30203964 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30203968 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3020396c #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30203970 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30203974 #define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30203978 #define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3020397c #define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30203980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] // base address: 0x30203480 #define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30203694 #define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30203780 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3020378c #define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30203790 #define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30203794 // addressBlock: nbio_nbif0_gdc_GDCDEC // base address: 0x30200000 #define cfgSHUB_REGS_IF_CTL 0x30203b8c #define cfgNGDC_MGCG_CTRL 0x30203ba8 #define cfgNGDC_RESERVED_0 0x30203bac #define cfgNGDC_RESERVED_1 0x30203bb0 #define cfgATDMA_MISC_CNTL 0x30203bf4 #define cfgS2A_MISC_CNTL 0x30203bfc #define cfgNGDC_PG_MISC_CTRL 0x30203c60 #define cfgNGDC_PGMST_CTRL 0x30203c64 #define cfgNGDC_PGSLV_CTRL 0x30203c68 // addressBlock: nbio_nbif0_bif_swus_SUMDEC // base address: 0x100000 #define cfgSUM_INDEX 0x1000e0 #define cfgSUM_DATA 0x1000e4 #define cfgSUM_INDEX_HI 0x1000ec // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec // base address: 0xfffe30000000 #define cfgSHADOW_COMMAND 0xfffe30000004 #define cfgSHADOW_BASE_ADDR_1 0xfffe30000010 #define cfgSHADOW_BASE_ADDR_2 0xfffe30000014 #define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018 #define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c #define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020 #define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024 #define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028 #define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c #define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030 #define cfgSUC_INDEX 0xfffe300000e0 #define cfgSUC_DATA 0xfffe300000e4 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 // base address: 0x0 #define cfgBIF_BX_PF1_MM_INDEX 0x0000 #define cfgBIF_BX_PF1_MM_DATA 0x0004 #define cfgBIF_BX_PF1_MM_INDEX_HI 0x0018 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp // base address: 0xfffe10300000 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0xfffe10300000 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0xfffe10300002 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0xfffe10300004 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0xfffe10300006 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0xfffe10300008 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0xfffe10300009 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0xfffe1030000a #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0xfffe1030000b #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0xfffe1030000c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0xfffe1030000d #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0xfffe1030000e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0xfffe1030000f #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0xfffe10300010 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0xfffe10300014 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0xfffe10300018 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0xfffe1030001c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0xfffe10300020 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0xfffe10300024 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0xfffe10300028 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0xfffe1030002c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0xfffe10300030 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0xfffe10300034 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0xfffe1030003c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0xfffe1030003d #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0xfffe1030003e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0xfffe1030003f #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0xfffe10300064 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0xfffe10300066 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0xfffe10300068 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0xfffe1030006c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0xfffe1030006e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0xfffe10300070 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0xfffe10300074 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0xfffe10300076 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0xfffe10300088 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0xfffe1030008c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0xfffe1030008e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0xfffe10300090 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0xfffe10300094 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0xfffe10300096 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0xfffe103000a0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0xfffe103000a2 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0xfffe103000a4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0xfffe103000a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0xfffe103000a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA 0xfffe103000aa #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0xfffe103000ac #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0xfffe103000ac #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_EXT_MSG_DATA_64 0xfffe103000ae #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0xfffe103000b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0xfffe103000b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0xfffe103000b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0xfffe103000c0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0xfffe103000c2 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0xfffe103000c4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0xfffe103000c8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0xfffe10300108 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0xfffe10300154 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0xfffe10300158 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0xfffe10300160 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0xfffe10300164 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0xfffe1030016c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0xfffe10300170 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0xfffe10300174 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0xfffe10300178 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0xfffe10300188 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0xfffe10300190 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0xfffe10300194 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0xfffe1030032c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0xfffe1030032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp // base address: 0xfffe10301000 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0xfffe10301000 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0xfffe10301002 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0xfffe10301004 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0xfffe10301006 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0xfffe10301008 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0xfffe10301009 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0xfffe1030100a #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0xfffe1030100b #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0xfffe1030100c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0xfffe1030100d #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0xfffe1030100e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0xfffe1030100f #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0xfffe10301010 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0xfffe10301014 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0xfffe10301018 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0xfffe1030101c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0xfffe10301020 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0xfffe10301024 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0xfffe10301028 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0xfffe1030102c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0xfffe10301030 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0xfffe10301034 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0xfffe1030103c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0xfffe1030103d #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0xfffe1030103e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0xfffe1030103f #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0xfffe10301064 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0xfffe10301066 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0xfffe10301068 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0xfffe1030106c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0xfffe1030106e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0xfffe10301070 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0xfffe10301074 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0xfffe10301076 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0xfffe10301088 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0xfffe1030108c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0xfffe1030108e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0xfffe10301090 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0xfffe10301094 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0xfffe10301096 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0xfffe103010a0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0xfffe103010a2 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0xfffe103010a4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0xfffe103010a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0xfffe103010a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA 0xfffe103010aa #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0xfffe103010ac #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0xfffe103010ac #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_EXT_MSG_DATA_64 0xfffe103010ae #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0xfffe103010b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0xfffe103010b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0xfffe103010b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0xfffe103010c0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0xfffe103010c2 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0xfffe103010c4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0xfffe103010c8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0xfffe10301108 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0xfffe10301154 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0xfffe10301158 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0xfffe10301160 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0xfffe10301164 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0xfffe1030116c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0xfffe10301170 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0xfffe10301174 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0xfffe10301178 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0xfffe10301188 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0xfffe10301190 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0xfffe10301194 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0xfffe1030132c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0xfffe1030132e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp // base address: 0xfffe10302000 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0xfffe10302000 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0xfffe10302002 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0xfffe10302004 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0xfffe10302006 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0xfffe10302008 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0xfffe10302009 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0xfffe1030200a #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0xfffe1030200b #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0xfffe1030200c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0xfffe1030200d #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0xfffe1030200e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0xfffe1030200f #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0xfffe10302010 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0xfffe10302014 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0xfffe10302018 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0xfffe1030201c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0xfffe10302020 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0xfffe10302024 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0xfffe10302028 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0xfffe1030202c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0xfffe10302030 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0xfffe10302034 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0xfffe1030203c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0xfffe1030203d #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0xfffe1030203e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0xfffe1030203f #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0xfffe10302064 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0xfffe10302066 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0xfffe10302068 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0xfffe1030206c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0xfffe1030206e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0xfffe10302070 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0xfffe10302074 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0xfffe10302076 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0xfffe10302088 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0xfffe1030208c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0xfffe1030208e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0xfffe10302090 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0xfffe10302094 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0xfffe10302096 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0xfffe103020a0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0xfffe103020a2 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0xfffe103020a4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0xfffe103020a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0xfffe103020a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA 0xfffe103020aa #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0xfffe103020ac #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0xfffe103020ac #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_EXT_MSG_DATA_64 0xfffe103020ae #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0xfffe103020b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0xfffe103020b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0xfffe103020b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0xfffe103020c0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0xfffe103020c2 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0xfffe103020c4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0xfffe103020c8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0xfffe10302108 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0xfffe10302154 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0xfffe10302158 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0xfffe10302160 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0xfffe10302164 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0xfffe1030216c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0xfffe10302170 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0xfffe10302174 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0xfffe10302178 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0xfffe10302188 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0xfffe10302190 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0xfffe10302194 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0xfffe1030232c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0xfffe1030232e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp // base address: 0xfffe10303000 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0xfffe10303000 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0xfffe10303002 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0xfffe10303004 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0xfffe10303006 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0xfffe10303008 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0xfffe10303009 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0xfffe1030300a #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0xfffe1030300b #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0xfffe1030300c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0xfffe1030300d #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0xfffe1030300e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0xfffe1030300f #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0xfffe10303010 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0xfffe10303014 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0xfffe10303018 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0xfffe1030301c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0xfffe10303020 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0xfffe10303024 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0xfffe10303028 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0xfffe1030302c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0xfffe10303030 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0xfffe10303034 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0xfffe1030303c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0xfffe1030303d #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0xfffe1030303e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0xfffe1030303f #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0xfffe10303064 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0xfffe10303066 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0xfffe10303068 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0xfffe1030306c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0xfffe1030306e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0xfffe10303070 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0xfffe10303074 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0xfffe10303076 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0xfffe10303088 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0xfffe1030308c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0xfffe1030308e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0xfffe10303090 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0xfffe10303094 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0xfffe10303096 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0xfffe103030a0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0xfffe103030a2 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0xfffe103030a4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0xfffe103030a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0xfffe103030a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA 0xfffe103030aa #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0xfffe103030ac #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0xfffe103030ac #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_EXT_MSG_DATA_64 0xfffe103030ae #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0xfffe103030b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0xfffe103030b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0xfffe103030b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0xfffe103030c0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0xfffe103030c2 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0xfffe103030c4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0xfffe103030c8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0xfffe10303108 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0xfffe10303154 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0xfffe10303158 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0xfffe10303160 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0xfffe10303164 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0xfffe1030316c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0xfffe10303170 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0xfffe10303174 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0xfffe10303178 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0xfffe10303188 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0xfffe10303190 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0xfffe10303194 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0xfffe1030332c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0xfffe1030332e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp // base address: 0xfffe10304000 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0xfffe10304000 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0xfffe10304002 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0xfffe10304004 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0xfffe10304006 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0xfffe10304008 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0xfffe10304009 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0xfffe1030400a #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0xfffe1030400b #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0xfffe1030400c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0xfffe1030400d #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0xfffe1030400e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0xfffe1030400f #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0xfffe10304010 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0xfffe10304014 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0xfffe10304018 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0xfffe1030401c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0xfffe10304020 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0xfffe10304024 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0xfffe10304028 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0xfffe1030402c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0xfffe10304030 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0xfffe10304034 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0xfffe1030403c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0xfffe1030403d #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0xfffe1030403e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0xfffe1030403f #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0xfffe10304064 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0xfffe10304066 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0xfffe10304068 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0xfffe1030406c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0xfffe1030406e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0xfffe10304070 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0xfffe10304074 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0xfffe10304076 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0xfffe10304088 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0xfffe1030408c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0xfffe1030408e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0xfffe10304090 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0xfffe10304094 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0xfffe10304096 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0xfffe103040a0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0xfffe103040a2 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0xfffe103040a4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0xfffe103040a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0xfffe103040a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA 0xfffe103040aa #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0xfffe103040ac #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0xfffe103040ac #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_EXT_MSG_DATA_64 0xfffe103040ae #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0xfffe103040b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0xfffe103040b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0xfffe103040b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0xfffe103040c0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0xfffe103040c2 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0xfffe103040c4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0xfffe103040c8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0xfffe10304108 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0xfffe10304154 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0xfffe10304158 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0xfffe10304160 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0xfffe10304164 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0xfffe1030416c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0xfffe10304170 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0xfffe10304174 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0xfffe10304178 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0xfffe10304188 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0xfffe10304190 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0xfffe10304194 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0xfffe1030432c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0xfffe1030432e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp // base address: 0xfffe10305000 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0xfffe10305000 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0xfffe10305002 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0xfffe10305004 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0xfffe10305006 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0xfffe10305008 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0xfffe10305009 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0xfffe1030500a #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0xfffe1030500b #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0xfffe1030500c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0xfffe1030500d #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0xfffe1030500e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0xfffe1030500f #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0xfffe10305010 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0xfffe10305014 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0xfffe10305018 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0xfffe1030501c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0xfffe10305020 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0xfffe10305024 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0xfffe10305028 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0xfffe1030502c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0xfffe10305030 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0xfffe10305034 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0xfffe1030503c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0xfffe1030503d #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0xfffe1030503e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0xfffe1030503f #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0xfffe10305064 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0xfffe10305066 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0xfffe10305068 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0xfffe1030506c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0xfffe1030506e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0xfffe10305070 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0xfffe10305074 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0xfffe10305076 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0xfffe10305088 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0xfffe1030508c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0xfffe1030508e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0xfffe10305090 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0xfffe10305094 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0xfffe10305096 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0xfffe103050a0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0xfffe103050a2 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0xfffe103050a4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0xfffe103050a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0xfffe103050a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA 0xfffe103050aa #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0xfffe103050ac #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0xfffe103050ac #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_EXT_MSG_DATA_64 0xfffe103050ae #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0xfffe103050b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0xfffe103050b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0xfffe103050b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0xfffe103050c0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0xfffe103050c2 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0xfffe103050c4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0xfffe103050c8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0xfffe10305108 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0xfffe10305154 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0xfffe10305158 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0xfffe10305160 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0xfffe10305164 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0xfffe1030516c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0xfffe10305170 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0xfffe10305174 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0xfffe10305178 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0xfffe10305188 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0xfffe10305190 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0xfffe10305194 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0xfffe1030532c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0xfffe1030532e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp // base address: 0xfffe10306000 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0xfffe10306000 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0xfffe10306002 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0xfffe10306004 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0xfffe10306006 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0xfffe10306008 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0xfffe10306009 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0xfffe1030600a #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0xfffe1030600b #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0xfffe1030600c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0xfffe1030600d #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0xfffe1030600e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0xfffe1030600f #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0xfffe10306010 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0xfffe10306014 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0xfffe10306018 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0xfffe1030601c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0xfffe10306020 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0xfffe10306024 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0xfffe10306028 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0xfffe1030602c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0xfffe10306030 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0xfffe10306034 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0xfffe1030603c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0xfffe1030603d #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0xfffe1030603e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0xfffe1030603f #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0xfffe10306064 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0xfffe10306066 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0xfffe10306068 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0xfffe1030606c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0xfffe1030606e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0xfffe10306070 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0xfffe10306074 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0xfffe10306076 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0xfffe10306088 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0xfffe1030608c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0xfffe1030608e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0xfffe10306090 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0xfffe10306094 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0xfffe10306096 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0xfffe103060a0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0xfffe103060a2 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0xfffe103060a4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0xfffe103060a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0xfffe103060a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA 0xfffe103060aa #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0xfffe103060ac #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0xfffe103060ac #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_EXT_MSG_DATA_64 0xfffe103060ae #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0xfffe103060b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0xfffe103060b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0xfffe103060b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0xfffe103060c0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0xfffe103060c2 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0xfffe103060c4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0xfffe103060c8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0xfffe10306108 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0xfffe10306154 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0xfffe10306158 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0xfffe10306160 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0xfffe10306164 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0xfffe1030616c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0xfffe10306170 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0xfffe10306174 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0xfffe10306178 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0xfffe10306188 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0xfffe10306190 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0xfffe10306194 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0xfffe1030632c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0xfffe1030632e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp // base address: 0xfffe10307000 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0xfffe10307000 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0xfffe10307002 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0xfffe10307004 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0xfffe10307006 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0xfffe10307008 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0xfffe10307009 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0xfffe1030700a #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0xfffe1030700b #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0xfffe1030700c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0xfffe1030700d #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0xfffe1030700e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0xfffe1030700f #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0xfffe10307010 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0xfffe10307014 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0xfffe10307018 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0xfffe1030701c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0xfffe10307020 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0xfffe10307024 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0xfffe10307028 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0xfffe1030702c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0xfffe10307030 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0xfffe10307034 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0xfffe1030703c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0xfffe1030703d #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0xfffe1030703e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0xfffe1030703f #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0xfffe10307064 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0xfffe10307066 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0xfffe10307068 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0xfffe1030706c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0xfffe1030706e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0xfffe10307070 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0xfffe10307074 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0xfffe10307076 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0xfffe10307088 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0xfffe1030708c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0xfffe1030708e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0xfffe10307090 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0xfffe10307094 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0xfffe10307096 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0xfffe103070a0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0xfffe103070a2 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0xfffe103070a4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0xfffe103070a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0xfffe103070a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA 0xfffe103070aa #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0xfffe103070ac #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0xfffe103070ac #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_EXT_MSG_DATA_64 0xfffe103070ae #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0xfffe103070b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0xfffe103070b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0xfffe103070b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0xfffe103070c0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0xfffe103070c2 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0xfffe103070c4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0xfffe103070c8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0xfffe10307108 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0xfffe10307154 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0xfffe10307158 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0xfffe10307160 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0xfffe10307164 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0xfffe1030716c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0xfffe10307170 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0xfffe10307174 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0xfffe10307178 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0xfffe10307188 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0xfffe10307190 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0xfffe10307194 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0xfffe1030732c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0xfffe1030732e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp // base address: 0xfffe10308000 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0xfffe10308000 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0xfffe10308002 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0xfffe10308004 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0xfffe10308006 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0xfffe10308008 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0xfffe10308009 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0xfffe1030800a #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0xfffe1030800b #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0xfffe1030800c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0xfffe1030800d #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0xfffe1030800e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0xfffe1030800f #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0xfffe10308010 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0xfffe10308014 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0xfffe10308018 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0xfffe1030801c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0xfffe10308020 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0xfffe10308024 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0xfffe10308028 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0xfffe1030802c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0xfffe10308030 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0xfffe10308034 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0xfffe1030803c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0xfffe1030803d #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0xfffe1030803e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0xfffe1030803f #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0xfffe10308064 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0xfffe10308066 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0xfffe10308068 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0xfffe1030806c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0xfffe1030806e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0xfffe10308070 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0xfffe10308074 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0xfffe10308076 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0xfffe10308088 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0xfffe1030808c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0xfffe1030808e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0xfffe10308090 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0xfffe10308094 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0xfffe10308096 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0xfffe103080a0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0xfffe103080a2 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0xfffe103080a4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0xfffe103080a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0xfffe103080a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA 0xfffe103080aa #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0xfffe103080ac #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0xfffe103080ac #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_EXT_MSG_DATA_64 0xfffe103080ae #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0xfffe103080b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0xfffe103080b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0xfffe103080b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0xfffe103080c0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0xfffe103080c2 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0xfffe103080c4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0xfffe103080c8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0xfffe10308108 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0xfffe10308154 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0xfffe10308158 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0xfffe10308160 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0xfffe10308164 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0xfffe1030816c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0xfffe10308170 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0xfffe10308174 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0xfffe10308178 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0xfffe10308188 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0xfffe10308190 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0xfffe10308194 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0xfffe1030832c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0xfffe1030832e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp // base address: 0xfffe10309000 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0xfffe10309000 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0xfffe10309002 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0xfffe10309004 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0xfffe10309006 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0xfffe10309008 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0xfffe10309009 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0xfffe1030900a #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0xfffe1030900b #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0xfffe1030900c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0xfffe1030900d #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0xfffe1030900e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0xfffe1030900f #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0xfffe10309010 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0xfffe10309014 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0xfffe10309018 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0xfffe1030901c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0xfffe10309020 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0xfffe10309024 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0xfffe10309028 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0xfffe1030902c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0xfffe10309030 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0xfffe10309034 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0xfffe1030903c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0xfffe1030903d #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0xfffe1030903e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0xfffe1030903f #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0xfffe10309064 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0xfffe10309066 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0xfffe10309068 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0xfffe1030906c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0xfffe1030906e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0xfffe10309070 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0xfffe10309074 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0xfffe10309076 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0xfffe10309088 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0xfffe1030908c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0xfffe1030908e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0xfffe10309090 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0xfffe10309094 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0xfffe10309096 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0xfffe103090a0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0xfffe103090a2 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0xfffe103090a4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0xfffe103090a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0xfffe103090a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA 0xfffe103090aa #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0xfffe103090ac #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0xfffe103090ac #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_EXT_MSG_DATA_64 0xfffe103090ae #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0xfffe103090b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0xfffe103090b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0xfffe103090b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0xfffe103090c0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0xfffe103090c2 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0xfffe103090c4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0xfffe103090c8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0xfffe10309108 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0xfffe10309154 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0xfffe10309158 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0xfffe10309160 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0xfffe10309164 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0xfffe1030916c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0xfffe10309170 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0xfffe10309174 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0xfffe10309178 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0xfffe10309188 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0xfffe10309190 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0xfffe10309194 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0xfffe1030932c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0xfffe1030932e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp // base address: 0xfffe1030a000 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0xfffe1030a000 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0xfffe1030a002 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0xfffe1030a004 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0xfffe1030a006 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0xfffe1030a008 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0xfffe1030a009 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0xfffe1030a00a #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0xfffe1030a00b #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0xfffe1030a00c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0xfffe1030a00d #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0xfffe1030a00e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0xfffe1030a00f #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0xfffe1030a010 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0xfffe1030a014 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0xfffe1030a018 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0xfffe1030a01c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0xfffe1030a020 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0xfffe1030a024 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0xfffe1030a028 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0xfffe1030a02c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0xfffe1030a030 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0xfffe1030a034 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0xfffe1030a03c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0xfffe1030a03d #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0xfffe1030a03e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0xfffe1030a03f #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0xfffe1030a064 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0xfffe1030a066 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0xfffe1030a068 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0xfffe1030a06c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0xfffe1030a06e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0xfffe1030a070 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0xfffe1030a074 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0xfffe1030a076 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0xfffe1030a088 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0xfffe1030a08c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0xfffe1030a08e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0xfffe1030a090 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0xfffe1030a094 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0xfffe1030a096 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0xfffe1030a0a0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0xfffe1030a0a2 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0xfffe1030a0a4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0xfffe1030a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0xfffe1030a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA 0xfffe1030a0aa #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0xfffe1030a0ac #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0xfffe1030a0ac #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_EXT_MSG_DATA_64 0xfffe1030a0ae #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0xfffe1030a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0xfffe1030a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0xfffe1030a0b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0xfffe1030a0c0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0xfffe1030a0c2 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0xfffe1030a0c4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0xfffe1030a0c8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0xfffe1030a158 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0xfffe1030a160 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0xfffe1030a164 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0xfffe1030a16c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0xfffe1030a170 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0xfffe1030a174 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0xfffe1030a178 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0xfffe1030a32c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0xfffe1030a32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp // base address: 0xfffe1030b000 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0xfffe1030b000 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0xfffe1030b002 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0xfffe1030b004 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0xfffe1030b006 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0xfffe1030b008 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0xfffe1030b009 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0xfffe1030b00a #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0xfffe1030b00b #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0xfffe1030b00c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0xfffe1030b00d #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0xfffe1030b00e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0xfffe1030b00f #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0xfffe1030b010 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0xfffe1030b014 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0xfffe1030b018 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0xfffe1030b01c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0xfffe1030b020 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0xfffe1030b024 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0xfffe1030b028 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0xfffe1030b02c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0xfffe1030b030 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0xfffe1030b034 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0xfffe1030b03c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0xfffe1030b03d #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0xfffe1030b03e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0xfffe1030b03f #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0xfffe1030b064 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0xfffe1030b066 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0xfffe1030b068 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0xfffe1030b06c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0xfffe1030b06e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0xfffe1030b070 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0xfffe1030b074 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0xfffe1030b076 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0xfffe1030b088 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0xfffe1030b08c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0xfffe1030b08e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0xfffe1030b090 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0xfffe1030b094 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0xfffe1030b096 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0xfffe1030b0a0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0xfffe1030b0a2 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0xfffe1030b0a4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0xfffe1030b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0xfffe1030b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA 0xfffe1030b0aa #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0xfffe1030b0ac #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0xfffe1030b0ac #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_EXT_MSG_DATA_64 0xfffe1030b0ae #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0xfffe1030b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0xfffe1030b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0xfffe1030b0b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0xfffe1030b0c0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0xfffe1030b0c2 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0xfffe1030b0c4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0xfffe1030b0c8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0xfffe1030b158 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0xfffe1030b160 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0xfffe1030b164 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0xfffe1030b16c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0xfffe1030b170 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0xfffe1030b174 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0xfffe1030b178 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0xfffe1030b32c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0xfffe1030b32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp // base address: 0xfffe1030c000 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0xfffe1030c000 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0xfffe1030c002 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0xfffe1030c004 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0xfffe1030c006 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0xfffe1030c008 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0xfffe1030c009 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0xfffe1030c00a #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0xfffe1030c00b #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0xfffe1030c00c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0xfffe1030c00d #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0xfffe1030c00e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0xfffe1030c00f #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0xfffe1030c010 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0xfffe1030c014 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0xfffe1030c018 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0xfffe1030c01c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0xfffe1030c020 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0xfffe1030c024 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0xfffe1030c028 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0xfffe1030c02c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0xfffe1030c030 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0xfffe1030c034 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0xfffe1030c03c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0xfffe1030c03d #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0xfffe1030c03e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0xfffe1030c03f #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0xfffe1030c064 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0xfffe1030c066 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0xfffe1030c068 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0xfffe1030c06c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0xfffe1030c06e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0xfffe1030c070 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0xfffe1030c074 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0xfffe1030c076 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0xfffe1030c088 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0xfffe1030c08c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0xfffe1030c08e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0xfffe1030c090 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0xfffe1030c094 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0xfffe1030c096 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0xfffe1030c0a0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0xfffe1030c0a2 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0xfffe1030c0a4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0xfffe1030c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0xfffe1030c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA 0xfffe1030c0aa #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0xfffe1030c0ac #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0xfffe1030c0ac #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_EXT_MSG_DATA_64 0xfffe1030c0ae #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0xfffe1030c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0xfffe1030c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0xfffe1030c0b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0xfffe1030c0c0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0xfffe1030c0c2 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0xfffe1030c0c4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0xfffe1030c0c8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0xfffe1030c158 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0xfffe1030c160 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0xfffe1030c164 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0xfffe1030c16c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0xfffe1030c170 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0xfffe1030c174 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0xfffe1030c178 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0xfffe1030c32c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0xfffe1030c32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp // base address: 0xfffe1030d000 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0xfffe1030d000 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0xfffe1030d002 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0xfffe1030d004 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0xfffe1030d006 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0xfffe1030d008 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0xfffe1030d009 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0xfffe1030d00a #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0xfffe1030d00b #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0xfffe1030d00c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0xfffe1030d00d #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0xfffe1030d00e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0xfffe1030d00f #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0xfffe1030d010 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0xfffe1030d014 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0xfffe1030d018 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0xfffe1030d01c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0xfffe1030d020 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0xfffe1030d024 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0xfffe1030d028 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0xfffe1030d02c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0xfffe1030d030 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0xfffe1030d034 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0xfffe1030d03c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0xfffe1030d03d #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0xfffe1030d03e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0xfffe1030d03f #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0xfffe1030d064 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0xfffe1030d066 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0xfffe1030d068 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0xfffe1030d06c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0xfffe1030d06e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0xfffe1030d070 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0xfffe1030d074 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0xfffe1030d076 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0xfffe1030d088 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0xfffe1030d08c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0xfffe1030d08e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0xfffe1030d090 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0xfffe1030d094 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0xfffe1030d096 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0xfffe1030d0a0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0xfffe1030d0a2 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0xfffe1030d0a4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0xfffe1030d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0xfffe1030d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA 0xfffe1030d0aa #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0xfffe1030d0ac #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0xfffe1030d0ac #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_EXT_MSG_DATA_64 0xfffe1030d0ae #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0xfffe1030d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0xfffe1030d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0xfffe1030d0b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0xfffe1030d0c0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0xfffe1030d0c2 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0xfffe1030d0c4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0xfffe1030d0c8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0xfffe1030d158 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0xfffe1030d160 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0xfffe1030d164 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0xfffe1030d16c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0xfffe1030d170 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0xfffe1030d174 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0xfffe1030d178 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0xfffe1030d32c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0xfffe1030d32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp // base address: 0xfffe1030e000 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0xfffe1030e000 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0xfffe1030e002 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0xfffe1030e004 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0xfffe1030e006 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0xfffe1030e008 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0xfffe1030e009 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0xfffe1030e00a #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0xfffe1030e00b #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0xfffe1030e00c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0xfffe1030e00d #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0xfffe1030e00e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0xfffe1030e00f #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0xfffe1030e010 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0xfffe1030e014 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0xfffe1030e018 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0xfffe1030e01c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0xfffe1030e020 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0xfffe1030e024 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0xfffe1030e028 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0xfffe1030e02c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0xfffe1030e030 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0xfffe1030e034 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0xfffe1030e03c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0xfffe1030e03d #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0xfffe1030e03e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0xfffe1030e03f #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0xfffe1030e064 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0xfffe1030e066 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0xfffe1030e068 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0xfffe1030e06c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0xfffe1030e06e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0xfffe1030e070 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0xfffe1030e074 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0xfffe1030e076 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0xfffe1030e088 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0xfffe1030e08c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0xfffe1030e08e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0xfffe1030e090 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0xfffe1030e094 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0xfffe1030e096 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0xfffe1030e0a0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0xfffe1030e0a2 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0xfffe1030e0a4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0xfffe1030e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0xfffe1030e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA 0xfffe1030e0aa #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0xfffe1030e0ac #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0xfffe1030e0ac #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_EXT_MSG_DATA_64 0xfffe1030e0ae #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0xfffe1030e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0xfffe1030e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0xfffe1030e0b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0xfffe1030e0c0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0xfffe1030e0c2 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0xfffe1030e0c4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0xfffe1030e0c8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0xfffe1030e158 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0xfffe1030e160 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0xfffe1030e164 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0xfffe1030e16c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0xfffe1030e170 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0xfffe1030e174 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0xfffe1030e178 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0xfffe1030e32c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0xfffe1030e32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp // base address: 0xfffe1030f000 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0xfffe1030f000 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0xfffe1030f002 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0xfffe1030f004 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0xfffe1030f006 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0xfffe1030f008 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0xfffe1030f009 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0xfffe1030f00a #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0xfffe1030f00b #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0xfffe1030f00c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0xfffe1030f00d #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0xfffe1030f00e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0xfffe1030f00f #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0xfffe1030f010 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0xfffe1030f014 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0xfffe1030f018 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0xfffe1030f01c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0xfffe1030f020 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0xfffe1030f024 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0xfffe1030f028 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0xfffe1030f02c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0xfffe1030f030 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0xfffe1030f034 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0xfffe1030f03c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0xfffe1030f03d #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0xfffe1030f03e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0xfffe1030f03f #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0xfffe1030f064 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0xfffe1030f066 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0xfffe1030f068 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0xfffe1030f06c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0xfffe1030f06e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0xfffe1030f070 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0xfffe1030f074 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0xfffe1030f076 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0xfffe1030f088 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0xfffe1030f08c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0xfffe1030f08e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0xfffe1030f090 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0xfffe1030f094 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0xfffe1030f096 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0xfffe1030f0a0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0xfffe1030f0a2 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0xfffe1030f0a4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0xfffe1030f0a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0xfffe1030f0a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA 0xfffe1030f0aa #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0xfffe1030f0ac #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0xfffe1030f0ac #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_EXT_MSG_DATA_64 0xfffe1030f0ae #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0xfffe1030f0b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0xfffe1030f0b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0xfffe1030f0b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0xfffe1030f0c0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0xfffe1030f0c2 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0xfffe1030f0c4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0xfffe1030f0c8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0xfffe1030f158 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0xfffe1030f160 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0xfffe1030f164 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0xfffe1030f16c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0xfffe1030f170 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0xfffe1030f174 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0xfffe1030f178 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0xfffe1030f32c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0xfffe1030f32e // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0003864 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0003868 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0 #define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC // base address: 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0xd0000000 #define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694 #define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790 #define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 // base address: 0xd0000000 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0083864 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0083868 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0 #define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC // base address: 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0xd0080000 #define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694 #define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790 #define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 // base address: 0xd0080000 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0103864 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0103868 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0 #define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC // base address: 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0xd0100000 #define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694 #define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790 #define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 // base address: 0xd0100000 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0183864 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0183868 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0 #define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC // base address: 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0xd0180000 #define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694 #define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790 #define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 // base address: 0xd0180000 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0203864 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0203868 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0 #define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC // base address: 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0xd0200000 #define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694 #define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790 #define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 // base address: 0xd0200000 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0283864 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0283868 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0 #define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC // base address: 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0xd0280000 #define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694 #define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790 #define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 // base address: 0xd0280000 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0303864 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0303868 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0 #define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC // base address: 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0xd0300000 #define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694 #define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790 #define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 // base address: 0xd0300000 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0383864 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0383868 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0 #define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC // base address: 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0xd0380000 #define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694 #define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790 #define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 // base address: 0xd0380000 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0403864 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0403868 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0 #define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC // base address: 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0xd0400000 #define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694 #define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790 #define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 // base address: 0xd0400000 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0483864 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0483868 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0 #define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC // base address: 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0xd0480000 #define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694 #define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790 #define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 // base address: 0xd0480000 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0503864 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0503868 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0 #define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC // base address: 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0xd0500000 #define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694 #define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790 #define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 // base address: 0xd0500000 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0583864 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0583868 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0 #define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC // base address: 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0xd0580000 #define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694 #define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790 #define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 // base address: 0xd0580000 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0603864 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0603868 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0 #define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC // base address: 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0xd0600000 #define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694 #define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790 #define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 // base address: 0xd0600000 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0683864 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0683868 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0 #define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC // base address: 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0xd0680000 #define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694 #define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790 #define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 // base address: 0xd0680000 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0703864 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0703868 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0 #define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC // base address: 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0xd0700000 #define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694 #define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790 #define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 // base address: 0xd0700000 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0xd0783864 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0xd0783868 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0 #define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC // base address: 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0xd0780000 #define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694 #define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790 #define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 // base address: 0xd0780000 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000 // addressBlock: nbio_pcie0_pswusp0_pciedir_p // base address: 0x1a340000 #define regPCIEP_RESERVED 0x2890000 #define regPCIEP_RESERVED_BASE_IDX 5 #define regPCIEP_SCRATCH 0x2890001 #define regPCIEP_SCRATCH_BASE_IDX 5 #define regPCIEP_PORT_CNTL 0x2890010 #define regPCIEP_PORT_CNTL_BASE_IDX 5 #define regPCIE_TX_REQUESTER_ID 0x2890021 #define regPCIE_TX_REQUESTER_ID_BASE_IDX 5 #define regPCIE_P_PORT_LANE_STATUS 0x2890050 #define regPCIE_P_PORT_LANE_STATUS_BASE_IDX 5 #define regPSWUSP0_PCIE_ERR_CNTL 0x289006a #define regPSWUSP0_PCIE_ERR_CNTL_BASE_IDX 5 #define regPSWUSP0_PCIE_RX_CNTL 0x2890070 #define regPSWUSP0_PCIE_RX_CNTL_BASE_IDX 5 #define regPCIE_RX_EXPECTED_SEQNUM 0x2890071 #define regPCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 #define regPCIE_RX_VENDOR_SPECIFIC 0x2890072 #define regPCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 #define regPCIE_RX_CNTL3 0x2890074 #define regPCIE_RX_CNTL3_BASE_IDX 5 #define regPCIE_RX_CREDITS_ALLOCATED_P 0x2890080 #define regPCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 #define regPCIE_RX_CREDITS_ALLOCATED_NP 0x2890081 #define regPCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 #define regPCIE_RX_CREDITS_ALLOCATED_CPL 0x2890082 #define regPCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 #define regPCIEP_ERROR_INJECT_PHYSICAL 0x2890083 #define regPCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 #define regPCIEP_ERROR_INJECT_TRANSACTION 0x2890084 #define regPCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 #define regPCIEP_NAK_COUNTER 0x2890086 #define regPCIEP_NAK_COUNTER_BASE_IDX 5 #define regPCIE_LC_CNTL 0x28900a0 #define regPCIE_LC_CNTL_BASE_IDX 5 #define regPCIE_LC_TRAINING_CNTL 0x28900a1 #define regPCIE_LC_TRAINING_CNTL_BASE_IDX 5 #define regPCIE_LC_LINK_WIDTH_CNTL 0x28900a2 #define regPCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 #define regPCIE_LC_N_FTS_CNTL 0x28900a3 #define regPCIE_LC_N_FTS_CNTL_BASE_IDX 5 #define regPSWUSP0_PCIE_LC_SPEED_CNTL 0x28900a4 #define regPSWUSP0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 #define regPCIE_LC_STATE0 0x28900a5 #define regPCIE_LC_STATE0_BASE_IDX 5 #define regPCIE_LC_STATE1 0x28900a6 #define regPCIE_LC_STATE1_BASE_IDX 5 #define regPCIE_LC_STATE2 0x28900a7 #define regPCIE_LC_STATE2_BASE_IDX 5 #define regPCIE_LC_STATE3 0x28900a8 #define regPCIE_LC_STATE3_BASE_IDX 5 #define regPCIE_LC_STATE4 0x28900a9 #define regPCIE_LC_STATE4_BASE_IDX 5 #define regPCIE_LC_STATE5 0x28900aa #define regPCIE_LC_STATE5_BASE_IDX 5 #define regPSWUSP0_PCIE_LC_CNTL2 0x28900b1 #define regPSWUSP0_PCIE_LC_CNTL2_BASE_IDX 5 #define regPCIE_LC_BW_CHANGE_CNTL 0x28900b2 #define regPCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 #define regPCIE_LC_CDR_CNTL 0x28900b3 #define regPCIE_LC_CDR_CNTL_BASE_IDX 5 #define regPCIE_LC_LANE_CNTL 0x28900b4 #define regPCIE_LC_LANE_CNTL_BASE_IDX 5 #define regPCIE_LC_CNTL3 0x28900b5 #define regPCIE_LC_CNTL3_BASE_IDX 5 #define regPCIE_LC_CNTL4 0x28900b6 #define regPCIE_LC_CNTL4_BASE_IDX 5 #define regPCIE_LC_CNTL5 0x28900b7 #define regPCIE_LC_CNTL5_BASE_IDX 5 #define regPCIE_LC_FORCE_COEFF 0x28900b8 #define regPCIE_LC_FORCE_COEFF_BASE_IDX 5 #define regPCIE_LC_BEST_EQ_SETTINGS 0x28900b9 #define regPCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 #define regPCIE_LC_FORCE_EQ_REQ_COEFF 0x28900ba #define regPCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 #define regPCIE_LC_CNTL6 0x28900bb #define regPCIE_LC_CNTL6_BASE_IDX 5 #define regPCIE_LC_CNTL7 0x28900bc #define regPCIE_LC_CNTL7_BASE_IDX 5 #define regPCIEP_STRAP_LC 0x28900c0 #define regPCIEP_STRAP_LC_BASE_IDX 5 #define regPSWUSP0_PCIEP_STRAP_MISC 0x28900c1 #define regPSWUSP0_PCIEP_STRAP_MISC_BASE_IDX 5 #define regPCIEP_STRAP_LC2 0x28900c2 #define regPCIEP_STRAP_LC2_BASE_IDX 5 #define regPCIE_LC_L1_PM_SUBSTATE 0x28900c6 #define regPCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 #define regPCIE_LC_L1_PM_SUBSTATE2 0x28900c7 #define regPCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 #define regPCIE_LC_L1_PM_SUBSTATE3 0x28900c8 #define regPCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 #define regPCIE_LC_L1_PM_SUBSTATE4 0x28900c9 #define regPCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 #define regPCIE_LC_L1_PM_SUBSTATE5 0x28900ca #define regPCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 #define regPCIEP_BCH_ECC_CNTL 0x28900d0 #define regPCIEP_BCH_ECC_CNTL_BASE_IDX 5 #define regPCIE_LC_CNTL8 0x28900dd #define regPCIE_LC_CNTL8_BASE_IDX 5 #define regPCIE_LC_CNTL9 0x28900de #define regPCIE_LC_CNTL9_BASE_IDX 5 #define regPCIE_LC_FORCE_COEFF2 0x28900df #define regPCIE_LC_FORCE_COEFF2_BASE_IDX 5 #define regPCIE_LC_FORCE_EQ_REQ_COEFF2 0x28900e0 #define regPCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 #define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x28900e2 #define regPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 #define regPCIE_LC_CNTL10 0x28900e3 #define regPCIE_LC_CNTL10_BASE_IDX 5 #define regPCIE_LC_SAVE_RESTORE_1 0x28900e6 #define regPCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 #define regPCIE_LC_SAVE_RESTORE_2 0x28900e7 #define regPCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 #define regPCIE_LC_CNTL11 0x2890103 #define regPCIE_LC_CNTL11_BASE_IDX 5 #define regPCIE_LC_CNTL12 0x2890104 #define regPCIE_LC_CNTL12_BASE_IDX 5 #define regPCIE_LC_SPEED_CNTL2 0x2890105 #define regPCIE_LC_SPEED_CNTL2_BASE_IDX 5 #define regPCIE_LC_FORCE_COEFF3 0x2890106 #define regPCIE_LC_FORCE_COEFF3_BASE_IDX 5 #define regPCIE_LC_FORCE_EQ_REQ_COEFF3 0x2890107 #define regPCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 #define regPCIE_TX_SEQ 0x2890188 #define regPCIE_TX_SEQ_BASE_IDX 5 #define regPCIE_TX_REPLAY 0x2890189 #define regPCIE_TX_REPLAY_BASE_IDX 5 #define regPCIE_TX_ACK_LATENCY_LIMIT 0x289018c #define regPCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 #define regPCIE_TX_CREDITS_FCU_THRESHOLD 0x2890190 #define regPCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 #define regPCIE_TX_VENDOR_SPECIFIC 0x2890194 #define regPCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 #define regPCIE_TX_NOP_DLLP 0x2890195 #define regPCIE_TX_NOP_DLLP_BASE_IDX 5 #define regPCIE_TX_REQUEST_NUM_CNTL 0x2890198 #define regPCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 #define regPCIE_TX_CREDITS_ADVT_P 0x28901a0 #define regPCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 #define regPCIE_TX_CREDITS_ADVT_NP 0x28901a1 #define regPCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 #define regPCIE_TX_CREDITS_ADVT_CPL 0x28901a2 #define regPCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 #define regPCIE_TX_CREDITS_INIT_P 0x28901a3 #define regPCIE_TX_CREDITS_INIT_P_BASE_IDX 5 #define regPCIE_TX_CREDITS_INIT_NP 0x28901a4 #define regPCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 #define regPCIE_TX_CREDITS_INIT_CPL 0x28901a5 #define regPCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 #define regPCIE_TX_CREDITS_STATUS 0x28901a6 #define regPCIE_TX_CREDITS_STATUS_BASE_IDX 5 #define regPCIE_FC_P 0x28901a8 #define regPCIE_FC_P_BASE_IDX 5 #define regPCIE_FC_NP 0x28901a9 #define regPCIE_FC_NP_BASE_IDX 5 #define regPCIE_FC_CPL 0x28901aa #define regPCIE_FC_CPL_BASE_IDX 5 #define regPCIE_FC_P_VC1 0x28901ab #define regPCIE_FC_P_VC1_BASE_IDX 5 #define regPCIE_FC_NP_VC1 0x28901ac #define regPCIE_FC_NP_VC1_BASE_IDX 5 #define regPCIE_FC_CPL_VC1 0x28901ad #define regPCIE_FC_CPL_VC1_BASE_IDX 5 // addressBlock: nbio_pcie0_pciedir // base address: 0x1a380000 #define regPCIE_RESERVED 0x28a0000 #define regPCIE_RESERVED_BASE_IDX 5 #define regPCIE_SCRATCH 0x28a0001 #define regPCIE_SCRATCH_BASE_IDX 5 #define regPCIE_RX_NUM_NAK 0x28a000e #define regPCIE_RX_NUM_NAK_BASE_IDX 5 #define regPCIE_RX_NUM_NAK_GENERATED 0x28a000f #define regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX 5 #define regPCIE_CNTL 0x28a0010 #define regPCIE_CNTL_BASE_IDX 5 #define regPCIE_CONFIG_CNTL 0x28a0011 #define regPCIE_CONFIG_CNTL_BASE_IDX 5 #define regPCIE_RX_CNTL5 0x28a0018 #define regPCIE_RX_CNTL5_BASE_IDX 5 #define regPCIE_RX_CNTL4 0x28a0019 #define regPCIE_RX_CNTL4_BASE_IDX 5 #define regPCIE_COMMON_AER_MASK 0x28a001a #define regPCIE_COMMON_AER_MASK_BASE_IDX 5 #define regPCIE_CNTL2 0x28a001c #define regPCIE_CNTL2_BASE_IDX 5 #define regPCIE_RX_CNTL2 0x28a001d #define regPCIE_RX_CNTL2_BASE_IDX 5 #define regPCIE_CI_CNTL 0x28a0020 #define regPCIE_CI_CNTL_BASE_IDX 5 #define regPCIE_BUS_CNTL 0x28a0021 #define regPCIE_BUS_CNTL_BASE_IDX 5 #define regPCIE_LC_STATE6 0x28a0022 #define regPCIE_LC_STATE6_BASE_IDX 5 #define regPCIE_LC_STATE7 0x28a0023 #define regPCIE_LC_STATE7_BASE_IDX 5 #define regPCIE_LC_STATE8 0x28a0024 #define regPCIE_LC_STATE8_BASE_IDX 5 #define regPCIE_LC_STATE9 0x28a0025 #define regPCIE_LC_STATE9_BASE_IDX 5 #define regPCIE_LC_STATE10 0x28a0026 #define regPCIE_LC_STATE10_BASE_IDX 5 #define regPCIE_LC_STATE11 0x28a0027 #define regPCIE_LC_STATE11_BASE_IDX 5 #define regPCIE_LC_STATUS1 0x28a0028 #define regPCIE_LC_STATUS1_BASE_IDX 5 #define regPCIE_LC_STATUS2 0x28a0029 #define regPCIE_LC_STATUS2_BASE_IDX 5 #define regPCIE_WPR_CNTL 0x28a0030 #define regPCIE_WPR_CNTL_BASE_IDX 5 #define regPCIE_RX_LAST_TLP0 0x28a0031 #define regPCIE_RX_LAST_TLP0_BASE_IDX 5 #define regPCIE_RX_LAST_TLP1 0x28a0032 #define regPCIE_RX_LAST_TLP1_BASE_IDX 5 #define regPCIE_RX_LAST_TLP2 0x28a0033 #define regPCIE_RX_LAST_TLP2_BASE_IDX 5 #define regPCIE_RX_LAST_TLP3 0x28a0034 #define regPCIE_RX_LAST_TLP3_BASE_IDX 5 #define regPCIE_I2C_REG_ADDR_EXPAND 0x28a003a #define regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX 5 #define regPCIE_I2C_REG_DATA 0x28a003b #define regPCIE_I2C_REG_DATA_BASE_IDX 5 #define regPCIE_CFG_CNTL 0x28a003c #define regPCIE_CFG_CNTL_BASE_IDX 5 #define regPCIE_LC_PM_CNTL 0x28a003d #define regPCIE_LC_PM_CNTL_BASE_IDX 5 #define regPCIE_LC_PM_CNTL2 0x28a003e #define regPCIE_LC_PM_CNTL2_BASE_IDX 5 #define regPCIE_P_CNTL 0x28a0040 #define regPCIE_P_CNTL_BASE_IDX 5 #define regPCIE_P_BUF_STATUS 0x28a0041 #define regPCIE_P_BUF_STATUS_BASE_IDX 5 #define regPCIE_P_DECODER_STATUS 0x28a0042 #define regPCIE_P_DECODER_STATUS_BASE_IDX 5 #define regPCIE_P_MISC_STATUS 0x28a0043 #define regPCIE_P_MISC_STATUS_BASE_IDX 5 #define regPCIE_P_RCV_L0S_FTS_DET 0x28a0050 #define regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX 5 #define regPCIE_RX_AD 0x28a0062 #define regPCIE_RX_AD_BASE_IDX 5 #define regPCIE_SDP_CTRL 0x28a0063 #define regPCIE_SDP_CTRL_BASE_IDX 5 #define regPCIE_SDP_SWUS_SLV_ATTR_CTRL 0x28a0065 #define regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX 5 #define regPCIE_SDP_CTRL2 0x28a0068 #define regPCIE_SDP_CTRL2_BASE_IDX 5 #define regPCIE_PERF_COUNT_CNTL 0x28a0080 #define regPCIE_PERF_COUNT_CNTL_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK1 0x28a0081 #define regPCIE_PERF_CNTL_TXCLK1_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK1 0x28a0082 #define regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK1 0x28a0083 #define regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK2 0x28a0084 #define regPCIE_PERF_CNTL_TXCLK2_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK2 0x28a0085 #define regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK2 0x28a0086 #define regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK3 0x28a0087 #define regPCIE_PERF_CNTL_TXCLK3_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK3 0x28a0088 #define regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK3 0x28a0089 #define regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK4 0x28a008a #define regPCIE_PERF_CNTL_TXCLK4_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK4 0x28a008b #define regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK4 0x28a008c #define regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX 5 #define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x28a0093 #define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX 5 #define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x28a0094 #define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK5 0x28a0096 #define regPCIE_PERF_CNTL_TXCLK5_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK5 0x28a0097 #define regPCIE_PERF_COUNT0_TXCLK5_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK5 0x28a0098 #define regPCIE_PERF_COUNT1_TXCLK5_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK6 0x28a0099 #define regPCIE_PERF_CNTL_TXCLK6_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK6 0x28a009a #define regPCIE_PERF_COUNT0_TXCLK6_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK6 0x28a009b #define regPCIE_PERF_COUNT1_TXCLK6_BASE_IDX 5 #define regPCIE_STRAP_F0 0x28a00b0 #define regPCIE_STRAP_F0_BASE_IDX 5 #define regPCIE_STRAP_MISC 0x28a00c0 #define regPCIE_STRAP_MISC_BASE_IDX 5 #define regPCIE_STRAP_MISC2 0x28a00c1 #define regPCIE_STRAP_MISC2_BASE_IDX 5 #define regPCIE_STRAP_PI 0x28a00c2 #define regPCIE_STRAP_PI_BASE_IDX 5 #define regPCIE_STRAP_I2C_BD 0x28a00c4 #define regPCIE_STRAP_I2C_BD_BASE_IDX 5 #define regPCIE_PRBS_CLR 0x28a00c8 #define regPCIE_PRBS_CLR_BASE_IDX 5 #define regPCIE_PRBS_STATUS1 0x28a00c9 #define regPCIE_PRBS_STATUS1_BASE_IDX 5 #define regPCIE_PRBS_STATUS2 0x28a00ca #define regPCIE_PRBS_STATUS2_BASE_IDX 5 #define regPCIE_PRBS_FREERUN 0x28a00cb #define regPCIE_PRBS_FREERUN_BASE_IDX 5 #define regPCIE_PRBS_MISC 0x28a00cc #define regPCIE_PRBS_MISC_BASE_IDX 5 #define regPCIE_PRBS_USER_PATTERN 0x28a00cd #define regPCIE_PRBS_USER_PATTERN_BASE_IDX 5 #define regPCIE_PRBS_LO_BITCNT 0x28a00ce #define regPCIE_PRBS_LO_BITCNT_BASE_IDX 5 #define regPCIE_PRBS_HI_BITCNT 0x28a00cf #define regPCIE_PRBS_HI_BITCNT_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_0 0x28a00d0 #define regPCIE_PRBS_ERRCNT_0_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_1 0x28a00d1 #define regPCIE_PRBS_ERRCNT_1_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_2 0x28a00d2 #define regPCIE_PRBS_ERRCNT_2_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_3 0x28a00d3 #define regPCIE_PRBS_ERRCNT_3_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_4 0x28a00d4 #define regPCIE_PRBS_ERRCNT_4_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_5 0x28a00d5 #define regPCIE_PRBS_ERRCNT_5_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_6 0x28a00d6 #define regPCIE_PRBS_ERRCNT_6_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_7 0x28a00d7 #define regPCIE_PRBS_ERRCNT_7_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_8 0x28a00d8 #define regPCIE_PRBS_ERRCNT_8_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_9 0x28a00d9 #define regPCIE_PRBS_ERRCNT_9_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_10 0x28a00da #define regPCIE_PRBS_ERRCNT_10_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_11 0x28a00db #define regPCIE_PRBS_ERRCNT_11_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_12 0x28a00dc #define regPCIE_PRBS_ERRCNT_12_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_13 0x28a00dd #define regPCIE_PRBS_ERRCNT_13_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_14 0x28a00de #define regPCIE_PRBS_ERRCNT_14_BASE_IDX 5 #define regPCIE_PRBS_ERRCNT_15 0x28a00df #define regPCIE_PRBS_ERRCNT_15_BASE_IDX 5 #define regSWRST_COMMAND_STATUS 0x28a0100 #define regSWRST_COMMAND_STATUS_BASE_IDX 5 #define regSWRST_GENERAL_CONTROL 0x28a0101 #define regSWRST_GENERAL_CONTROL_BASE_IDX 5 #define regSWRST_COMMAND_0 0x28a0102 #define regSWRST_COMMAND_0_BASE_IDX 5 #define regSWRST_COMMAND_1 0x28a0103 #define regSWRST_COMMAND_1_BASE_IDX 5 #define regSWRST_CONTROL_0 0x28a0104 #define regSWRST_CONTROL_0_BASE_IDX 5 #define regSWRST_CONTROL_1 0x28a0105 #define regSWRST_CONTROL_1_BASE_IDX 5 #define regSWRST_CONTROL_2 0x28a0106 #define regSWRST_CONTROL_2_BASE_IDX 5 #define regSWRST_CONTROL_3 0x28a0107 #define regSWRST_CONTROL_3_BASE_IDX 5 #define regSWRST_CONTROL_4 0x28a0108 #define regSWRST_CONTROL_4_BASE_IDX 5 #define regSWRST_CONTROL_5 0x28a0109 #define regSWRST_CONTROL_5_BASE_IDX 5 #define regSWRST_CONTROL_6 0x28a010a #define regSWRST_CONTROL_6_BASE_IDX 5 #define regSWRST_EP_COMMAND_0 0x28a010b #define regSWRST_EP_COMMAND_0_BASE_IDX 5 #define regSWRST_EP_CONTROL_0 0x28a010c #define regSWRST_EP_CONTROL_0_BASE_IDX 5 #define regCPM_CONTROL 0x28a0118 #define regCPM_CONTROL_BASE_IDX 5 #define regCPM_SPLIT_CONTROL 0x28a0119 #define regCPM_SPLIT_CONTROL_BASE_IDX 5 #define regCPM_CONTROL_EXT 0x28a011a #define regCPM_CONTROL_EXT_BASE_IDX 5 #define regSMN_APERTURE_ID_A 0x28a011d #define regSMN_APERTURE_ID_A_BASE_IDX 5 #define regSMN_APERTURE_ID_B 0x28a011e #define regSMN_APERTURE_ID_B_BASE_IDX 5 #define regLNCNT_CONTROL 0x28a0125 #define regLNCNT_CONTROL_BASE_IDX 5 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR 0x28a012f #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX 5 #define regPCIE_PGMST_CNTL 0x28a0130 #define regPCIE_PGMST_CNTL_BASE_IDX 5 #define regPCIE_PGSLV_CNTL 0x28a0131 #define regPCIE_PGSLV_CNTL_BASE_IDX 5 #define regLC_CPM_CONTROL_0 0x28a0133 #define regLC_CPM_CONTROL_0_BASE_IDX 5 #define regLC_CPM_CONTROL_1 0x28a0134 #define regLC_CPM_CONTROL_1_BASE_IDX 5 #define regPCIE_RXMARGIN_CONTROL_CAPABILITIES 0x28a0135 #define regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX 5 #define regPCIE_RXMARGIN_1_SETTINGS 0x28a0136 #define regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX 5 #define regPCIE_RXMARGIN_2_SETTINGS 0x28a0137 #define regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX 5 #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO 0x28a013a #define regSMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX 5 #define regPCIE_TX_LAST_TLP0 0x28a0180 #define regPCIE_TX_LAST_TLP0_BASE_IDX 5 #define regPCIE_TX_LAST_TLP1 0x28a0181 #define regPCIE_TX_LAST_TLP1_BASE_IDX 5 #define regPCIE_TX_LAST_TLP2 0x28a0182 #define regPCIE_TX_LAST_TLP2_BASE_IDX 5 #define regPCIE_TX_LAST_TLP3 0x28a0183 #define regPCIE_TX_LAST_TLP3_BASE_IDX 5 #define regPCIE_TX_TRACKING_ADDR_LO 0x28a0184 #define regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX 5 #define regPCIE_TX_TRACKING_ADDR_HI 0x28a0185 #define regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5 #define regPCIE_TX_TRACKING_CTRL_STATUS 0x28a0186 #define regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5 #define regPCIE_TX_CTRL_4 0x28a018b #define regPCIE_TX_CTRL_4_BASE_IDX 5 #define regPCIE_TX_STATUS 0x28a0194 #define regPCIE_TX_STATUS_BASE_IDX 5 #define regPCIE_TX_F0_ATTR_CNTL 0x28a019c #define regPCIE_TX_F0_ATTR_CNTL_BASE_IDX 5 #define regPCIE_TX_SWUS_ATTR_CNTL 0x28a019d #define regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX 5 #define regPCIE_MST_CTRL_1 0x28a01c4 #define regPCIE_MST_CTRL_1_BASE_IDX 5 #define regPCIE_HIP_REG0 0x28a01e0 #define regPCIE_HIP_REG0_BASE_IDX 5 #define regPCIE_HIP_REG1 0x28a01e1 #define regPCIE_HIP_REG1_BASE_IDX 5 #define regPCIE_HIP_REG2 0x28a01e2 #define regPCIE_HIP_REG2_BASE_IDX 5 #define regPCIE_HIP_REG3 0x28a01e3 #define regPCIE_HIP_REG3_BASE_IDX 5 #define regPCIE_HIP_REG4 0x28a01e4 #define regPCIE_HIP_REG4_BASE_IDX 5 #define regPCIE_HIP_REG5 0x28a01e5 #define regPCIE_HIP_REG5_BASE_IDX 5 #define regPCIE_HIP_REG6 0x28a01e6 #define regPCIE_HIP_REG6_BASE_IDX 5 #define regPCIE_HIP_REG7 0x28a01e7 #define regPCIE_HIP_REG7_BASE_IDX 5 #define regPCIE_HIP_REG8 0x28a01e8 #define regPCIE_HIP_REG8_BASE_IDX 5 #define regSMU_PCIE_FENCED1_REG 0x28a0200 #define regSMU_PCIE_FENCED1_REG_BASE_IDX 5 #define regSMU_PCIE_FENCED2_REG 0x28a0201 #define regSMU_PCIE_FENCED2_REG_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK7 0x28a0222 #define regPCIE_PERF_CNTL_TXCLK7_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK7 0x28a0223 #define regPCIE_PERF_COUNT0_TXCLK7_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK7 0x28a0224 #define regPCIE_PERF_COUNT1_TXCLK7_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK8 0x28a0225 #define regPCIE_PERF_CNTL_TXCLK8_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK8 0x28a0226 #define regPCIE_PERF_COUNT0_TXCLK8_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK8 0x28a0227 #define regPCIE_PERF_COUNT1_TXCLK8_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK9 0x28a0228 #define regPCIE_PERF_CNTL_TXCLK9_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK9 0x28a0229 #define regPCIE_PERF_COUNT0_TXCLK9_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK9 0x28a022a #define regPCIE_PERF_COUNT1_TXCLK9_BASE_IDX 5 #define regPCIE_PERF_CNTL_TXCLK10 0x28a022b #define regPCIE_PERF_CNTL_TXCLK10_BASE_IDX 5 #define regPCIE_PERF_COUNT0_TXCLK10 0x28a022c #define regPCIE_PERF_COUNT0_TXCLK10_BASE_IDX 5 #define regPCIE_PERF_COUNT1_TXCLK10 0x28a022d #define regPCIE_PERF_COUNT1_TXCLK10_BASE_IDX 5 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp // base address: 0x1a300000 #define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x2880006 #define regPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 #define regPSWUSCFG0_IO_BASE_LIMIT 0x2880007 #define regPSWUSCFG0_IO_BASE_LIMIT_BASE_IDX 5 #define regPSWUSCFG0_SECONDARY_STATUS 0x2880007 #define regPSWUSCFG0_SECONDARY_STATUS_BASE_IDX 5 #define regPSWUSCFG0_MEM_BASE_LIMIT 0x2880008 #define regPSWUSCFG0_MEM_BASE_LIMIT_BASE_IDX 5 #define regPSWUSCFG0_PREF_BASE_LIMIT 0x2880009 #define regPSWUSCFG0_PREF_BASE_LIMIT_BASE_IDX 5 #define regPSWUSCFG0_PREF_BASE_UPPER 0x288000a #define regPSWUSCFG0_PREF_BASE_UPPER_BASE_IDX 5 #define regPSWUSCFG0_PREF_LIMIT_UPPER 0x288000b #define regPSWUSCFG0_PREF_LIMIT_UPPER_BASE_IDX 5 #define regPSWUSCFG0_IO_BASE_LIMIT_HI 0x288000c #define regPSWUSCFG0_IO_BASE_LIMIT_HI_BASE_IDX 5 #define regPSWUSCFG0_SSID_CAP_LIST 0x2880030 #define regPSWUSCFG0_SSID_CAP_LIST_BASE_IDX 5 #define regPSWUSCFG0_SSID_CAP 0x2880031 #define regPSWUSCFG0_SSID_CAP_BASE_IDX 5 #define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL 0x2890102 #define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp // base address: 0x10100000 #define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0006 #define regBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x0007 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x0007 #define regBIF_CFG_DEV0_RC_SECONDARY_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0008 #define regBIF_CFG_DEV0_RC_MEM_BASE_LIMIT_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0009 #define regBIF_CFG_DEV0_RC_PREF_BASE_LIMIT_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x000a #define regBIF_CFG_DEV0_RC_PREF_BASE_UPPER_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x000b #define regBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x000c #define regBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI_BASE_IDX 5 #define regSLOT_CAP 0x001b #define regSLOT_CAP_BASE_IDX 5 #define regSLOT_CNTL 0x001c #define regSLOT_CNTL_BASE_IDX 5 #define regSLOT_STATUS 0x001c #define regSLOT_STATUS_BASE_IDX 5 #define regSLOT_CAP2 0x0023 #define regSLOT_CAP2_BASE_IDX 5 #define regSLOT_CNTL2 0x0024 #define regSLOT_CNTL2_BASE_IDX 5 #define regSLOT_STATUS2 0x0024 #define regSLOT_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x0030 #define regBIF_CFG_DEV0_RC_SSID_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_RC_SSID_CAP 0x0031 #define regBIF_CFG_DEV0_RC_SSID_CAP_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp // base address: 0x10140000 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID 0x10000 #define regBIF_CFG_DEV0_EPF0_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID 0x10000 #define regBIF_CFG_DEV0_EPF0_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_COMMAND 0x10001 #define regBIF_CFG_DEV0_EPF0_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_STATUS 0x10001 #define regBIF_CFG_DEV0_EPF0_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_REVISION_ID 0x10002 #define regBIF_CFG_DEV0_EPF0_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x10002 #define regBIF_CFG_DEV0_EPF0_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS 0x10002 #define regBIF_CFG_DEV0_EPF0_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS 0x10002 #define regBIF_CFG_DEV0_EPF0_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE 0x10003 #define regBIF_CFG_DEV0_EPF0_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LATENCY 0x10003 #define regBIF_CFG_DEV0_EPF0_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_HEADER 0x10003 #define regBIF_CFG_DEV0_EPF0_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BIST 0x10003 #define regBIF_CFG_DEV0_EPF0_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x10004 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x10005 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x10006 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x10007 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x10008 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x10009 #define regBIF_CFG_DEV0_EPF0_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x1000a #define regBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x1000b #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x1000c #define regBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_CAP_PTR 0x1000d #define regBIF_CFG_DEV0_EPF0_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x1000f #define regBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x1000f #define regBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MIN_GRANT 0x1000f #define regBIF_CFG_DEV0_EPF0_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x1000f #define regBIF_CFG_DEV0_EPF0_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x10012 #define regBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x10013 #define regBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x10014 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PMI_CAP 0x10014 #define regBIF_CFG_DEV0_EPF0_PMI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x10015 #define regBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x10019 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP 0x10019 #define regBIF_CFG_DEV0_EPF0_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x1001a #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x1001b #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x1001b #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CAP 0x1001c #define regBIF_CFG_DEV0_EPF0_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL 0x1001d #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS 0x1001d #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x10022 #define regBIF_CFG_DEV0_EPF0_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x10023 #define regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x10023 #define regBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2 0x10024 #define regBIF_CFG_DEV0_EPF0_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x10025 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x10025 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x10028 #define regBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x10028 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x10029 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x1002a #define regBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x1002a #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x1002a #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MASK 0x1002b #define regBIF_CFG_DEV0_EPF0_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x1002b #define regBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x1002b #define regBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x1002c #define regBIF_CFG_DEV0_EPF0_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING 0x1002c #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x1002d #define regBIF_CFG_DEV0_EPF0_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x10030 #define regBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x10030 #define regBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x10031 #define regBIF_CFG_DEV0_EPF0_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA 0x10032 #define regBIF_CFG_DEV0_EPF0_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x10042 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x10043 #define regBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x10044 #define regBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x10045 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x10046 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x10047 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x10047 #define regBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x10048 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x10049 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x1004a #define regBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x1004b #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x1004c #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x1004d #define regBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 #define regBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x10055 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x10056 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x10057 #define regBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x10058 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x10059 #define regBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x1005a #define regBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x1005b #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x1005c #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x1005d #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x1005e #define regBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x10062 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x10063 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x10064 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x10065 #define regBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x10080 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x10081 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x10082 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x10083 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x10084 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x10085 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x10086 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x10087 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x10088 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x10089 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x1008a #define regBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x1008b #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x1008c #define regBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x10092 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x10093 #define regBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x10094 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x10095 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x10096 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x10097 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x10097 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 #define regBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c #define regBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x1009d #define regBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x1009e #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 #define regBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x100a8 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x100a9 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x100a9 #define regBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x100b4 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x100b5 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x100b5 #define regBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x100bc #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x100bd #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x100bd #define regBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x100be #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x100bf #define regBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x100c0 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x100c1 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x100c2 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x100c3 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 #define regBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x100c8 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x100c9 #define regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x100ca #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x100cb #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x100cb #define regBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x100cd #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x100ce #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x100ce #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x100cf #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x100cf #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x100d0 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x100d1 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db #define regBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x10100 #define regBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x10101 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x10102 #define regBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 #define regBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x10105 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x10106 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x10107 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 #define regBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 #define regBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a #define regBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c #define regBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c #define regBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c #define regBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c #define regBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d #define regBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d #define regBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d #define regBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d #define regBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e #define regBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e #define regBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e #define regBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e #define regBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f #define regBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f #define regBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f #define regBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f #define regBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 #define regBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x10115 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x10115 #define regBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x10116 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x10116 #define regBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x10117 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x10117 #define regBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x10118 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x10118 #define regBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x10119 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x10119 #define regBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x1011a #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x1011a #define regBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x1011b #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x1011b #define regBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x1011c #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x1011c #define regBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x1011d #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x1011d #define regBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x1011e #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x1011e #define regBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x1011f #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x1011f #define regBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x10120 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x10120 #define regBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x10121 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x10121 #define regBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x10122 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x10122 #define regBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x10123 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x10123 #define regBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x10124 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x10124 #define regBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x10125 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x10125 #define regBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x10131 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x10133 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x10135 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x10137 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x10139 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c #define regBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x10141 #define regBIF_CFG_DEV0_EPF0_LINK_CAP_32GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x10142 #define regBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x10143 #define regBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp // base address: 0x10160000 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x18000 #define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x18000 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x18001 #define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x18001 #define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x18002 #define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x18002 #define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x18002 #define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x18002 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x18003 #define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x18003 #define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x18003 #define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x18003 #define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x18004 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x18005 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x18006 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x18007 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x18008 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x18009 #define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1800a #define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1800b #define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1800c #define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1800d #define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1800f #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1800f #define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1800f #define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1800f #define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x18019 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x18019 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1801a #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1801b #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1801b #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1801c #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1801d #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1801d #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x18022 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x18023 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x18023 #define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x18024 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x18025 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x18025 #define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x18028 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x18028 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x18029 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1802a #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1802a #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1802a #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1802b #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1802b #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1802b #define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1802c #define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1802c #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1802d #define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x18030 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x18030 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x18031 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x18032 #define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18040 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x18041 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x18042 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x18043 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18054 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x18055 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x18056 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x18057 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x18058 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x18059 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x1805a #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x1805b #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x1805c #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1805d #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1805e #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x18062 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x18063 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x18064 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x18065 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x180ca #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x180cb #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x180cb #define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp // base address: 0x10161000 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x18400 #define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x18400 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x18401 #define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x18401 #define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x18402 #define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x18402 #define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x18402 #define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x18402 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x18403 #define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x18403 #define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x18403 #define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x18403 #define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x18404 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x18405 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x18406 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x18407 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x18408 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x18409 #define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1840a #define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1840b #define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1840c #define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1840d #define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1840f #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1840f #define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1840f #define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1840f #define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x18419 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x18419 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1841a #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1841b #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1841b #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1841c #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1841d #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1841d #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x18422 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x18423 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x18423 #define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x18424 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x18425 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x18425 #define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x18428 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x18428 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x18429 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1842a #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1842a #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1842a #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1842b #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1842b #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1842b #define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1842c #define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1842c #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1842d #define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x18430 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x18430 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x18431 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x18432 #define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18440 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x18441 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x18442 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x18443 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18454 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x18455 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x18456 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x18457 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x18458 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x18459 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x1845a #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x1845b #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x1845c #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1845d #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1845e #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x18462 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x18463 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x18464 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x18465 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x184ca #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x184cb #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x184cb #define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp // base address: 0x10162000 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x18800 #define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x18800 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x18801 #define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x18801 #define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x18802 #define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x18802 #define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x18802 #define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x18802 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x18803 #define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x18803 #define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x18803 #define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x18803 #define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x18804 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x18805 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x18806 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x18807 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x18808 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x18809 #define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1880a #define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1880b #define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1880c #define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1880d #define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1880f #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1880f #define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1880f #define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1880f #define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x18819 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x18819 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1881a #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1881b #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1881b #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1881c #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1881d #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1881d #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x18822 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x18823 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x18823 #define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x18824 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x18825 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x18825 #define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x18828 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x18828 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x18829 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1882a #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1882a #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1882a #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1882b #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1882b #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1882b #define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1882c #define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1882c #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1882d #define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x18830 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x18830 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x18831 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x18832 #define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18840 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x18841 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x18842 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x18843 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18854 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x18855 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x18856 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x18857 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x18858 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x18859 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x1885a #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x1885b #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x1885c #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1885d #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1885e #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x18862 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x18863 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x18864 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x18865 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x188ca #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x188cb #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x188cb #define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp // base address: 0x10163000 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x18c00 #define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x18c00 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x18c01 #define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x18c01 #define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x18c02 #define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x18c02 #define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x18c02 #define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x18c02 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x18c03 #define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x18c03 #define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x18c03 #define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x18c03 #define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x18c04 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x18c05 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x18c06 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x18c07 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x18c08 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x18c09 #define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x18c0a #define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x18c0b #define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x18c0c #define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x18c0d #define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x18c0f #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x18c0f #define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x18c0f #define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x18c0f #define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x18c19 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x18c19 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x18c1a #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x18c1b #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x18c1b #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x18c1c #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x18c1d #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x18c1d #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x18c22 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x18c23 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x18c23 #define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x18c24 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x18c25 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x18c25 #define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x18c28 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x18c28 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x18c29 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x18c2a #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x18c2a #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x18c2a #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x18c2b #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x18c2b #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x18c2b #define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x18c2c #define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x18c2c #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x18c2d #define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x18c30 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x18c30 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x18c31 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x18c32 #define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x18c40 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x18c41 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x18c42 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x18c43 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x18c54 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x18c55 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x18c56 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x18c57 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x18c58 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x18c59 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x18c5a #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x18c5b #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x18c5c #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x18c5d #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x18c5e #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x18c62 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x18c63 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x18c64 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x18c65 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x18cca #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x18ccb #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x18ccb #define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp // base address: 0x10164000 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x19000 #define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x19000 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x19001 #define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x19001 #define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x19002 #define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x19002 #define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x19002 #define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x19002 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x19003 #define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x19003 #define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x19003 #define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x19003 #define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x19004 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x19005 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x19006 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x19007 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x19008 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x19009 #define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1900a #define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1900b #define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1900c #define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1900d #define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1900f #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1900f #define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1900f #define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1900f #define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x19019 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x19019 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1901a #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1901b #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1901b #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1901c #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1901d #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1901d #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x19022 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x19023 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x19023 #define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x19024 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x19025 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x19025 #define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x19028 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x19028 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x19029 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1902a #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1902a #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1902a #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1902b #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1902b #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1902b #define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1902c #define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1902c #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1902d #define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x19030 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x19030 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x19031 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x19032 #define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19040 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x19041 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x19042 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x19043 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19054 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x19055 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x19056 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x19057 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x19058 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x19059 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x1905a #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x1905b #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x1905c #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1905d #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1905e #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x19062 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x19063 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x19064 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x19065 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x190ca #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x190cb #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x190cb #define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp // base address: 0x10165000 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x19400 #define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x19400 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x19401 #define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x19401 #define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x19402 #define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x19402 #define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x19402 #define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x19402 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x19403 #define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x19403 #define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x19403 #define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x19403 #define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x19404 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x19405 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x19406 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x19407 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x19408 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x19409 #define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1940a #define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1940b #define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1940c #define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1940d #define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1940f #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1940f #define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1940f #define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1940f #define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x19419 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x19419 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1941a #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1941b #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1941b #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1941c #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1941d #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1941d #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x19422 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x19423 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x19423 #define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x19424 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x19425 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x19425 #define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x19428 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x19428 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x19429 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1942a #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1942a #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1942a #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1942b #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1942b #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1942b #define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1942c #define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1942c #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1942d #define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x19430 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x19430 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x19431 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x19432 #define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19440 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x19441 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x19442 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x19443 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19454 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x19455 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x19456 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x19457 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x19458 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x19459 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x1945a #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x1945b #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x1945c #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1945d #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1945e #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x19462 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x19463 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x19464 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x19465 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x194ca #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x194cb #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x194cb #define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp // base address: 0x10166000 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x19800 #define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x19800 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x19801 #define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x19801 #define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x19802 #define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x19802 #define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x19802 #define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x19802 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x19803 #define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x19803 #define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x19803 #define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x19803 #define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x19804 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x19805 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x19806 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x19807 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x19808 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x19809 #define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1980a #define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1980b #define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1980c #define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1980d #define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1980f #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1980f #define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1980f #define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1980f #define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x19819 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x19819 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1981a #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1981b #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1981b #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1981c #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1981d #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1981d #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x19822 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x19823 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x19823 #define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x19824 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x19825 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x19825 #define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x19828 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x19828 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x19829 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1982a #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1982a #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1982a #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1982b #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1982b #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1982b #define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1982c #define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1982c #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1982d #define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x19830 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x19830 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x19831 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x19832 #define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19840 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x19841 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x19842 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x19843 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19854 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x19855 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x19856 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x19857 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x19858 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x19859 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x1985a #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x1985b #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x1985c #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1985d #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1985e #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x19862 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x19863 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x19864 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x19865 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x198ca #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x198cb #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x198cb #define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp // base address: 0x10167000 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x19c00 #define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x19c00 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x19c01 #define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x19c01 #define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x19c02 #define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x19c02 #define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x19c02 #define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x19c02 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x19c03 #define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x19c03 #define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x19c03 #define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x19c03 #define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x19c04 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x19c05 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x19c06 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x19c07 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x19c08 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x19c09 #define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x19c0a #define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x19c0b #define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x19c0c #define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x19c0d #define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x19c0f #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x19c0f #define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x19c0f #define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x19c0f #define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x19c19 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x19c19 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x19c1a #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x19c1b #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x19c1b #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x19c1c #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x19c1d #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x19c1d #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x19c22 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x19c23 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x19c23 #define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x19c24 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x19c25 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x19c25 #define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x19c28 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x19c28 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x19c29 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x19c2a #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x19c2a #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x19c2a #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x19c2b #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x19c2b #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x19c2b #define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x19c2c #define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x19c2c #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x19c2d #define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x19c30 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x19c30 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x19c31 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x19c32 #define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x19c40 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x19c41 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x19c42 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x19c43 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x19c54 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x19c55 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x19c56 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x19c57 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x19c58 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x19c59 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x19c5a #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x19c5b #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x19c5c #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x19c5d #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x19c5e #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x19c62 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x19c63 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x19c64 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x19c65 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x19cca #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x19ccb #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x19ccb #define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp // base address: 0x10168000 #define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID 0x1a000 #define regBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID 0x1a000 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_COMMAND 0x1a001 #define regBIF_CFG_DEV0_EPF0_VF8_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_STATUS 0x1a001 #define regBIF_CFG_DEV0_EPF0_VF8_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID 0x1a002 #define regBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE 0x1a002 #define regBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS 0x1a002 #define regBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS 0x1a002 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE 0x1a003 #define regBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LATENCY 0x1a003 #define regBIF_CFG_DEV0_EPF0_VF8_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_HEADER 0x1a003 #define regBIF_CFG_DEV0_EPF0_VF8_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BIST 0x1a003 #define regBIF_CFG_DEV0_EPF0_VF8_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 0x1a004 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 0x1a005 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 0x1a006 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 0x1a007 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 0x1a008 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 0x1a009 #define regBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR 0x1a00a #define regBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID 0x1a00b #define regBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR 0x1a00c #define regBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR 0x1a00d #define regBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE 0x1a00f #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN 0x1a00f #define regBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT 0x1a00f #define regBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY 0x1a00f #define regBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST 0x1a019 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP 0x1a019 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP 0x1a01a #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL 0x1a01b #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS 0x1a01b #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP 0x1a01c #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL 0x1a01d #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS 0x1a01d #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 0x1a022 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 0x1a023 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 0x1a023 #define regBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 0x1a024 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 0x1a025 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 0x1a025 #define regBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST 0x1a028 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL 0x1a028 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO 0x1a029 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI 0x1a02a #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA 0x1a02a #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA 0x1a02a #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK 0x1a02b #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 0x1a02b #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64 0x1a02b #define regBIF_CFG_DEV0_EPF0_VF8_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 0x1a02c #define regBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING 0x1a02c #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 0x1a02d #define regBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST 0x1a030 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL 0x1a030 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE 0x1a031 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA 0x1a032 #define regBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a040 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR 0x1a041 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 0x1a042 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 0x1a043 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a054 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS 0x1a055 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK 0x1a056 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY 0x1a057 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS 0x1a058 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK 0x1a059 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL 0x1a05a #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 0x1a05b #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 0x1a05c #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 0x1a05d #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 0x1a05e #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 0x1a062 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 0x1a063 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 0x1a064 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 0x1a065 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST 0x1a0ca #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP 0x1a0cb #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL 0x1a0cb #define regBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp // base address: 0x10169000 #define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID 0x1a400 #define regBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID 0x1a400 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_COMMAND 0x1a401 #define regBIF_CFG_DEV0_EPF0_VF9_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_STATUS 0x1a401 #define regBIF_CFG_DEV0_EPF0_VF9_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID 0x1a402 #define regBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE 0x1a402 #define regBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS 0x1a402 #define regBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS 0x1a402 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE 0x1a403 #define regBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LATENCY 0x1a403 #define regBIF_CFG_DEV0_EPF0_VF9_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_HEADER 0x1a403 #define regBIF_CFG_DEV0_EPF0_VF9_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BIST 0x1a403 #define regBIF_CFG_DEV0_EPF0_VF9_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 0x1a404 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 0x1a405 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 0x1a406 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 0x1a407 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 0x1a408 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 0x1a409 #define regBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR 0x1a40a #define regBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID 0x1a40b #define regBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR 0x1a40c #define regBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR 0x1a40d #define regBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE 0x1a40f #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN 0x1a40f #define regBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT 0x1a40f #define regBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY 0x1a40f #define regBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST 0x1a419 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP 0x1a419 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP 0x1a41a #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL 0x1a41b #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS 0x1a41b #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP 0x1a41c #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL 0x1a41d #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS 0x1a41d #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 0x1a422 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 0x1a423 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 0x1a423 #define regBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 0x1a424 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 0x1a425 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 0x1a425 #define regBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST 0x1a428 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL 0x1a428 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO 0x1a429 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI 0x1a42a #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA 0x1a42a #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA 0x1a42a #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK 0x1a42b #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 0x1a42b #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64 0x1a42b #define regBIF_CFG_DEV0_EPF0_VF9_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 0x1a42c #define regBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING 0x1a42c #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 0x1a42d #define regBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST 0x1a430 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL 0x1a430 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE 0x1a431 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA 0x1a432 #define regBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a440 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR 0x1a441 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 0x1a442 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 0x1a443 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a454 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS 0x1a455 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK 0x1a456 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY 0x1a457 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS 0x1a458 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK 0x1a459 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL 0x1a45a #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 0x1a45b #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 0x1a45c #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 0x1a45d #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 0x1a45e #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 0x1a462 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 0x1a463 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 0x1a464 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 0x1a465 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST 0x1a4ca #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP 0x1a4cb #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL 0x1a4cb #define regBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp // base address: 0x1016a000 #define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID 0x1a800 #define regBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID 0x1a800 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_COMMAND 0x1a801 #define regBIF_CFG_DEV0_EPF0_VF10_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_STATUS 0x1a801 #define regBIF_CFG_DEV0_EPF0_VF10_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID 0x1a802 #define regBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE 0x1a802 #define regBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS 0x1a802 #define regBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS 0x1a802 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE 0x1a803 #define regBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LATENCY 0x1a803 #define regBIF_CFG_DEV0_EPF0_VF10_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_HEADER 0x1a803 #define regBIF_CFG_DEV0_EPF0_VF10_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BIST 0x1a803 #define regBIF_CFG_DEV0_EPF0_VF10_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 0x1a804 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 0x1a805 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 0x1a806 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 0x1a807 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 0x1a808 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 0x1a809 #define regBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR 0x1a80a #define regBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID 0x1a80b #define regBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR 0x1a80c #define regBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR 0x1a80d #define regBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE 0x1a80f #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN 0x1a80f #define regBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT 0x1a80f #define regBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY 0x1a80f #define regBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST 0x1a819 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP 0x1a819 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP 0x1a81a #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL 0x1a81b #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS 0x1a81b #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP 0x1a81c #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL 0x1a81d #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS 0x1a81d #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 0x1a822 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 0x1a823 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 0x1a823 #define regBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 0x1a824 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 0x1a825 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 0x1a825 #define regBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST 0x1a828 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL 0x1a828 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO 0x1a829 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI 0x1a82a #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA 0x1a82a #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA 0x1a82a #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK 0x1a82b #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 0x1a82b #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64 0x1a82b #define regBIF_CFG_DEV0_EPF0_VF10_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 0x1a82c #define regBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING 0x1a82c #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 0x1a82d #define regBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST 0x1a830 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL 0x1a830 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE 0x1a831 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA 0x1a832 #define regBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1a840 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR 0x1a841 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 0x1a842 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 0x1a843 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1a854 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS 0x1a855 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK 0x1a856 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY 0x1a857 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS 0x1a858 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK 0x1a859 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL 0x1a85a #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 0x1a85b #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 0x1a85c #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 0x1a85d #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 0x1a85e #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 0x1a862 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 0x1a863 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 0x1a864 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 0x1a865 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST 0x1a8ca #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP 0x1a8cb #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL 0x1a8cb #define regBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp // base address: 0x1016b000 #define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID 0x1ac00 #define regBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID 0x1ac00 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_COMMAND 0x1ac01 #define regBIF_CFG_DEV0_EPF0_VF11_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_STATUS 0x1ac01 #define regBIF_CFG_DEV0_EPF0_VF11_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID 0x1ac02 #define regBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE 0x1ac02 #define regBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS 0x1ac02 #define regBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS 0x1ac02 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE 0x1ac03 #define regBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LATENCY 0x1ac03 #define regBIF_CFG_DEV0_EPF0_VF11_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_HEADER 0x1ac03 #define regBIF_CFG_DEV0_EPF0_VF11_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BIST 0x1ac03 #define regBIF_CFG_DEV0_EPF0_VF11_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 0x1ac04 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 0x1ac05 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 0x1ac06 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 0x1ac07 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 0x1ac08 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 0x1ac09 #define regBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR 0x1ac0a #define regBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID 0x1ac0b #define regBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR 0x1ac0c #define regBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR 0x1ac0d #define regBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE 0x1ac0f #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN 0x1ac0f #define regBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT 0x1ac0f #define regBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY 0x1ac0f #define regBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST 0x1ac19 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP 0x1ac19 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP 0x1ac1a #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL 0x1ac1b #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS 0x1ac1b #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP 0x1ac1c #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL 0x1ac1d #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS 0x1ac1d #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 0x1ac22 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 0x1ac23 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 0x1ac23 #define regBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 0x1ac24 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 0x1ac25 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 0x1ac25 #define regBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST 0x1ac28 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL 0x1ac28 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO 0x1ac29 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI 0x1ac2a #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA 0x1ac2a #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA 0x1ac2a #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK 0x1ac2b #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 0x1ac2b #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64 0x1ac2b #define regBIF_CFG_DEV0_EPF0_VF11_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 0x1ac2c #define regBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING 0x1ac2c #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 0x1ac2d #define regBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST 0x1ac30 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL 0x1ac30 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE 0x1ac31 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA 0x1ac32 #define regBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1ac40 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR 0x1ac41 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 0x1ac42 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 0x1ac43 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1ac54 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS 0x1ac55 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK 0x1ac56 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY 0x1ac57 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS 0x1ac58 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK 0x1ac59 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL 0x1ac5a #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 0x1ac5b #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 0x1ac5c #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 0x1ac5d #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 0x1ac5e #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 0x1ac62 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 0x1ac63 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 0x1ac64 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 0x1ac65 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST 0x1acca #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP 0x1accb #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL 0x1accb #define regBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp // base address: 0x1016c000 #define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID 0x1b000 #define regBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID 0x1b000 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_COMMAND 0x1b001 #define regBIF_CFG_DEV0_EPF0_VF12_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_STATUS 0x1b001 #define regBIF_CFG_DEV0_EPF0_VF12_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID 0x1b002 #define regBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE 0x1b002 #define regBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS 0x1b002 #define regBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS 0x1b002 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE 0x1b003 #define regBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LATENCY 0x1b003 #define regBIF_CFG_DEV0_EPF0_VF12_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_HEADER 0x1b003 #define regBIF_CFG_DEV0_EPF0_VF12_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BIST 0x1b003 #define regBIF_CFG_DEV0_EPF0_VF12_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 0x1b004 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 0x1b005 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 0x1b006 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 0x1b007 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 0x1b008 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 0x1b009 #define regBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR 0x1b00a #define regBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID 0x1b00b #define regBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR 0x1b00c #define regBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR 0x1b00d #define regBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE 0x1b00f #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN 0x1b00f #define regBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT 0x1b00f #define regBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY 0x1b00f #define regBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST 0x1b019 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP 0x1b019 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP 0x1b01a #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL 0x1b01b #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS 0x1b01b #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP 0x1b01c #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL 0x1b01d #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS 0x1b01d #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 0x1b022 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 0x1b023 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 0x1b023 #define regBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 0x1b024 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 0x1b025 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 0x1b025 #define regBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST 0x1b028 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL 0x1b028 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO 0x1b029 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI 0x1b02a #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA 0x1b02a #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA 0x1b02a #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK 0x1b02b #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 0x1b02b #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64 0x1b02b #define regBIF_CFG_DEV0_EPF0_VF12_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 0x1b02c #define regBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING 0x1b02c #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 0x1b02d #define regBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST 0x1b030 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL 0x1b030 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE 0x1b031 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA 0x1b032 #define regBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b040 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR 0x1b041 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 0x1b042 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 0x1b043 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b054 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS 0x1b055 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK 0x1b056 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY 0x1b057 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS 0x1b058 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK 0x1b059 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL 0x1b05a #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 0x1b05b #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 0x1b05c #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 0x1b05d #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 0x1b05e #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 0x1b062 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 0x1b063 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 0x1b064 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 0x1b065 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST 0x1b0ca #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP 0x1b0cb #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL 0x1b0cb #define regBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp // base address: 0x1016d000 #define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID 0x1b400 #define regBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID 0x1b400 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_COMMAND 0x1b401 #define regBIF_CFG_DEV0_EPF0_VF13_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_STATUS 0x1b401 #define regBIF_CFG_DEV0_EPF0_VF13_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID 0x1b402 #define regBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE 0x1b402 #define regBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS 0x1b402 #define regBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS 0x1b402 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE 0x1b403 #define regBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LATENCY 0x1b403 #define regBIF_CFG_DEV0_EPF0_VF13_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_HEADER 0x1b403 #define regBIF_CFG_DEV0_EPF0_VF13_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BIST 0x1b403 #define regBIF_CFG_DEV0_EPF0_VF13_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 0x1b404 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 0x1b405 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 0x1b406 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 0x1b407 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 0x1b408 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 0x1b409 #define regBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR 0x1b40a #define regBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID 0x1b40b #define regBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR 0x1b40c #define regBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR 0x1b40d #define regBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE 0x1b40f #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN 0x1b40f #define regBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT 0x1b40f #define regBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY 0x1b40f #define regBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST 0x1b419 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP 0x1b419 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP 0x1b41a #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL 0x1b41b #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS 0x1b41b #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP 0x1b41c #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL 0x1b41d #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS 0x1b41d #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 0x1b422 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 0x1b423 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 0x1b423 #define regBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 0x1b424 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 0x1b425 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 0x1b425 #define regBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST 0x1b428 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL 0x1b428 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO 0x1b429 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI 0x1b42a #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA 0x1b42a #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA 0x1b42a #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK 0x1b42b #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 0x1b42b #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64 0x1b42b #define regBIF_CFG_DEV0_EPF0_VF13_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 0x1b42c #define regBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING 0x1b42c #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 0x1b42d #define regBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST 0x1b430 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL 0x1b430 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE 0x1b431 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA 0x1b432 #define regBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b440 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR 0x1b441 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 0x1b442 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 0x1b443 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b454 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS 0x1b455 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK 0x1b456 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY 0x1b457 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS 0x1b458 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK 0x1b459 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL 0x1b45a #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 0x1b45b #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 0x1b45c #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 0x1b45d #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 0x1b45e #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 0x1b462 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 0x1b463 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 0x1b464 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 0x1b465 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST 0x1b4ca #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP 0x1b4cb #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL 0x1b4cb #define regBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp // base address: 0x1016e000 #define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID 0x1b800 #define regBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID 0x1b800 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_COMMAND 0x1b801 #define regBIF_CFG_DEV0_EPF0_VF14_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_STATUS 0x1b801 #define regBIF_CFG_DEV0_EPF0_VF14_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID 0x1b802 #define regBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE 0x1b802 #define regBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS 0x1b802 #define regBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS 0x1b802 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE 0x1b803 #define regBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LATENCY 0x1b803 #define regBIF_CFG_DEV0_EPF0_VF14_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_HEADER 0x1b803 #define regBIF_CFG_DEV0_EPF0_VF14_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BIST 0x1b803 #define regBIF_CFG_DEV0_EPF0_VF14_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 0x1b804 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 0x1b805 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 0x1b806 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 0x1b807 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 0x1b808 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 0x1b809 #define regBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR 0x1b80a #define regBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID 0x1b80b #define regBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR 0x1b80c #define regBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR 0x1b80d #define regBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE 0x1b80f #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN 0x1b80f #define regBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT 0x1b80f #define regBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY 0x1b80f #define regBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST 0x1b819 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP 0x1b819 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP 0x1b81a #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL 0x1b81b #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS 0x1b81b #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP 0x1b81c #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL 0x1b81d #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS 0x1b81d #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 0x1b822 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 0x1b823 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 0x1b823 #define regBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 0x1b824 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 0x1b825 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 0x1b825 #define regBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST 0x1b828 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL 0x1b828 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO 0x1b829 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI 0x1b82a #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA 0x1b82a #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA 0x1b82a #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK 0x1b82b #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 0x1b82b #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64 0x1b82b #define regBIF_CFG_DEV0_EPF0_VF14_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 0x1b82c #define regBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING 0x1b82c #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 0x1b82d #define regBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST 0x1b830 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL 0x1b830 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE 0x1b831 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA 0x1b832 #define regBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1b840 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR 0x1b841 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 0x1b842 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 0x1b843 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1b854 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS 0x1b855 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK 0x1b856 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY 0x1b857 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS 0x1b858 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK 0x1b859 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL 0x1b85a #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 0x1b85b #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 0x1b85c #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 0x1b85d #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 0x1b85e #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 0x1b862 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 0x1b863 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 0x1b864 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 0x1b865 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST 0x1b8ca #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP 0x1b8cb #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL 0x1b8cb #define regBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp // base address: 0x1016f000 #define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID 0x1bc00 #define regBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID 0x1bc00 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_COMMAND 0x1bc01 #define regBIF_CFG_DEV0_EPF0_VF15_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_STATUS 0x1bc01 #define regBIF_CFG_DEV0_EPF0_VF15_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID 0x1bc02 #define regBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE 0x1bc02 #define regBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS 0x1bc02 #define regBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS 0x1bc02 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE 0x1bc03 #define regBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LATENCY 0x1bc03 #define regBIF_CFG_DEV0_EPF0_VF15_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_HEADER 0x1bc03 #define regBIF_CFG_DEV0_EPF0_VF15_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BIST 0x1bc03 #define regBIF_CFG_DEV0_EPF0_VF15_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 0x1bc04 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 0x1bc05 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 0x1bc06 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 0x1bc07 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 0x1bc08 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 0x1bc09 #define regBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR 0x1bc0a #define regBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID 0x1bc0b #define regBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR 0x1bc0c #define regBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR 0x1bc0d #define regBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE 0x1bc0f #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN 0x1bc0f #define regBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT 0x1bc0f #define regBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY 0x1bc0f #define regBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST 0x1bc19 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP 0x1bc19 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP 0x1bc1a #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL 0x1bc1b #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS 0x1bc1b #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP 0x1bc1c #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL 0x1bc1d #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS 0x1bc1d #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 0x1bc22 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 0x1bc23 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 0x1bc23 #define regBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 0x1bc24 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 0x1bc25 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 0x1bc25 #define regBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST 0x1bc28 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL 0x1bc28 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO 0x1bc29 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI 0x1bc2a #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA 0x1bc2a #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA 0x1bc2a #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK 0x1bc2b #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 0x1bc2b #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64 0x1bc2b #define regBIF_CFG_DEV0_EPF0_VF15_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 0x1bc2c #define regBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING 0x1bc2c #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 0x1bc2d #define regBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST 0x1bc30 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL 0x1bc30 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE 0x1bc31 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA 0x1bc32 #define regBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x1bc40 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR 0x1bc41 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 0x1bc42 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 0x1bc43 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x1bc54 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS 0x1bc55 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK 0x1bc56 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY 0x1bc57 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS 0x1bc58 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK 0x1bc59 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL 0x1bc5a #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 0x1bc5b #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 0x1bc5c #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 0x1bc5d #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 0x1bc5e #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 0x1bc62 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 0x1bc63 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 0x1bc64 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 0x1bc65 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST 0x1bcca #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP 0x1bccb #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL 0x1bccb #define regBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp // base address: 0x10141000 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 #define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 #define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 #define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 #define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 #define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 #define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 #define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 #define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 #define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 #define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 #define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BIST 0x10403 #define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 #define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a #define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c #define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d #define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f #define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f #define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f #define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f #define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 #define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 #define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 #define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 #define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 #define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c #define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d #define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d #define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 #define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 #define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 #define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 #define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 #define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 #define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 #define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a #define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b #define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b #define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b #define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c #define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d #define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 #define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 #define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 #define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 #define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 #define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x10451 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x10452 #define regBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10455 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10456 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10457 #define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10458 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10459 #define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x1045a #define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x1045b #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x1045c #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1045d #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1045e #define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x10462 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10463 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10464 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10465 #define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x10480 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x10481 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x10482 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x10483 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x10484 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x10485 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x10486 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x10487 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x10488 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x10489 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x1048a #define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x1048b #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x1048c #define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x10492 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x10493 #define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x10494 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x10495 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x10496 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x10497 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x10497 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 #define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c #define regBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x1049d #define regBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x1049e #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6 #define regBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x104a8 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x104a9 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x104a9 #define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x104b4 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x104b5 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x104b5 #define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST 0x104bc #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP 0x104bd #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL 0x104bd #define regBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 0x104be #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 0x104bf #define regBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 0x104c0 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 0x104c1 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 0x104c2 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 0x104c3 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x104c4 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x104c5 #define regBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x104c8 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x104c9 #define regBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x104ca #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x104cb #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x104cb #define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x104cc #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x104cd #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x104ce #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x104ce #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x104cf #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x104cf #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x104d0 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x104d1 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x104d2 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db #define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10531 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x10532 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x10533 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x10534 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x10535 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x10536 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x10537 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10538 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10539 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x1053b #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c #define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp // base address: 0x10142000 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID 0x10800 #define regBIF_CFG_DEV0_EPF2_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID 0x10800 #define regBIF_CFG_DEV0_EPF2_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_COMMAND 0x10801 #define regBIF_CFG_DEV0_EPF2_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_STATUS 0x10801 #define regBIF_CFG_DEV0_EPF2_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_REVISION_ID 0x10802 #define regBIF_CFG_DEV0_EPF2_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x10802 #define regBIF_CFG_DEV0_EPF2_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS 0x10802 #define regBIF_CFG_DEV0_EPF2_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS 0x10802 #define regBIF_CFG_DEV0_EPF2_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE 0x10803 #define regBIF_CFG_DEV0_EPF2_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LATENCY 0x10803 #define regBIF_CFG_DEV0_EPF2_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_HEADER 0x10803 #define regBIF_CFG_DEV0_EPF2_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BIST 0x10803 #define regBIF_CFG_DEV0_EPF2_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x10804 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x10805 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x10806 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x10807 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x10808 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x10809 #define regBIF_CFG_DEV0_EPF2_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x1080a #define regBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x1080b #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x1080c #define regBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_CAP_PTR 0x1080d #define regBIF_CFG_DEV0_EPF2_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x1080f #define regBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x1080f #define regBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MIN_GRANT 0x1080f #define regBIF_CFG_DEV0_EPF2_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x1080f #define regBIF_CFG_DEV0_EPF2_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x10812 #define regBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x10813 #define regBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x10814 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PMI_CAP 0x10814 #define regBIF_CFG_DEV0_EPF2_PMI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x10815 #define regBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_SBRN 0x10818 #define regBIF_CFG_DEV0_EPF2_SBRN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_FLADJ 0x10818 #define regBIF_CFG_DEV0_EPF2_FLADJ_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x10818 #define regBIF_CFG_DEV0_EPF2_DBESL_DBESLD_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x10819 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP 0x10819 #define regBIF_CFG_DEV0_EPF2_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x1081a #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x1081b #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x1081b #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_CAP 0x1081c #define regBIF_CFG_DEV0_EPF2_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL 0x1081d #define regBIF_CFG_DEV0_EPF2_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS 0x1081d #define regBIF_CFG_DEV0_EPF2_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x10822 #define regBIF_CFG_DEV0_EPF2_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x10823 #define regBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x10823 #define regBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2 0x10824 #define regBIF_CFG_DEV0_EPF2_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x10825 #define regBIF_CFG_DEV0_EPF2_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x10825 #define regBIF_CFG_DEV0_EPF2_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x10828 #define regBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x10828 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x10829 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x1082a #define regBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x1082a #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x1082a #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MASK 0x1082b #define regBIF_CFG_DEV0_EPF2_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x1082b #define regBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x1082b #define regBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x1082c #define regBIF_CFG_DEV0_EPF2_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING 0x1082c #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x1082d #define regBIF_CFG_DEV0_EPF2_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x10830 #define regBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x10830 #define regBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x10831 #define regBIF_CFG_DEV0_EPF2_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA 0x10832 #define regBIF_CFG_DEV0_EPF2_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x10841 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x10842 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x10843 #define regBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x10855 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x10856 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x10857 #define regBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x10858 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x10859 #define regBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x1085a #define regBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x1085b #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x1085c #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x1085d #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x1085e #define regBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x10862 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x10863 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x10864 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x10865 #define regBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x10880 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x10881 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x10882 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x10883 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x10884 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x10885 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x10886 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x10887 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x10888 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x10889 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x1088a #define regBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x1088b #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x1088c #define regBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x10891 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x10892 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x10893 #define regBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x10894 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x10895 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x10896 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x10897 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x10897 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899 #define regBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x108a8 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x108a9 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x108a9 #define regBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x108b4 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x108b5 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x108b5 #define regBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x108ca #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x108cb #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x108cb #define regBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp // base address: 0x10143000 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID 0x10c00 #define regBIF_CFG_DEV0_EPF3_VENDOR_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID 0x10c00 #define regBIF_CFG_DEV0_EPF3_DEVICE_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_COMMAND 0x10c01 #define regBIF_CFG_DEV0_EPF3_COMMAND_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_STATUS 0x10c01 #define regBIF_CFG_DEV0_EPF3_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_REVISION_ID 0x10c02 #define regBIF_CFG_DEV0_EPF3_REVISION_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x10c02 #define regBIF_CFG_DEV0_EPF3_PROG_INTERFACE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS 0x10c02 #define regBIF_CFG_DEV0_EPF3_SUB_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS 0x10c02 #define regBIF_CFG_DEV0_EPF3_BASE_CLASS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE 0x10c03 #define regBIF_CFG_DEV0_EPF3_CACHE_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LATENCY 0x10c03 #define regBIF_CFG_DEV0_EPF3_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_HEADER 0x10c03 #define regBIF_CFG_DEV0_EPF3_HEADER_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BIST 0x10c03 #define regBIF_CFG_DEV0_EPF3_BIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x10c04 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x10c05 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x10c06 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x10c07 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x10c08 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x10c09 #define regBIF_CFG_DEV0_EPF3_BASE_ADDR_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x10c0a #define regBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x10c0b #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x10c0c #define regBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_CAP_PTR 0x10c0d #define regBIF_CFG_DEV0_EPF3_CAP_PTR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x10c0f #define regBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x10c0f #define regBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MIN_GRANT 0x10c0f #define regBIF_CFG_DEV0_EPF3_MIN_GRANT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x10c0f #define regBIF_CFG_DEV0_EPF3_MAX_LATENCY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x10c12 #define regBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x10c13 #define regBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x10c14 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PMI_CAP 0x10c14 #define regBIF_CFG_DEV0_EPF3_PMI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x10c15 #define regBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_SBRN 0x10c18 #define regBIF_CFG_DEV0_EPF3_SBRN_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_FLADJ 0x10c18 #define regBIF_CFG_DEV0_EPF3_FLADJ_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x10c18 #define regBIF_CFG_DEV0_EPF3_DBESL_DBESLD_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x10c19 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP 0x10c19 #define regBIF_CFG_DEV0_EPF3_PCIE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x10c1a #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x10c1b #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x10c1b #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_CAP 0x10c1c #define regBIF_CFG_DEV0_EPF3_LINK_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL 0x10c1d #define regBIF_CFG_DEV0_EPF3_LINK_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS 0x10c1d #define regBIF_CFG_DEV0_EPF3_LINK_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x10c22 #define regBIF_CFG_DEV0_EPF3_DEVICE_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x10c23 #define regBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x10c23 #define regBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2 0x10c24 #define regBIF_CFG_DEV0_EPF3_LINK_CAP2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x10c25 #define regBIF_CFG_DEV0_EPF3_LINK_CNTL2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x10c25 #define regBIF_CFG_DEV0_EPF3_LINK_STATUS2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x10c28 #define regBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x10c28 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x10c29 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x10c2a #define regBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x10c2a #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x10c2a #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MASK 0x10c2b #define regBIF_CFG_DEV0_EPF3_MSI_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x10c2b #define regBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x10c2b #define regBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x10c2c #define regBIF_CFG_DEV0_EPF3_MSI_MASK_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING 0x10c2c #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x10c2d #define regBIF_CFG_DEV0_EPF3_MSI_PENDING_64_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x10c30 #define regBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x10c30 #define regBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x10c31 #define regBIF_CFG_DEV0_EPF3_MSIX_TABLE_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA 0x10c32 #define regBIF_CFG_DEV0_EPF3_MSIX_PBA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x10c41 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x10c42 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x10c43 #define regBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x10c55 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x10c56 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x10c57 #define regBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x10c58 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x10c59 #define regBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x10c5a #define regBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x10c5b #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x10c5c #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x10c5d #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x10c5e #define regBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x10c62 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x10c63 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x10c64 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x10c65 #define regBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x10c80 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x10c81 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x10c82 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x10c83 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x10c84 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x10c85 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x10c86 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x10c87 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x10c88 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x10c89 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x10c8a #define regBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x10c8b #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x10c8c #define regBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x10c92 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x10c93 #define regBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x10c94 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x10c95 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x10c96 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x10c97 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x10c97 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99 #define regBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x10ca8 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x10ca9 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x10ca9 #define regBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x10cb4 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x10cb5 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x10cb5 #define regBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x10cca #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x10ccb #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_BASE_IDX 5 #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x10ccb #define regBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC // base address: 0x10131000 #define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 #define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 #define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC // base address: 0x10131000 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e #define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC // base address: 0x10131000 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC // base address: 0x10131000 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 // base address: 0x10170000 #define regPCIEMSIX_VECT0_ADDR_LO 0x1c000 #define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT0_ADDR_HI 0x1c001 #define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT0_MSG_DATA 0x1c002 #define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT0_CONTROL 0x1c003 #define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT1_ADDR_LO 0x1c004 #define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT1_ADDR_HI 0x1c005 #define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT1_MSG_DATA 0x1c006 #define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT1_CONTROL 0x1c007 #define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT2_ADDR_LO 0x1c008 #define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT2_ADDR_HI 0x1c009 #define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT2_MSG_DATA 0x1c00a #define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT2_CONTROL 0x1c00b #define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT3_ADDR_LO 0x1c00c #define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT3_ADDR_HI 0x1c00d #define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT3_MSG_DATA 0x1c00e #define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT3_CONTROL 0x1c00f #define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT4_ADDR_LO 0x1c010 #define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT4_ADDR_HI 0x1c011 #define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT4_MSG_DATA 0x1c012 #define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT4_CONTROL 0x1c013 #define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT5_ADDR_LO 0x1c014 #define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT5_ADDR_HI 0x1c015 #define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT5_MSG_DATA 0x1c016 #define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT5_CONTROL 0x1c017 #define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT6_ADDR_LO 0x1c018 #define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT6_ADDR_HI 0x1c019 #define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT6_MSG_DATA 0x1c01a #define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT6_CONTROL 0x1c01b #define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT7_ADDR_LO 0x1c01c #define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT7_ADDR_HI 0x1c01d #define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT7_MSG_DATA 0x1c01e #define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT7_CONTROL 0x1c01f #define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT8_ADDR_LO 0x1c020 #define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT8_ADDR_HI 0x1c021 #define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT8_MSG_DATA 0x1c022 #define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT8_CONTROL 0x1c023 #define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT9_ADDR_LO 0x1c024 #define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT9_ADDR_HI 0x1c025 #define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT9_MSG_DATA 0x1c026 #define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT9_CONTROL 0x1c027 #define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT10_ADDR_LO 0x1c028 #define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT10_ADDR_HI 0x1c029 #define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT10_MSG_DATA 0x1c02a #define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT10_CONTROL 0x1c02b #define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT11_ADDR_LO 0x1c02c #define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT11_ADDR_HI 0x1c02d #define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT11_MSG_DATA 0x1c02e #define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT11_CONTROL 0x1c02f #define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT12_ADDR_LO 0x1c030 #define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT12_ADDR_HI 0x1c031 #define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT12_MSG_DATA 0x1c032 #define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT12_CONTROL 0x1c033 #define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT13_ADDR_LO 0x1c034 #define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT13_ADDR_HI 0x1c035 #define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT13_MSG_DATA 0x1c036 #define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT13_CONTROL 0x1c037 #define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT14_ADDR_LO 0x1c038 #define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT14_ADDR_HI 0x1c039 #define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT14_MSG_DATA 0x1c03a #define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT14_CONTROL 0x1c03b #define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT15_ADDR_LO 0x1c03c #define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT15_ADDR_HI 0x1c03d #define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT15_MSG_DATA 0x1c03e #define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT15_CONTROL 0x1c03f #define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT16_ADDR_LO 0x1c040 #define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT16_ADDR_HI 0x1c041 #define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT16_MSG_DATA 0x1c042 #define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT16_CONTROL 0x1c043 #define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT17_ADDR_LO 0x1c044 #define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT17_ADDR_HI 0x1c045 #define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT17_MSG_DATA 0x1c046 #define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT17_CONTROL 0x1c047 #define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT18_ADDR_LO 0x1c048 #define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT18_ADDR_HI 0x1c049 #define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT18_MSG_DATA 0x1c04a #define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT18_CONTROL 0x1c04b #define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT19_ADDR_LO 0x1c04c #define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT19_ADDR_HI 0x1c04d #define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT19_MSG_DATA 0x1c04e #define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT19_CONTROL 0x1c04f #define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT20_ADDR_LO 0x1c050 #define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT20_ADDR_HI 0x1c051 #define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT20_MSG_DATA 0x1c052 #define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT20_CONTROL 0x1c053 #define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT21_ADDR_LO 0x1c054 #define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT21_ADDR_HI 0x1c055 #define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT21_MSG_DATA 0x1c056 #define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT21_CONTROL 0x1c057 #define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT22_ADDR_LO 0x1c058 #define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT22_ADDR_HI 0x1c059 #define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT22_MSG_DATA 0x1c05a #define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT22_CONTROL 0x1c05b #define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT23_ADDR_LO 0x1c05c #define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT23_ADDR_HI 0x1c05d #define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT23_MSG_DATA 0x1c05e #define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT23_CONTROL 0x1c05f #define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT24_ADDR_LO 0x1c060 #define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT24_ADDR_HI 0x1c061 #define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT24_MSG_DATA 0x1c062 #define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT24_CONTROL 0x1c063 #define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT25_ADDR_LO 0x1c064 #define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT25_ADDR_HI 0x1c065 #define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT25_MSG_DATA 0x1c066 #define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT25_CONTROL 0x1c067 #define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT26_ADDR_LO 0x1c068 #define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT26_ADDR_HI 0x1c069 #define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT26_MSG_DATA 0x1c06a #define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT26_CONTROL 0x1c06b #define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT27_ADDR_LO 0x1c06c #define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT27_ADDR_HI 0x1c06d #define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT27_MSG_DATA 0x1c06e #define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT27_CONTROL 0x1c06f #define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT28_ADDR_LO 0x1c070 #define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT28_ADDR_HI 0x1c071 #define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT28_MSG_DATA 0x1c072 #define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT28_CONTROL 0x1c073 #define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT29_ADDR_LO 0x1c074 #define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT29_ADDR_HI 0x1c075 #define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT29_MSG_DATA 0x1c076 #define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT29_CONTROL 0x1c077 #define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT30_ADDR_LO 0x1c078 #define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT30_ADDR_HI 0x1c079 #define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT30_MSG_DATA 0x1c07a #define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT30_CONTROL 0x1c07b #define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT31_ADDR_LO 0x1c07c #define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT31_ADDR_HI 0x1c07d #define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT31_MSG_DATA 0x1c07e #define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT31_CONTROL 0x1c07f #define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT32_ADDR_LO 0x1c080 #define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT32_ADDR_HI 0x1c081 #define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT32_MSG_DATA 0x1c082 #define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT32_CONTROL 0x1c083 #define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT33_ADDR_LO 0x1c084 #define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT33_ADDR_HI 0x1c085 #define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT33_MSG_DATA 0x1c086 #define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT33_CONTROL 0x1c087 #define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT34_ADDR_LO 0x1c088 #define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT34_ADDR_HI 0x1c089 #define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT34_MSG_DATA 0x1c08a #define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT34_CONTROL 0x1c08b #define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT35_ADDR_LO 0x1c08c #define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT35_ADDR_HI 0x1c08d #define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT35_MSG_DATA 0x1c08e #define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT35_CONTROL 0x1c08f #define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT36_ADDR_LO 0x1c090 #define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT36_ADDR_HI 0x1c091 #define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT36_MSG_DATA 0x1c092 #define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT36_CONTROL 0x1c093 #define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT37_ADDR_LO 0x1c094 #define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT37_ADDR_HI 0x1c095 #define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT37_MSG_DATA 0x1c096 #define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT37_CONTROL 0x1c097 #define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT38_ADDR_LO 0x1c098 #define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT38_ADDR_HI 0x1c099 #define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT38_MSG_DATA 0x1c09a #define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT38_CONTROL 0x1c09b #define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT39_ADDR_LO 0x1c09c #define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT39_ADDR_HI 0x1c09d #define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT39_MSG_DATA 0x1c09e #define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT39_CONTROL 0x1c09f #define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT40_ADDR_LO 0x1c0a0 #define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT40_ADDR_HI 0x1c0a1 #define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT40_MSG_DATA 0x1c0a2 #define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT40_CONTROL 0x1c0a3 #define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT41_ADDR_LO 0x1c0a4 #define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT41_ADDR_HI 0x1c0a5 #define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT41_MSG_DATA 0x1c0a6 #define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT41_CONTROL 0x1c0a7 #define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT42_ADDR_LO 0x1c0a8 #define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT42_ADDR_HI 0x1c0a9 #define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT42_MSG_DATA 0x1c0aa #define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT42_CONTROL 0x1c0ab #define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT43_ADDR_LO 0x1c0ac #define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT43_ADDR_HI 0x1c0ad #define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT43_MSG_DATA 0x1c0ae #define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT43_CONTROL 0x1c0af #define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT44_ADDR_LO 0x1c0b0 #define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT44_ADDR_HI 0x1c0b1 #define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT44_MSG_DATA 0x1c0b2 #define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT44_CONTROL 0x1c0b3 #define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT45_ADDR_LO 0x1c0b4 #define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT45_ADDR_HI 0x1c0b5 #define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT45_MSG_DATA 0x1c0b6 #define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT45_CONTROL 0x1c0b7 #define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT46_ADDR_LO 0x1c0b8 #define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT46_ADDR_HI 0x1c0b9 #define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT46_MSG_DATA 0x1c0ba #define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT46_CONTROL 0x1c0bb #define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT47_ADDR_LO 0x1c0bc #define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT47_ADDR_HI 0x1c0bd #define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT47_MSG_DATA 0x1c0be #define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT47_CONTROL 0x1c0bf #define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT48_ADDR_LO 0x1c0c0 #define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT48_ADDR_HI 0x1c0c1 #define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT48_MSG_DATA 0x1c0c2 #define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT48_CONTROL 0x1c0c3 #define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT49_ADDR_LO 0x1c0c4 #define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT49_ADDR_HI 0x1c0c5 #define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT49_MSG_DATA 0x1c0c6 #define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT49_CONTROL 0x1c0c7 #define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT50_ADDR_LO 0x1c0c8 #define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT50_ADDR_HI 0x1c0c9 #define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT50_MSG_DATA 0x1c0ca #define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT50_CONTROL 0x1c0cb #define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT51_ADDR_LO 0x1c0cc #define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT51_ADDR_HI 0x1c0cd #define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT51_MSG_DATA 0x1c0ce #define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT51_CONTROL 0x1c0cf #define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT52_ADDR_LO 0x1c0d0 #define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT52_ADDR_HI 0x1c0d1 #define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT52_MSG_DATA 0x1c0d2 #define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT52_CONTROL 0x1c0d3 #define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT53_ADDR_LO 0x1c0d4 #define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT53_ADDR_HI 0x1c0d5 #define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT53_MSG_DATA 0x1c0d6 #define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT53_CONTROL 0x1c0d7 #define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT54_ADDR_LO 0x1c0d8 #define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT54_ADDR_HI 0x1c0d9 #define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT54_MSG_DATA 0x1c0da #define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT54_CONTROL 0x1c0db #define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT55_ADDR_LO 0x1c0dc #define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT55_ADDR_HI 0x1c0dd #define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT55_MSG_DATA 0x1c0de #define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT55_CONTROL 0x1c0df #define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT56_ADDR_LO 0x1c0e0 #define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT56_ADDR_HI 0x1c0e1 #define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT56_MSG_DATA 0x1c0e2 #define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT56_CONTROL 0x1c0e3 #define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT57_ADDR_LO 0x1c0e4 #define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT57_ADDR_HI 0x1c0e5 #define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT57_MSG_DATA 0x1c0e6 #define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT57_CONTROL 0x1c0e7 #define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT58_ADDR_LO 0x1c0e8 #define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT58_ADDR_HI 0x1c0e9 #define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT58_MSG_DATA 0x1c0ea #define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT58_CONTROL 0x1c0eb #define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT59_ADDR_LO 0x1c0ec #define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT59_ADDR_HI 0x1c0ed #define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT59_MSG_DATA 0x1c0ee #define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT59_CONTROL 0x1c0ef #define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT60_ADDR_LO 0x1c0f0 #define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT60_ADDR_HI 0x1c0f1 #define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT60_MSG_DATA 0x1c0f2 #define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT60_CONTROL 0x1c0f3 #define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT61_ADDR_LO 0x1c0f4 #define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT61_ADDR_HI 0x1c0f5 #define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT61_MSG_DATA 0x1c0f6 #define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT61_CONTROL 0x1c0f7 #define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT62_ADDR_LO 0x1c0f8 #define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT62_ADDR_HI 0x1c0f9 #define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT62_MSG_DATA 0x1c0fa #define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT62_CONTROL 0x1c0fb #define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT63_ADDR_LO 0x1c0fc #define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT63_ADDR_HI 0x1c0fd #define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT63_MSG_DATA 0x1c0fe #define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT63_CONTROL 0x1c0ff #define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT64_ADDR_LO 0x1c100 #define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT64_ADDR_HI 0x1c101 #define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT64_MSG_DATA 0x1c102 #define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT64_CONTROL 0x1c103 #define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT65_ADDR_LO 0x1c104 #define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT65_ADDR_HI 0x1c105 #define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT65_MSG_DATA 0x1c106 #define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT65_CONTROL 0x1c107 #define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT66_ADDR_LO 0x1c108 #define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT66_ADDR_HI 0x1c109 #define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT66_MSG_DATA 0x1c10a #define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT66_CONTROL 0x1c10b #define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT67_ADDR_LO 0x1c10c #define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT67_ADDR_HI 0x1c10d #define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT67_MSG_DATA 0x1c10e #define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT67_CONTROL 0x1c10f #define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT68_ADDR_LO 0x1c110 #define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT68_ADDR_HI 0x1c111 #define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT68_MSG_DATA 0x1c112 #define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT68_CONTROL 0x1c113 #define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT69_ADDR_LO 0x1c114 #define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT69_ADDR_HI 0x1c115 #define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT69_MSG_DATA 0x1c116 #define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT69_CONTROL 0x1c117 #define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT70_ADDR_LO 0x1c118 #define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT70_ADDR_HI 0x1c119 #define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT70_MSG_DATA 0x1c11a #define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT70_CONTROL 0x1c11b #define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT71_ADDR_LO 0x1c11c #define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT71_ADDR_HI 0x1c11d #define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT71_MSG_DATA 0x1c11e #define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT71_CONTROL 0x1c11f #define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT72_ADDR_LO 0x1c120 #define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT72_ADDR_HI 0x1c121 #define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT72_MSG_DATA 0x1c122 #define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT72_CONTROL 0x1c123 #define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT73_ADDR_LO 0x1c124 #define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT73_ADDR_HI 0x1c125 #define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT73_MSG_DATA 0x1c126 #define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT73_CONTROL 0x1c127 #define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT74_ADDR_LO 0x1c128 #define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT74_ADDR_HI 0x1c129 #define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT74_MSG_DATA 0x1c12a #define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT74_CONTROL 0x1c12b #define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT75_ADDR_LO 0x1c12c #define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT75_ADDR_HI 0x1c12d #define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT75_MSG_DATA 0x1c12e #define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT75_CONTROL 0x1c12f #define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT76_ADDR_LO 0x1c130 #define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT76_ADDR_HI 0x1c131 #define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT76_MSG_DATA 0x1c132 #define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT76_CONTROL 0x1c133 #define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT77_ADDR_LO 0x1c134 #define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT77_ADDR_HI 0x1c135 #define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT77_MSG_DATA 0x1c136 #define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT77_CONTROL 0x1c137 #define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT78_ADDR_LO 0x1c138 #define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT78_ADDR_HI 0x1c139 #define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT78_MSG_DATA 0x1c13a #define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT78_CONTROL 0x1c13b #define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT79_ADDR_LO 0x1c13c #define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT79_ADDR_HI 0x1c13d #define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT79_MSG_DATA 0x1c13e #define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT79_CONTROL 0x1c13f #define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT80_ADDR_LO 0x1c140 #define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT80_ADDR_HI 0x1c141 #define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT80_MSG_DATA 0x1c142 #define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT80_CONTROL 0x1c143 #define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT81_ADDR_LO 0x1c144 #define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT81_ADDR_HI 0x1c145 #define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT81_MSG_DATA 0x1c146 #define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT81_CONTROL 0x1c147 #define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT82_ADDR_LO 0x1c148 #define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT82_ADDR_HI 0x1c149 #define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT82_MSG_DATA 0x1c14a #define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT82_CONTROL 0x1c14b #define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT83_ADDR_LO 0x1c14c #define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT83_ADDR_HI 0x1c14d #define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT83_MSG_DATA 0x1c14e #define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT83_CONTROL 0x1c14f #define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT84_ADDR_LO 0x1c150 #define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT84_ADDR_HI 0x1c151 #define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT84_MSG_DATA 0x1c152 #define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT84_CONTROL 0x1c153 #define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT85_ADDR_LO 0x1c154 #define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT85_ADDR_HI 0x1c155 #define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT85_MSG_DATA 0x1c156 #define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT85_CONTROL 0x1c157 #define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT86_ADDR_LO 0x1c158 #define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT86_ADDR_HI 0x1c159 #define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT86_MSG_DATA 0x1c15a #define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT86_CONTROL 0x1c15b #define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT87_ADDR_LO 0x1c15c #define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT87_ADDR_HI 0x1c15d #define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT87_MSG_DATA 0x1c15e #define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT87_CONTROL 0x1c15f #define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT88_ADDR_LO 0x1c160 #define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT88_ADDR_HI 0x1c161 #define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT88_MSG_DATA 0x1c162 #define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT88_CONTROL 0x1c163 #define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT89_ADDR_LO 0x1c164 #define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT89_ADDR_HI 0x1c165 #define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT89_MSG_DATA 0x1c166 #define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT89_CONTROL 0x1c167 #define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT90_ADDR_LO 0x1c168 #define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT90_ADDR_HI 0x1c169 #define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT90_MSG_DATA 0x1c16a #define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT90_CONTROL 0x1c16b #define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT91_ADDR_LO 0x1c16c #define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT91_ADDR_HI 0x1c16d #define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT91_MSG_DATA 0x1c16e #define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT91_CONTROL 0x1c16f #define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT92_ADDR_LO 0x1c170 #define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT92_ADDR_HI 0x1c171 #define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT92_MSG_DATA 0x1c172 #define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT92_CONTROL 0x1c173 #define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT93_ADDR_LO 0x1c174 #define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT93_ADDR_HI 0x1c175 #define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT93_MSG_DATA 0x1c176 #define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT93_CONTROL 0x1c177 #define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT94_ADDR_LO 0x1c178 #define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT94_ADDR_HI 0x1c179 #define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT94_MSG_DATA 0x1c17a #define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT94_CONTROL 0x1c17b #define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT95_ADDR_LO 0x1c17c #define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT95_ADDR_HI 0x1c17d #define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT95_MSG_DATA 0x1c17e #define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT95_CONTROL 0x1c17f #define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT96_ADDR_LO 0x1c180 #define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT96_ADDR_HI 0x1c181 #define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT96_MSG_DATA 0x1c182 #define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT96_CONTROL 0x1c183 #define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT97_ADDR_LO 0x1c184 #define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT97_ADDR_HI 0x1c185 #define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT97_MSG_DATA 0x1c186 #define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT97_CONTROL 0x1c187 #define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT98_ADDR_LO 0x1c188 #define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT98_ADDR_HI 0x1c189 #define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT98_MSG_DATA 0x1c18a #define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT98_CONTROL 0x1c18b #define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT99_ADDR_LO 0x1c18c #define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT99_ADDR_HI 0x1c18d #define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT99_MSG_DATA 0x1c18e #define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT99_CONTROL 0x1c18f #define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT100_ADDR_LO 0x1c190 #define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT100_ADDR_HI 0x1c191 #define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT100_MSG_DATA 0x1c192 #define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT100_CONTROL 0x1c193 #define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT101_ADDR_LO 0x1c194 #define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT101_ADDR_HI 0x1c195 #define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT101_MSG_DATA 0x1c196 #define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT101_CONTROL 0x1c197 #define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT102_ADDR_LO 0x1c198 #define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT102_ADDR_HI 0x1c199 #define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT102_MSG_DATA 0x1c19a #define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT102_CONTROL 0x1c19b #define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT103_ADDR_LO 0x1c19c #define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT103_ADDR_HI 0x1c19d #define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT103_MSG_DATA 0x1c19e #define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT103_CONTROL 0x1c19f #define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT104_ADDR_LO 0x1c1a0 #define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT104_ADDR_HI 0x1c1a1 #define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT104_MSG_DATA 0x1c1a2 #define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT104_CONTROL 0x1c1a3 #define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT105_ADDR_LO 0x1c1a4 #define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT105_ADDR_HI 0x1c1a5 #define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT105_MSG_DATA 0x1c1a6 #define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT105_CONTROL 0x1c1a7 #define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT106_ADDR_LO 0x1c1a8 #define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT106_ADDR_HI 0x1c1a9 #define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT106_MSG_DATA 0x1c1aa #define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT106_CONTROL 0x1c1ab #define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT107_ADDR_LO 0x1c1ac #define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT107_ADDR_HI 0x1c1ad #define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT107_MSG_DATA 0x1c1ae #define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT107_CONTROL 0x1c1af #define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT108_ADDR_LO 0x1c1b0 #define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT108_ADDR_HI 0x1c1b1 #define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT108_MSG_DATA 0x1c1b2 #define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT108_CONTROL 0x1c1b3 #define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT109_ADDR_LO 0x1c1b4 #define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT109_ADDR_HI 0x1c1b5 #define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT109_MSG_DATA 0x1c1b6 #define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT109_CONTROL 0x1c1b7 #define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT110_ADDR_LO 0x1c1b8 #define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT110_ADDR_HI 0x1c1b9 #define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT110_MSG_DATA 0x1c1ba #define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT110_CONTROL 0x1c1bb #define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT111_ADDR_LO 0x1c1bc #define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT111_ADDR_HI 0x1c1bd #define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT111_MSG_DATA 0x1c1be #define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT111_CONTROL 0x1c1bf #define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT112_ADDR_LO 0x1c1c0 #define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT112_ADDR_HI 0x1c1c1 #define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT112_MSG_DATA 0x1c1c2 #define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT112_CONTROL 0x1c1c3 #define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT113_ADDR_LO 0x1c1c4 #define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT113_ADDR_HI 0x1c1c5 #define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT113_MSG_DATA 0x1c1c6 #define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT113_CONTROL 0x1c1c7 #define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT114_ADDR_LO 0x1c1c8 #define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT114_ADDR_HI 0x1c1c9 #define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT114_MSG_DATA 0x1c1ca #define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT114_CONTROL 0x1c1cb #define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT115_ADDR_LO 0x1c1cc #define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT115_ADDR_HI 0x1c1cd #define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT115_MSG_DATA 0x1c1ce #define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT115_CONTROL 0x1c1cf #define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT116_ADDR_LO 0x1c1d0 #define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT116_ADDR_HI 0x1c1d1 #define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT116_MSG_DATA 0x1c1d2 #define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT116_CONTROL 0x1c1d3 #define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT117_ADDR_LO 0x1c1d4 #define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT117_ADDR_HI 0x1c1d5 #define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT117_MSG_DATA 0x1c1d6 #define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT117_CONTROL 0x1c1d7 #define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT118_ADDR_LO 0x1c1d8 #define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT118_ADDR_HI 0x1c1d9 #define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT118_MSG_DATA 0x1c1da #define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT118_CONTROL 0x1c1db #define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT119_ADDR_LO 0x1c1dc #define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT119_ADDR_HI 0x1c1dd #define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT119_MSG_DATA 0x1c1de #define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT119_CONTROL 0x1c1df #define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT120_ADDR_LO 0x1c1e0 #define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT120_ADDR_HI 0x1c1e1 #define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT120_MSG_DATA 0x1c1e2 #define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT120_CONTROL 0x1c1e3 #define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT121_ADDR_LO 0x1c1e4 #define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT121_ADDR_HI 0x1c1e5 #define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT121_MSG_DATA 0x1c1e6 #define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT121_CONTROL 0x1c1e7 #define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT122_ADDR_LO 0x1c1e8 #define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT122_ADDR_HI 0x1c1e9 #define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT122_MSG_DATA 0x1c1ea #define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT122_CONTROL 0x1c1eb #define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT123_ADDR_LO 0x1c1ec #define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT123_ADDR_HI 0x1c1ed #define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT123_MSG_DATA 0x1c1ee #define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT123_CONTROL 0x1c1ef #define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT124_ADDR_LO 0x1c1f0 #define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT124_ADDR_HI 0x1c1f1 #define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT124_MSG_DATA 0x1c1f2 #define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT124_CONTROL 0x1c1f3 #define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT125_ADDR_LO 0x1c1f4 #define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT125_ADDR_HI 0x1c1f5 #define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT125_MSG_DATA 0x1c1f6 #define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT125_CONTROL 0x1c1f7 #define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT126_ADDR_LO 0x1c1f8 #define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT126_ADDR_HI 0x1c1f9 #define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT126_MSG_DATA 0x1c1fa #define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT126_CONTROL 0x1c1fb #define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT127_ADDR_LO 0x1c1fc #define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT127_ADDR_HI 0x1c1fd #define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT127_MSG_DATA 0x1c1fe #define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT127_CONTROL 0x1c1ff #define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT128_ADDR_LO 0x1c200 #define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT128_ADDR_HI 0x1c201 #define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT128_MSG_DATA 0x1c202 #define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT128_CONTROL 0x1c203 #define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT129_ADDR_LO 0x1c204 #define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT129_ADDR_HI 0x1c205 #define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT129_MSG_DATA 0x1c206 #define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT129_CONTROL 0x1c207 #define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT130_ADDR_LO 0x1c208 #define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT130_ADDR_HI 0x1c209 #define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT130_MSG_DATA 0x1c20a #define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT130_CONTROL 0x1c20b #define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT131_ADDR_LO 0x1c20c #define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT131_ADDR_HI 0x1c20d #define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT131_MSG_DATA 0x1c20e #define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT131_CONTROL 0x1c20f #define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT132_ADDR_LO 0x1c210 #define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT132_ADDR_HI 0x1c211 #define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT132_MSG_DATA 0x1c212 #define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT132_CONTROL 0x1c213 #define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT133_ADDR_LO 0x1c214 #define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT133_ADDR_HI 0x1c215 #define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT133_MSG_DATA 0x1c216 #define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT133_CONTROL 0x1c217 #define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT134_ADDR_LO 0x1c218 #define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT134_ADDR_HI 0x1c219 #define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT134_MSG_DATA 0x1c21a #define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT134_CONTROL 0x1c21b #define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT135_ADDR_LO 0x1c21c #define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT135_ADDR_HI 0x1c21d #define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT135_MSG_DATA 0x1c21e #define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT135_CONTROL 0x1c21f #define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT136_ADDR_LO 0x1c220 #define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT136_ADDR_HI 0x1c221 #define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT136_MSG_DATA 0x1c222 #define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT136_CONTROL 0x1c223 #define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT137_ADDR_LO 0x1c224 #define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT137_ADDR_HI 0x1c225 #define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT137_MSG_DATA 0x1c226 #define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT137_CONTROL 0x1c227 #define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT138_ADDR_LO 0x1c228 #define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT138_ADDR_HI 0x1c229 #define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT138_MSG_DATA 0x1c22a #define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT138_CONTROL 0x1c22b #define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT139_ADDR_LO 0x1c22c #define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT139_ADDR_HI 0x1c22d #define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT139_MSG_DATA 0x1c22e #define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT139_CONTROL 0x1c22f #define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT140_ADDR_LO 0x1c230 #define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT140_ADDR_HI 0x1c231 #define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT140_MSG_DATA 0x1c232 #define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT140_CONTROL 0x1c233 #define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT141_ADDR_LO 0x1c234 #define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT141_ADDR_HI 0x1c235 #define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT141_MSG_DATA 0x1c236 #define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT141_CONTROL 0x1c237 #define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT142_ADDR_LO 0x1c238 #define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT142_ADDR_HI 0x1c239 #define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT142_MSG_DATA 0x1c23a #define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT142_CONTROL 0x1c23b #define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT143_ADDR_LO 0x1c23c #define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT143_ADDR_HI 0x1c23d #define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT143_MSG_DATA 0x1c23e #define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT143_CONTROL 0x1c23f #define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT144_ADDR_LO 0x1c240 #define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT144_ADDR_HI 0x1c241 #define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT144_MSG_DATA 0x1c242 #define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT144_CONTROL 0x1c243 #define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT145_ADDR_LO 0x1c244 #define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT145_ADDR_HI 0x1c245 #define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT145_MSG_DATA 0x1c246 #define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT145_CONTROL 0x1c247 #define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT146_ADDR_LO 0x1c248 #define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT146_ADDR_HI 0x1c249 #define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT146_MSG_DATA 0x1c24a #define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT146_CONTROL 0x1c24b #define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT147_ADDR_LO 0x1c24c #define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT147_ADDR_HI 0x1c24d #define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT147_MSG_DATA 0x1c24e #define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT147_CONTROL 0x1c24f #define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT148_ADDR_LO 0x1c250 #define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT148_ADDR_HI 0x1c251 #define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT148_MSG_DATA 0x1c252 #define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT148_CONTROL 0x1c253 #define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT149_ADDR_LO 0x1c254 #define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT149_ADDR_HI 0x1c255 #define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT149_MSG_DATA 0x1c256 #define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT149_CONTROL 0x1c257 #define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT150_ADDR_LO 0x1c258 #define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT150_ADDR_HI 0x1c259 #define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT150_MSG_DATA 0x1c25a #define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT150_CONTROL 0x1c25b #define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT151_ADDR_LO 0x1c25c #define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT151_ADDR_HI 0x1c25d #define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT151_MSG_DATA 0x1c25e #define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT151_CONTROL 0x1c25f #define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT152_ADDR_LO 0x1c260 #define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT152_ADDR_HI 0x1c261 #define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT152_MSG_DATA 0x1c262 #define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT152_CONTROL 0x1c263 #define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT153_ADDR_LO 0x1c264 #define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT153_ADDR_HI 0x1c265 #define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT153_MSG_DATA 0x1c266 #define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT153_CONTROL 0x1c267 #define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT154_ADDR_LO 0x1c268 #define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT154_ADDR_HI 0x1c269 #define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT154_MSG_DATA 0x1c26a #define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT154_CONTROL 0x1c26b #define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT155_ADDR_LO 0x1c26c #define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT155_ADDR_HI 0x1c26d #define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT155_MSG_DATA 0x1c26e #define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT155_CONTROL 0x1c26f #define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT156_ADDR_LO 0x1c270 #define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT156_ADDR_HI 0x1c271 #define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT156_MSG_DATA 0x1c272 #define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT156_CONTROL 0x1c273 #define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT157_ADDR_LO 0x1c274 #define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT157_ADDR_HI 0x1c275 #define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT157_MSG_DATA 0x1c276 #define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT157_CONTROL 0x1c277 #define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT158_ADDR_LO 0x1c278 #define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT158_ADDR_HI 0x1c279 #define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT158_MSG_DATA 0x1c27a #define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT158_CONTROL 0x1c27b #define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT159_ADDR_LO 0x1c27c #define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT159_ADDR_HI 0x1c27d #define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT159_MSG_DATA 0x1c27e #define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT159_CONTROL 0x1c27f #define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT160_ADDR_LO 0x1c280 #define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT160_ADDR_HI 0x1c281 #define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT160_MSG_DATA 0x1c282 #define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT160_CONTROL 0x1c283 #define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT161_ADDR_LO 0x1c284 #define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT161_ADDR_HI 0x1c285 #define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT161_MSG_DATA 0x1c286 #define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT161_CONTROL 0x1c287 #define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT162_ADDR_LO 0x1c288 #define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT162_ADDR_HI 0x1c289 #define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT162_MSG_DATA 0x1c28a #define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT162_CONTROL 0x1c28b #define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT163_ADDR_LO 0x1c28c #define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT163_ADDR_HI 0x1c28d #define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT163_MSG_DATA 0x1c28e #define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT163_CONTROL 0x1c28f #define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT164_ADDR_LO 0x1c290 #define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT164_ADDR_HI 0x1c291 #define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT164_MSG_DATA 0x1c292 #define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT164_CONTROL 0x1c293 #define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT165_ADDR_LO 0x1c294 #define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT165_ADDR_HI 0x1c295 #define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT165_MSG_DATA 0x1c296 #define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT165_CONTROL 0x1c297 #define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT166_ADDR_LO 0x1c298 #define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT166_ADDR_HI 0x1c299 #define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT166_MSG_DATA 0x1c29a #define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT166_CONTROL 0x1c29b #define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT167_ADDR_LO 0x1c29c #define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT167_ADDR_HI 0x1c29d #define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT167_MSG_DATA 0x1c29e #define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT167_CONTROL 0x1c29f #define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT168_ADDR_LO 0x1c2a0 #define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT168_ADDR_HI 0x1c2a1 #define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT168_MSG_DATA 0x1c2a2 #define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT168_CONTROL 0x1c2a3 #define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT169_ADDR_LO 0x1c2a4 #define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT169_ADDR_HI 0x1c2a5 #define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT169_MSG_DATA 0x1c2a6 #define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT169_CONTROL 0x1c2a7 #define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT170_ADDR_LO 0x1c2a8 #define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT170_ADDR_HI 0x1c2a9 #define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT170_MSG_DATA 0x1c2aa #define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT170_CONTROL 0x1c2ab #define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT171_ADDR_LO 0x1c2ac #define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT171_ADDR_HI 0x1c2ad #define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT171_MSG_DATA 0x1c2ae #define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT171_CONTROL 0x1c2af #define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT172_ADDR_LO 0x1c2b0 #define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT172_ADDR_HI 0x1c2b1 #define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT172_MSG_DATA 0x1c2b2 #define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT172_CONTROL 0x1c2b3 #define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT173_ADDR_LO 0x1c2b4 #define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT173_ADDR_HI 0x1c2b5 #define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT173_MSG_DATA 0x1c2b6 #define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT173_CONTROL 0x1c2b7 #define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT174_ADDR_LO 0x1c2b8 #define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT174_ADDR_HI 0x1c2b9 #define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT174_MSG_DATA 0x1c2ba #define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT174_CONTROL 0x1c2bb #define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT175_ADDR_LO 0x1c2bc #define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT175_ADDR_HI 0x1c2bd #define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT175_MSG_DATA 0x1c2be #define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT175_CONTROL 0x1c2bf #define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT176_ADDR_LO 0x1c2c0 #define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT176_ADDR_HI 0x1c2c1 #define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT176_MSG_DATA 0x1c2c2 #define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT176_CONTROL 0x1c2c3 #define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT177_ADDR_LO 0x1c2c4 #define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT177_ADDR_HI 0x1c2c5 #define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT177_MSG_DATA 0x1c2c6 #define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT177_CONTROL 0x1c2c7 #define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT178_ADDR_LO 0x1c2c8 #define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT178_ADDR_HI 0x1c2c9 #define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT178_MSG_DATA 0x1c2ca #define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT178_CONTROL 0x1c2cb #define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT179_ADDR_LO 0x1c2cc #define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT179_ADDR_HI 0x1c2cd #define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT179_MSG_DATA 0x1c2ce #define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT179_CONTROL 0x1c2cf #define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT180_ADDR_LO 0x1c2d0 #define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT180_ADDR_HI 0x1c2d1 #define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT180_MSG_DATA 0x1c2d2 #define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT180_CONTROL 0x1c2d3 #define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT181_ADDR_LO 0x1c2d4 #define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT181_ADDR_HI 0x1c2d5 #define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT181_MSG_DATA 0x1c2d6 #define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT181_CONTROL 0x1c2d7 #define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT182_ADDR_LO 0x1c2d8 #define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT182_ADDR_HI 0x1c2d9 #define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT182_MSG_DATA 0x1c2da #define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT182_CONTROL 0x1c2db #define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT183_ADDR_LO 0x1c2dc #define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT183_ADDR_HI 0x1c2dd #define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT183_MSG_DATA 0x1c2de #define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT183_CONTROL 0x1c2df #define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT184_ADDR_LO 0x1c2e0 #define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT184_ADDR_HI 0x1c2e1 #define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT184_MSG_DATA 0x1c2e2 #define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT184_CONTROL 0x1c2e3 #define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT185_ADDR_LO 0x1c2e4 #define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT185_ADDR_HI 0x1c2e5 #define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT185_MSG_DATA 0x1c2e6 #define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT185_CONTROL 0x1c2e7 #define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT186_ADDR_LO 0x1c2e8 #define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT186_ADDR_HI 0x1c2e9 #define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT186_MSG_DATA 0x1c2ea #define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT186_CONTROL 0x1c2eb #define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT187_ADDR_LO 0x1c2ec #define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT187_ADDR_HI 0x1c2ed #define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT187_MSG_DATA 0x1c2ee #define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT187_CONTROL 0x1c2ef #define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT188_ADDR_LO 0x1c2f0 #define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT188_ADDR_HI 0x1c2f1 #define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT188_MSG_DATA 0x1c2f2 #define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT188_CONTROL 0x1c2f3 #define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT189_ADDR_LO 0x1c2f4 #define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT189_ADDR_HI 0x1c2f5 #define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT189_MSG_DATA 0x1c2f6 #define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT189_CONTROL 0x1c2f7 #define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT190_ADDR_LO 0x1c2f8 #define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT190_ADDR_HI 0x1c2f9 #define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT190_MSG_DATA 0x1c2fa #define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT190_CONTROL 0x1c2fb #define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT191_ADDR_LO 0x1c2fc #define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT191_ADDR_HI 0x1c2fd #define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT191_MSG_DATA 0x1c2fe #define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT191_CONTROL 0x1c2ff #define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT192_ADDR_LO 0x1c300 #define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT192_ADDR_HI 0x1c301 #define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT192_MSG_DATA 0x1c302 #define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT192_CONTROL 0x1c303 #define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT193_ADDR_LO 0x1c304 #define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT193_ADDR_HI 0x1c305 #define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT193_MSG_DATA 0x1c306 #define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT193_CONTROL 0x1c307 #define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT194_ADDR_LO 0x1c308 #define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT194_ADDR_HI 0x1c309 #define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT194_MSG_DATA 0x1c30a #define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT194_CONTROL 0x1c30b #define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT195_ADDR_LO 0x1c30c #define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT195_ADDR_HI 0x1c30d #define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT195_MSG_DATA 0x1c30e #define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT195_CONTROL 0x1c30f #define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT196_ADDR_LO 0x1c310 #define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT196_ADDR_HI 0x1c311 #define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT196_MSG_DATA 0x1c312 #define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT196_CONTROL 0x1c313 #define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT197_ADDR_LO 0x1c314 #define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT197_ADDR_HI 0x1c315 #define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT197_MSG_DATA 0x1c316 #define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT197_CONTROL 0x1c317 #define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT198_ADDR_LO 0x1c318 #define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT198_ADDR_HI 0x1c319 #define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT198_MSG_DATA 0x1c31a #define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT198_CONTROL 0x1c31b #define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT199_ADDR_LO 0x1c31c #define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT199_ADDR_HI 0x1c31d #define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT199_MSG_DATA 0x1c31e #define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT199_CONTROL 0x1c31f #define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT200_ADDR_LO 0x1c320 #define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT200_ADDR_HI 0x1c321 #define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT200_MSG_DATA 0x1c322 #define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT200_CONTROL 0x1c323 #define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT201_ADDR_LO 0x1c324 #define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT201_ADDR_HI 0x1c325 #define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT201_MSG_DATA 0x1c326 #define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT201_CONTROL 0x1c327 #define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT202_ADDR_LO 0x1c328 #define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT202_ADDR_HI 0x1c329 #define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT202_MSG_DATA 0x1c32a #define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT202_CONTROL 0x1c32b #define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT203_ADDR_LO 0x1c32c #define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT203_ADDR_HI 0x1c32d #define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT203_MSG_DATA 0x1c32e #define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT203_CONTROL 0x1c32f #define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT204_ADDR_LO 0x1c330 #define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT204_ADDR_HI 0x1c331 #define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT204_MSG_DATA 0x1c332 #define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT204_CONTROL 0x1c333 #define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT205_ADDR_LO 0x1c334 #define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT205_ADDR_HI 0x1c335 #define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT205_MSG_DATA 0x1c336 #define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT205_CONTROL 0x1c337 #define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT206_ADDR_LO 0x1c338 #define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT206_ADDR_HI 0x1c339 #define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT206_MSG_DATA 0x1c33a #define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT206_CONTROL 0x1c33b #define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT207_ADDR_LO 0x1c33c #define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT207_ADDR_HI 0x1c33d #define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT207_MSG_DATA 0x1c33e #define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT207_CONTROL 0x1c33f #define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT208_ADDR_LO 0x1c340 #define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT208_ADDR_HI 0x1c341 #define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT208_MSG_DATA 0x1c342 #define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT208_CONTROL 0x1c343 #define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT209_ADDR_LO 0x1c344 #define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT209_ADDR_HI 0x1c345 #define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT209_MSG_DATA 0x1c346 #define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT209_CONTROL 0x1c347 #define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT210_ADDR_LO 0x1c348 #define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT210_ADDR_HI 0x1c349 #define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT210_MSG_DATA 0x1c34a #define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT210_CONTROL 0x1c34b #define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT211_ADDR_LO 0x1c34c #define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT211_ADDR_HI 0x1c34d #define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT211_MSG_DATA 0x1c34e #define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT211_CONTROL 0x1c34f #define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT212_ADDR_LO 0x1c350 #define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT212_ADDR_HI 0x1c351 #define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT212_MSG_DATA 0x1c352 #define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT212_CONTROL 0x1c353 #define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT213_ADDR_LO 0x1c354 #define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT213_ADDR_HI 0x1c355 #define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT213_MSG_DATA 0x1c356 #define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT213_CONTROL 0x1c357 #define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT214_ADDR_LO 0x1c358 #define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT214_ADDR_HI 0x1c359 #define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT214_MSG_DATA 0x1c35a #define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT214_CONTROL 0x1c35b #define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT215_ADDR_LO 0x1c35c #define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT215_ADDR_HI 0x1c35d #define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT215_MSG_DATA 0x1c35e #define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT215_CONTROL 0x1c35f #define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT216_ADDR_LO 0x1c360 #define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT216_ADDR_HI 0x1c361 #define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT216_MSG_DATA 0x1c362 #define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT216_CONTROL 0x1c363 #define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT217_ADDR_LO 0x1c364 #define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT217_ADDR_HI 0x1c365 #define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT217_MSG_DATA 0x1c366 #define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT217_CONTROL 0x1c367 #define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT218_ADDR_LO 0x1c368 #define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT218_ADDR_HI 0x1c369 #define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT218_MSG_DATA 0x1c36a #define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT218_CONTROL 0x1c36b #define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT219_ADDR_LO 0x1c36c #define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT219_ADDR_HI 0x1c36d #define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT219_MSG_DATA 0x1c36e #define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT219_CONTROL 0x1c36f #define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT220_ADDR_LO 0x1c370 #define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT220_ADDR_HI 0x1c371 #define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT220_MSG_DATA 0x1c372 #define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT220_CONTROL 0x1c373 #define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT221_ADDR_LO 0x1c374 #define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT221_ADDR_HI 0x1c375 #define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT221_MSG_DATA 0x1c376 #define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT221_CONTROL 0x1c377 #define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT222_ADDR_LO 0x1c378 #define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT222_ADDR_HI 0x1c379 #define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT222_MSG_DATA 0x1c37a #define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT222_CONTROL 0x1c37b #define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT223_ADDR_LO 0x1c37c #define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT223_ADDR_HI 0x1c37d #define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT223_MSG_DATA 0x1c37e #define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT223_CONTROL 0x1c37f #define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT224_ADDR_LO 0x1c380 #define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT224_ADDR_HI 0x1c381 #define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT224_MSG_DATA 0x1c382 #define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT224_CONTROL 0x1c383 #define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT225_ADDR_LO 0x1c384 #define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT225_ADDR_HI 0x1c385 #define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT225_MSG_DATA 0x1c386 #define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT225_CONTROL 0x1c387 #define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT226_ADDR_LO 0x1c388 #define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT226_ADDR_HI 0x1c389 #define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT226_MSG_DATA 0x1c38a #define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT226_CONTROL 0x1c38b #define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT227_ADDR_LO 0x1c38c #define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT227_ADDR_HI 0x1c38d #define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT227_MSG_DATA 0x1c38e #define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT227_CONTROL 0x1c38f #define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT228_ADDR_LO 0x1c390 #define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT228_ADDR_HI 0x1c391 #define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT228_MSG_DATA 0x1c392 #define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT228_CONTROL 0x1c393 #define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT229_ADDR_LO 0x1c394 #define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT229_ADDR_HI 0x1c395 #define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT229_MSG_DATA 0x1c396 #define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT229_CONTROL 0x1c397 #define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT230_ADDR_LO 0x1c398 #define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT230_ADDR_HI 0x1c399 #define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT230_MSG_DATA 0x1c39a #define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT230_CONTROL 0x1c39b #define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT231_ADDR_LO 0x1c39c #define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT231_ADDR_HI 0x1c39d #define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT231_MSG_DATA 0x1c39e #define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT231_CONTROL 0x1c39f #define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT232_ADDR_LO 0x1c3a0 #define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT232_ADDR_HI 0x1c3a1 #define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT232_MSG_DATA 0x1c3a2 #define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT232_CONTROL 0x1c3a3 #define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT233_ADDR_LO 0x1c3a4 #define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT233_ADDR_HI 0x1c3a5 #define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT233_MSG_DATA 0x1c3a6 #define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT233_CONTROL 0x1c3a7 #define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT234_ADDR_LO 0x1c3a8 #define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT234_ADDR_HI 0x1c3a9 #define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT234_MSG_DATA 0x1c3aa #define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT234_CONTROL 0x1c3ab #define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT235_ADDR_LO 0x1c3ac #define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT235_ADDR_HI 0x1c3ad #define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT235_MSG_DATA 0x1c3ae #define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT235_CONTROL 0x1c3af #define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT236_ADDR_LO 0x1c3b0 #define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT236_ADDR_HI 0x1c3b1 #define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT236_MSG_DATA 0x1c3b2 #define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT236_CONTROL 0x1c3b3 #define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT237_ADDR_LO 0x1c3b4 #define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT237_ADDR_HI 0x1c3b5 #define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT237_MSG_DATA 0x1c3b6 #define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT237_CONTROL 0x1c3b7 #define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT238_ADDR_LO 0x1c3b8 #define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT238_ADDR_HI 0x1c3b9 #define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT238_MSG_DATA 0x1c3ba #define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT238_CONTROL 0x1c3bb #define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT239_ADDR_LO 0x1c3bc #define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT239_ADDR_HI 0x1c3bd #define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT239_MSG_DATA 0x1c3be #define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT239_CONTROL 0x1c3bf #define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT240_ADDR_LO 0x1c3c0 #define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT240_ADDR_HI 0x1c3c1 #define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT240_MSG_DATA 0x1c3c2 #define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT240_CONTROL 0x1c3c3 #define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT241_ADDR_LO 0x1c3c4 #define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT241_ADDR_HI 0x1c3c5 #define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT241_MSG_DATA 0x1c3c6 #define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT241_CONTROL 0x1c3c7 #define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT242_ADDR_LO 0x1c3c8 #define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT242_ADDR_HI 0x1c3c9 #define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT242_MSG_DATA 0x1c3ca #define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT242_CONTROL 0x1c3cb #define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT243_ADDR_LO 0x1c3cc #define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT243_ADDR_HI 0x1c3cd #define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT243_MSG_DATA 0x1c3ce #define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT243_CONTROL 0x1c3cf #define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT244_ADDR_LO 0x1c3d0 #define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT244_ADDR_HI 0x1c3d1 #define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT244_MSG_DATA 0x1c3d2 #define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT244_CONTROL 0x1c3d3 #define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT245_ADDR_LO 0x1c3d4 #define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT245_ADDR_HI 0x1c3d5 #define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT245_MSG_DATA 0x1c3d6 #define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT245_CONTROL 0x1c3d7 #define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT246_ADDR_LO 0x1c3d8 #define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT246_ADDR_HI 0x1c3d9 #define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT246_MSG_DATA 0x1c3da #define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT246_CONTROL 0x1c3db #define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT247_ADDR_LO 0x1c3dc #define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT247_ADDR_HI 0x1c3dd #define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT247_MSG_DATA 0x1c3de #define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT247_CONTROL 0x1c3df #define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT248_ADDR_LO 0x1c3e0 #define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT248_ADDR_HI 0x1c3e1 #define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT248_MSG_DATA 0x1c3e2 #define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT248_CONTROL 0x1c3e3 #define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT249_ADDR_LO 0x1c3e4 #define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT249_ADDR_HI 0x1c3e5 #define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT249_MSG_DATA 0x1c3e6 #define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT249_CONTROL 0x1c3e7 #define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT250_ADDR_LO 0x1c3e8 #define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT250_ADDR_HI 0x1c3e9 #define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT250_MSG_DATA 0x1c3ea #define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT250_CONTROL 0x1c3eb #define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT251_ADDR_LO 0x1c3ec #define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT251_ADDR_HI 0x1c3ed #define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT251_MSG_DATA 0x1c3ee #define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT251_CONTROL 0x1c3ef #define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT252_ADDR_LO 0x1c3f0 #define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT252_ADDR_HI 0x1c3f1 #define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT252_MSG_DATA 0x1c3f2 #define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT252_CONTROL 0x1c3f3 #define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT253_ADDR_LO 0x1c3f4 #define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT253_ADDR_HI 0x1c3f5 #define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT253_MSG_DATA 0x1c3f6 #define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT253_CONTROL 0x1c3f7 #define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT254_ADDR_LO 0x1c3f8 #define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT254_ADDR_HI 0x1c3f9 #define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT254_MSG_DATA 0x1c3fa #define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT254_CONTROL 0x1c3fb #define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 5 #define regPCIEMSIX_VECT255_ADDR_LO 0x1c3fc #define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 5 #define regPCIEMSIX_VECT255_ADDR_HI 0x1c3fd #define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 5 #define regPCIEMSIX_VECT255_MSG_DATA 0x1c3fe #define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 5 #define regPCIEMSIX_VECT255_CONTROL 0x1c3ff #define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 5 // base address: 0x10171000 #define regPCIEMSIX_PBA_0 0x1c400 #define regPCIEMSIX_PBA_0_BASE_IDX 5 #define regPCIEMSIX_PBA_1 0x1c401 #define regPCIEMSIX_PBA_1_BASE_IDX 5 #define regPCIEMSIX_PBA_2 0x1c402 #define regPCIEMSIX_PBA_2_BASE_IDX 5 #define regPCIEMSIX_PBA_3 0x1c403 #define regPCIEMSIX_PBA_3_BASE_IDX 5 #define regPCIEMSIX_PBA_4 0x1c404 #define regPCIEMSIX_PBA_4_BASE_IDX 5 #define regPCIEMSIX_PBA_5 0x1c405 #define regPCIEMSIX_PBA_5_BASE_IDX 5 #define regPCIEMSIX_PBA_6 0x1c406 #define regPCIEMSIX_PBA_6_BASE_IDX 5 #define regPCIEMSIX_PBA_7 0x1c407 #define regPCIEMSIX_PBA_7_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec // base address: 0x10130000 #define regSHADOW_COMMAND 0xc001 #define regSHADOW_COMMAND_BASE_IDX 5 #define regSHADOW_BASE_ADDR_1 0xc004 #define regSHADOW_BASE_ADDR_1_BASE_IDX 5 #define regSHADOW_BASE_ADDR_2 0xc005 #define regSHADOW_BASE_ADDR_2_BASE_IDX 5 #define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006 #define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 #define regSHADOW_IO_BASE_LIMIT 0xc007 #define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5 #define regSHADOW_MEM_BASE_LIMIT 0xc008 #define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5 #define regSHADOW_PREF_BASE_LIMIT 0xc009 #define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5 #define regSHADOW_PREF_BASE_UPPER 0xc00a #define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5 #define regSHADOW_PREF_LIMIT_UPPER 0xc00b #define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5 #define regSHADOW_IO_BASE_LIMIT_HI 0xc00c #define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5 #define regSUC_INDEX 0xc038 #define regSUC_INDEX_BASE_IDX 5 #define regSUC_DATA 0xc039 #define regSUC_DATA_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_swus_SUMDEC // base address: 0x1013b000 #define regSUM_INDEX 0xec38 #define regSUM_INDEX_BASE_IDX 5 #define regSUM_DATA 0xec39 #define regSUM_DATA_BASE_IDX 5 #define regSUM_INDEX_HI 0xec3b #define regSUM_INDEX_HI_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal // base address: 0x10100000 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP0 0xc480 #define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP1 0xc481 #define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP2 0xc482 #define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP3 0xc483 #define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP4 0xc484 #define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP5 0xc485 #define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP6 0xc486 #define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP7 0xc487 #define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP8 0xc488 #define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP9 0xc489 #define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP10 0xc48a #define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP11 0xc48b #define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP12 0xc48c #define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP13 0xc48d #define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 #define regRCC_DEV1_PORT_STRAP14 0xc48e #define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP0 0xc500 #define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP1 0xc501 #define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP2 0xc502 #define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP3 0xc503 #define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP4 0xc504 #define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP5 0xc505 #define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP6 0xc506 #define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP7 0xc507 #define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP8 0xc508 #define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP9 0xc509 #define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP10 0xc50a #define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP11 0xc50b #define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP12 0xc50c #define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP13 0xc50d #define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 #define regRCC_DEV2_PORT_STRAP14 0xc50e #define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 #define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 #define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 #define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 #define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 #define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 #define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 #define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 #define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP0 0xd100 #define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP2 0xd102 #define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP3 0xd103 #define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP4 0xd104 #define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP5 0xd105 #define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP6 0xd106 #define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP7 0xd107 #define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP10 0xd10a #define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP11 0xd10b #define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP12 0xd10c #define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP13 0xd10d #define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP14 0xd10e #define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 #define regRCC_DEV0_EPF2_STRAP20 0xd114 #define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP0 0xd180 #define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP2 0xd182 #define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP3 0xd183 #define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP4 0xd184 #define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP5 0xd185 #define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP6 0xd186 #define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP7 0xd187 #define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP10 0xd18a #define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP11 0xd18b #define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP12 0xd18c #define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP13 0xd18d #define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP14 0xd18e #define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 #define regRCC_DEV0_EPF3_STRAP20 0xd194 #define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP0 0xd200 #define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP2 0xd202 #define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP3 0xd203 #define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP4 0xd204 #define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP5 0xd205 #define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP6 0xd206 #define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP7 0xd207 #define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP13 0xd20d #define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF4_STRAP14 0xd20e #define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP0 0xd280 #define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP2 0xd282 #define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP3 0xd283 #define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP4 0xd284 #define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP5 0xd285 #define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP6 0xd286 #define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP7 0xd287 #define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP13 0xd28d #define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF5_STRAP14 0xd28e #define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP0 0xd300 #define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP2 0xd302 #define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP3 0xd303 #define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP4 0xd304 #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP5 0xd305 #define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP6 0xd306 #define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP13 0xd30d #define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF6_STRAP14 0xd30e #define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP0 0xd380 #define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP2 0xd382 #define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP3 0xd383 #define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP4 0xd384 #define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP5 0xd385 #define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP6 0xd386 #define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP7 0xd387 #define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP13 0xd38d #define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 #define regRCC_DEV0_EPF7_STRAP14 0xd38e #define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP0 0xd400 #define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP2 0xd402 #define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP3 0xd403 #define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP4 0xd404 #define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP5 0xd405 #define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP6 0xd406 #define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP7 0xd407 #define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP13 0xd40d #define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF0_STRAP14 0xd40e #define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP0 0xd480 #define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP2 0xd482 #define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP3 0xd483 #define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP4 0xd484 #define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP5 0xd485 #define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP6 0xd486 #define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP7 0xd487 #define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP13 0xd48d #define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF1_STRAP14 0xd48e #define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP0 0xd500 #define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP2 0xd502 #define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP3 0xd503 #define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP4 0xd504 #define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP5 0xd505 #define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP6 0xd506 #define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP13 0xd50d #define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF2_STRAP14 0xd50e #define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP0 0xd580 #define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP2 0xd582 #define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP3 0xd583 #define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP4 0xd584 #define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP5 0xd585 #define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP6 0xd586 #define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP13 0xd58d #define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF3_STRAP14 0xd58e #define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP0 0xd600 #define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP2 0xd602 #define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP3 0xd603 #define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP4 0xd604 #define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP5 0xd605 #define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP6 0xd606 #define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP13 0xd60d #define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF4_STRAP14 0xd60e #define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP0 0xd680 #define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP2 0xd682 #define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP3 0xd683 #define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP4 0xd684 #define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP5 0xd685 #define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP6 0xd686 #define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP13 0xd68d #define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5 #define regRCC_DEV1_EPF5_STRAP14 0xd68e #define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP0 0xd800 #define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP2 0xd802 #define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP3 0xd803 #define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP4 0xd804 #define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP5 0xd805 #define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP6 0xd806 #define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP7 0xd807 #define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP13 0xd80d #define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 #define regRCC_DEV2_EPF0_STRAP14 0xd80e #define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP0 0xd880 #define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP2 0xd882 #define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP3 0xd883 #define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP4 0xd884 #define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP5 0xd885 #define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP6 0xd886 #define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP13 0xd88d #define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 #define regRCC_DEV2_EPF1_STRAP14 0xd88e #define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP0 0xd900 #define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP2 0xd902 #define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP3 0xd903 #define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP4 0xd904 #define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP5 0xd905 #define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP6 0xd906 #define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP13 0xd90d #define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 #define regRCC_DEV2_EPF2_STRAP14 0xd90e #define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk // base address: 0x10100000 #define regHARD_RST_CTRL 0xe000 #define regHARD_RST_CTRL_BASE_IDX 5 #define regSELF_SOFT_RST 0xe002 #define regSELF_SOFT_RST_BASE_IDX 5 #define regBIF_GFX_DRV_VPU_RST 0xe003 #define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 #define regBIF_RST_MISC_CTRL 0xe004 #define regBIF_RST_MISC_CTRL_BASE_IDX 5 #define regBIF_RST_MISC_CTRL2 0xe005 #define regBIF_RST_MISC_CTRL2_BASE_IDX 5 #define regBIF_RST_MISC_CTRL3 0xe006 #define regBIF_RST_MISC_CTRL3_BASE_IDX 5 #define regDEV0_PF0_FLR_RST_CTRL 0xe008 #define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 #define regDEV0_PF1_FLR_RST_CTRL 0xe009 #define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 #define regDEV0_PF2_FLR_RST_CTRL 0xe00a #define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5 #define regDEV0_PF3_FLR_RST_CTRL 0xe00b #define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5 #define regBIF_INST_RESET_INTR_STS 0xe010 #define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 #define regBIF_PF_FLR_INTR_STS 0xe011 #define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 #define regBIF_D3HOTD0_INTR_STS 0xe012 #define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 #define regBIF_POWER_INTR_STS 0xe014 #define regBIF_POWER_INTR_STS_BASE_IDX 5 #define regBIF_PF_DSTATE_INTR_STS 0xe015 #define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 #define regSELF_SOFT_RST_2 0xe016 #define regSELF_SOFT_RST_2_BASE_IDX 5 #define regBIF_INST_RESET_INTR_MASK 0xe020 #define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 #define regBIF_PF_FLR_INTR_MASK 0xe021 #define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 #define regBIF_D3HOTD0_INTR_MASK 0xe022 #define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 #define regBIF_POWER_INTR_MASK 0xe024 #define regBIF_POWER_INTR_MASK_BASE_IDX 5 #define regBIF_PF_DSTATE_INTR_MASK 0xe025 #define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 #define regBIF_PF_FLR_RST 0xe040 #define regBIF_PF_FLR_RST_BASE_IDX 5 #define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 #define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 #define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 #define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 #define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052 #define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5 #define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053 #define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5 #define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 #define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 #define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 #define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 #define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a #define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 #define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b #define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 #define regBIF_PORT0_DSTATE_VALUE 0xe230 #define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk // base address: 0x10100000 #define regREGS_ROM_OFFSET_CTRL 0xcc23 #define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 #define regNBIF_STRAP_BIOS_CNTL 0xcc81 #define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 #define regMISC_SCRATCH 0xe800 #define regMISC_SCRATCH_BASE_IDX 5 #define regINTR_LINE_POLARITY 0xe801 #define regINTR_LINE_POLARITY_BASE_IDX 5 #define regINTR_LINE_ENABLE 0xe802 #define regINTR_LINE_ENABLE_BASE_IDX 5 #define regOUTSTANDING_VC_ALLOC 0xe803 #define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 #define regBIFC_MISC_CTRL0 0xe804 #define regBIFC_MISC_CTRL0_BASE_IDX 5 #define regBIFC_MISC_CTRL1 0xe805 #define regBIFC_MISC_CTRL1_BASE_IDX 5 #define regBIFC_BME_ERR_LOG_LB 0xe806 #define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 #define regBIFC_LC_TIMER_CTRL 0xe807 #define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 #define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 #define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 #define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a #define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 #define regBME_DUMMY_CNTL_0 0xe825 #define regBME_DUMMY_CNTL_0_BASE_IDX 5 #define regBIFC_HSTARB_CNTL 0xe828 #define regBIFC_HSTARB_CNTL_BASE_IDX 5 #define regBIFC_GSI_CNTL 0xe829 #define regBIFC_GSI_CNTL_BASE_IDX 5 #define regBIFC_PCIEFUNC_CNTL 0xe82a #define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 #define regBIFC_PASID_CHECK_DIS 0xe82b #define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 #define regBIFC_SDP_CNTL_0 0xe82c #define regBIFC_SDP_CNTL_0_BASE_IDX 5 #define regBIFC_SDP_CNTL_1 0xe82d #define regBIFC_SDP_CNTL_1_BASE_IDX 5 #define regBIFC_PASID_STS 0xe82e #define regBIFC_PASID_STS_BASE_IDX 5 #define regBIFC_ATHUB_ACT_CNTL 0xe82f #define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 #define regBIFC_PERF_CNTL_0 0xe830 #define regBIFC_PERF_CNTL_0_BASE_IDX 5 #define regBIFC_PERF_CNTL_1 0xe831 #define regBIFC_PERF_CNTL_1_BASE_IDX 5 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 #define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 #define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 #define regNBIF_REGIF_ERRSET_CTRL 0xe836 #define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 #define regBIFC_SDP_CNTL_2 0xe837 #define regBIFC_SDP_CNTL_2_BASE_IDX 5 #define regNBIF_PGMST_CTRL 0xe838 #define regNBIF_PGMST_CTRL_BASE_IDX 5 #define regNBIF_PGSLV_CTRL 0xe839 #define regNBIF_PGSLV_CTRL_BASE_IDX 5 #define regNBIF_PG_MISC_CTRL 0xe83a #define regNBIF_PG_MISC_CTRL_BASE_IDX 5 #define regSMN_MST_EP_CNTL3 0xe83c #define regSMN_MST_EP_CNTL3_BASE_IDX 5 #define regSMN_MST_EP_CNTL4 0xe83d #define regSMN_MST_EP_CNTL4_BASE_IDX 5 #define regSMN_MST_CNTL1 0xe83e #define regSMN_MST_CNTL1_BASE_IDX 5 #define regSMN_MST_EP_CNTL5 0xe83f #define regSMN_MST_EP_CNTL5_BASE_IDX 5 #define regBIF_SELFRING_BUFFER_VID 0xe840 #define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 #define regBIF_SELFRING_VECTOR_CNTL 0xe841 #define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 #define regNBIF_STRAP_WRITE_CTRL 0xe845 #define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 #define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 #define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 #define regNBIF_PENDING_MISC_CNTL 0xe847 #define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 #define regBIF_GMI_WRR_WEIGHT 0xe848 #define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 #define regBIF_GMI_WRR_WEIGHT2 0xe849 #define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 #define regBIF_GMI_WRR_WEIGHT3 0xe84a #define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 #define regNBIF_PWRBRK_REQUEST 0xe84c #define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852 #define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853 #define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5 #define regBIF_DMA_MP4_ERR_LOG 0xe870 #define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 #define regBIF_PASID_ERR_LOG 0xe871 #define regBIF_PASID_ERR_LOG_BASE_IDX 5 #define regBIF_PASID_ERR_CLR 0xe872 #define regBIF_PASID_ERR_CLR_BASE_IDX 5 #define regNBIF_VWIRE_CTRL 0xe880 #define regNBIF_VWIRE_CTRL_BASE_IDX 5 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5 #define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 #define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5 #define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 #define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5 #define regNBIF_MGCG_CTRL_LCLK 0xe887 #define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 #define regNBIF_DS_CTRL_LCLK 0xe888 #define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 #define regSMN_MST_CNTL0 0xe889 #define regSMN_MST_CNTL0_BASE_IDX 5 #define regSMN_MST_EP_CNTL1 0xe88a #define regSMN_MST_EP_CNTL1_BASE_IDX 5 #define regSMN_MST_EP_CNTL2 0xe88b #define regSMN_MST_EP_CNTL2_BASE_IDX 5 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c #define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e #define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 #define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f #define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 #define regNBIF_SHUB_TODET_CTRL 0xe898 #define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 #define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 #define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 #define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a #define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 #define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c #define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 #define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d #define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 #define regBIFC_BME_ERR_LOG_HB 0xe8ab #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 #define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 #define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 #define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 #define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 #define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 #define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 #define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_misc_pfvf_bif_misc_pfvf_regblk // base address: 0x10100000 // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk // base address: 0x10100000 #define regBIFL_RAS_CENTRAL_CNTL 0xe400 #define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 #define regBIFL_RAS_CENTRAL_STATUS 0xe410 #define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 #define regBIFL_RAS_LEAF0_CTRL 0xe420 #define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 #define regBIFL_RAS_LEAF1_CTRL 0xe421 #define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 #define regBIFL_RAS_LEAF2_CTRL 0xe422 #define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 #define regBIFL_RAS_LEAF3_CTRL 0xe423 #define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 #define regBIFL_RAS_LEAF0_STATUS 0xe430 #define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 #define regBIFL_RAS_LEAF1_STATUS 0xe431 #define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 #define regBIFL_RAS_LEAF2_STATUS 0xe432 #define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 #define regBIFL_RAS_LEAF3_STATUS 0xe433 #define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 #define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe #define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 #define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff #define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 // base address: 0x10120000 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 // base address: 0x10120000 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 // base address: 0x10120000 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 // base address: 0x10120000 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 #define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 #define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 #define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 #define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 #define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac #define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 #define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 #define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 #define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 #define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 #define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 #define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea #define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded #define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee #define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 #define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 #define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_bx_SYSDEC // base address: 0x10120000 #define regBIF_BX1_PCIE_INDEX 0x800c #define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 #define regBIF_BX1_PCIE_DATA 0x800d #define regBIF_BX1_PCIE_DATA_BASE_IDX 5 #define regBIF_BX1_PCIE_INDEX2 0x800e #define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 #define regBIF_BX1_PCIE_DATA2 0x800f #define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 #define regBIF_BX1_PCIE_INDEX_HI 0x8010 #define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 #define regBIF_BX1_PCIE_INDEX2_HI 0x8011 #define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 #define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 #define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_2 0x804a #define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_3 0x804b #define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_0 0x804c #define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_1 0x804d #define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_2 0x804e #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_3 0x804f #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_4 0x8050 #define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_5 0x8051 #define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_6 0x8052 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_7 0x8053 #define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_8 0x8054 #define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_9 0x8055 #define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_10 0x8056 #define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_11 0x8057 #define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_12 0x8058 #define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_13 0x8059 #define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_14 0x805a #define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 #define regBIF_BX1_BIOS_SCRATCH_15 0x805b #define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 #define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 #define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 #define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 #define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 #define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 #define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 #define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 #define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 #define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 #define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_6 0x809a #define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_7 0x809b #define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_8 0x809c #define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_9 0x809d #define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_10 0x809e #define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_11 0x809f #define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 #define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 #define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 #define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 #define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 #define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_0 0x80a4 #define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_1 0x80a5 #define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_2 0x80a6 #define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_3 0x80a7 #define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_4 0x80a8 #define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_5 0x80a9 #define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_6 0x80aa #define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_7 0x80ab #define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_8 0x80ac #define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_9 0x80ad #define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_10 0x80ae #define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_11 0x80af #define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_12 0x80b0 #define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_13 0x80b1 #define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_14 0x80b2 #define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 #define regBIF_BX1_FW_SCRATCH_15 0x80b3 #define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 #define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 #define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 #define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 #define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 #define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 #define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba #define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb #define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc #define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd #define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_14 0x80be #define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 #define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf #define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC // base address: 0x10120000 #define regBIF_BX_PF1_MM_INDEX 0x8000 #define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 #define regBIF_BX_PF1_MM_DATA 0x8001 #define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 #define regBIF_BX_PF1_MM_INDEX_HI 0x8006 #define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 // base address: 0x10120000 #define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 #define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 #define regBIF_BX1_BUS_CNTL 0x8e07 #define regBIF_BX1_BUS_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_SCRATCH0 0x8e08 #define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 #define regBIF_BX1_BIF_SCRATCH1 0x8e09 #define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 #define regBIF_BX1_BX_RESET_EN 0x8e0d #define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 #define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 #define regBIF_BX1_BX_RESET_CNTL 0x8e10 #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 #define regBIF_BX1_INTERRUPT_CNTL 0x8e11 #define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 #define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 #define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 #define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 #define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d #define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e #define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_FB_EN 0x8e20 #define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 #define regBIF_BX1_BIF_INTR_CNTL 0x8e21 #define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 #define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 #define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 #define regBIF_BX1_VF_REGWR_EN 0x8e44 #define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 #define regBIF_BX1_VF_DOORBELL_EN 0x8e45 #define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 #define regBIF_BX1_VF_FB_EN 0x8e46 #define regBIF_BX1_VF_FB_EN_BASE_IDX 5 #define regBIF_BX1_VF_REGWR_STATUS 0x8e47 #define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 #define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 #define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 #define regBIF_BX1_VF_FB_STATUS 0x8e49 #define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_RB_CNTL 0x8e4f #define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_RB_BASE 0x8e50 #define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 #define regBIF_BX1_BIF_RB_RPTR 0x8e51 #define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 #define regBIF_BX1_BIF_RB_WPTR 0x8e52 #define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 #define regBIF_BX1_MAILBOX_INDEX 0x8e55 #define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 #define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 #define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e63 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 5 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e64 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 5 #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x8e65 #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 5 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e68 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e69 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e6a #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e6b #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6c #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_WAKEB_PAD_CNTL 0x8e6d #define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0x8e6e #define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 5 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0x8e70 #define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX 5 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0x8e71 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX 5 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0x8e72 #define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX 5 #define regBIF_BX1_BIF_S5_DUMMY_REGS 0x8e73 #define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 // base address: 0x10120000 #define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b #define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 #define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 #define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e #define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 #define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f #define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 // base address: 0x10120000 #define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 #define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 #define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 #define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 #define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 #define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 #define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 #define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 #define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d43 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d44 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d45 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d51 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d52 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d53 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d54 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d55 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d56 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d57 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d58 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d59 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5a #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5b #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5c #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 // addressBlock: nbio_nbif0_gdc_dma_sion_SIONDEC // base address: 0x1400000 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 #define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 #define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 #define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 #define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 #define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b #define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d #define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f #define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 #define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 #define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 #define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 #define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 #define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b #define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d #define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f #define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 #define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 #define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 #define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 #define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 #define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b #define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d #define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f #define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 #define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 #define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 #define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 #define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 #define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b #define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0 0x4f743c #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1 0x4f743d #define regGDC_DMA_SION_CL3_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0 0x4f743e #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1 0x4f743f #define regGDC_DMA_SION_CL3_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0 0x4f7440 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1 0x4f7441 #define regGDC_DMA_SION_CL3_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0 0x4f7442 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1 0x4f7443 #define regGDC_DMA_SION_CL3_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0 0x4f7444 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1 0x4f7445 #define regGDC_DMA_SION_CL3_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0 0x4f7446 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1 0x4f7447 #define regGDC_DMA_SION_CL3_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0 0x4f7448 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1 0x4f7449 #define regGDC_DMA_SION_CL3_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0 0x4f744a #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1 0x4f744b #define regGDC_DMA_SION_CL3_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0 0x4f744c #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1 0x4f744d #define regGDC_DMA_SION_CL3_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0 0x4f744e #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1 0x4f744f #define regGDC_DMA_SION_CL3_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_DMA_SION_CNTL_REG0 0x4f7450 #define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 #define regGDC_DMA_SION_CNTL_REG1 0x4f7451 #define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 // addressBlock: nbio_nbif0_gdc_hst_sion_SIONDEC // base address: 0x1400000 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 #define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 #define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 #define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 #define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 #define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a #define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b #define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d #define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f #define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 #define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 #define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 #define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 #define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 #define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b #define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c #define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d #define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e #define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f #define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 #define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 #define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 #define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 #define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7628 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7629 #define regGDC_HST_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0 0x4f762a #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1 0x4f762b #define regGDC_HST_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0 0x4f762c #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1 0x4f762d #define regGDC_HST_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0 0x4f762e #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1 0x4f762f #define regGDC_HST_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG0 0x4f7630 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG1 0x4f7631 #define regGDC_HST_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG0 0x4f7632 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG1 0x4f7633 #define regGDC_HST_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7634 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7635 #define regGDC_HST_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7636 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7637 #define regGDC_HST_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7638 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7639 #define regGDC_HST_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f763a #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f763b #define regGDC_HST_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 #define regGDC_HST_SION_CNTL_REG0 0x4f763c #define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 #define regGDC_HST_SION_CNTL_REG1 0x4f763d #define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_0_CTRL 0x4f7640 #define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_1_CTRL 0x4f7641 #define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_2_CTRL 0x4f7642 #define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_3_CTRL 0x4f7643 #define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_4_CTRL 0x4f7644 #define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_5_CTRL 0x4f7645 #define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_6_CTRL 0x4f7646 #define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_7_CTRL 0x4f7647 #define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_8_CTRL 0x4f7648 #define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_9_CTRL 0x4f7649 #define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_10_CTRL 0x4f764a #define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_11_CTRL 0x4f764b #define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_12_CTRL 0x4f764c #define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_13_CTRL 0x4f764d #define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_14_CTRL 0x4f764e #define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_ENTRY_15_CTRL 0x4f764f #define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 #define regS2A_DOORBELL_COMMON_CTRL_REG 0x4f7650 #define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 // addressBlock: nbio_nbif0_gdc_GDCDEC // base address: 0x1400000 #define regGDC1_SHUB_REGS_IF_CTL 0x4f0ae3 #define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 #define regGDC1_NGDC_MGCG_CTRL 0x4f0aea #define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 #define regGDC1_NGDC_RESERVED_0 0x4f0aeb #define regGDC1_NGDC_RESERVED_0_BASE_IDX 3 #define regGDC1_NGDC_RESERVED_1 0x4f0aec #define regGDC1_NGDC_RESERVED_1_BASE_IDX 3 #define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x4f0aef #define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 #define regGDC1_ATDMA_MISC_CNTL 0x4f0afd #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 3 #define regGDC1_S2A_MISC_CNTL 0x4f0aff #define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0b01 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 #define regGDC1_NGDC_PG_MISC_CTRL 0x4f0b18 #define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 3 #define regGDC1_NGDC_PGMST_CTRL 0x4f0b19 #define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 3 #define regGDC1_NGDC_PGSLV_CTRL 0x4f0b1a #define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 3 // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk // base address: 0x1400000 #define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 #define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 #define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 #define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 #define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 #define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 #define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 #define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 #define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 #define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF2_MISC_CTRL 0x4f5c2e #define regGDCSOC_RAS_LEAF2_MISC_CTRL_BASE_IDX 3 #define regGDCSOC_RAS_LEAF2_MISC_CTRL2 0x4f5c2f #define regGDCSOC_RAS_LEAF2_MISC_CTRL2_BASE_IDX 3 #define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 #define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 #define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 #define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 #define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 #define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 #define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 #define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 #define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 #define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC // base address: 0x1400000 #define regSHUB_PF_FLR_RST 0x4f7800 #define regSHUB_PF_FLR_RST_BASE_IDX 3 #define regSHUB_GFX_DRV_VPU_RST 0x4f7801 #define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 #define regSHUB_LINK_RESET 0x4f7802 #define regSHUB_LINK_RESET_BASE_IDX 3 #define regSHUB_HARD_RST_CTRL 0x4f7810 #define regSHUB_HARD_RST_CTRL_BASE_IDX 3 #define regSHUB_SOFT_RST_CTRL 0x4f7811 #define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 #define regSHUB_SDP_PORT_RST 0x4f7812 #define regSHUB_SDP_PORT_RST_BASE_IDX 3 #define regSHUB_RST_MISC_TRL 0x4f7813 #define regSHUB_RST_MISC_TRL_BASE_IDX 3 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect // base address: 0x1400000 #define regHST_CLK0_SW0_CL0_CNTL 0x4f3d40 #define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 3 #define regHST_CLK0_SW1_CL0_CNTL 0x4f3d60 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 3 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp // base address: 0x0 #define cfgPSWUSCFG0_1_VENDOR_ID 0x0000 #define cfgPSWUSCFG0_1_DEVICE_ID 0x0002 #define cfgPSWUSCFG0_1_COMMAND 0x0004 #define cfgPSWUSCFG0_1_STATUS 0x0006 #define cfgPSWUSCFG0_1_REVISION_ID 0x0008 #define cfgPSWUSCFG0_1_PROG_INTERFACE 0x0009 #define cfgPSWUSCFG0_1_SUB_CLASS 0x000a #define cfgPSWUSCFG0_1_BASE_CLASS 0x000b #define cfgPSWUSCFG0_1_CACHE_LINE 0x000c #define cfgPSWUSCFG0_1_LATENCY 0x000d #define cfgPSWUSCFG0_1_HEADER 0x000e #define cfgPSWUSCFG0_1_BIST 0x000f #define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0x0018 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0x001c #define cfgPSWUSCFG0_1_SECONDARY_STATUS 0x001e #define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0x0020 #define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0x0024 #define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0x0028 #define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0x002c #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0x0030 #define cfgPSWUSCFG0_1_CAP_PTR 0x0034 #define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0x0038 #define cfgPSWUSCFG0_1_INTERRUPT_LINE 0x003c #define cfgPSWUSCFG0_1_INTERRUPT_PIN 0x003d #define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0x0048 #define cfgPSWUSCFG0_1_ADAPTER_ID_W 0x004c #define cfgPSWUSCFG0_1_PMI_CAP_LIST 0x0050 #define cfgPSWUSCFG0_1_PMI_CAP 0x0052 #define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0x0054 #define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0x0058 #define cfgPSWUSCFG0_1_PCIE_CAP 0x005a #define cfgPSWUSCFG0_1_DEVICE_CAP 0x005c #define cfgPSWUSCFG0_1_DEVICE_CNTL 0x0060 #define cfgPSWUSCFG0_1_DEVICE_STATUS 0x0062 #define cfgPSWUSCFG0_1_LINK_CAP 0x0064 #define cfgPSWUSCFG0_1_LINK_CNTL 0x0068 #define cfgPSWUSCFG0_1_LINK_STATUS 0x006a #define cfgPSWUSCFG0_1_DEVICE_CAP2 0x007c #define cfgPSWUSCFG0_1_DEVICE_CNTL2 0x0080 #define cfgPSWUSCFG0_1_DEVICE_STATUS2 0x0082 #define cfgPSWUSCFG0_1_LINK_CAP2 0x0084 #define cfgPSWUSCFG0_1_LINK_CNTL2 0x0088 #define cfgPSWUSCFG0_1_LINK_STATUS2 0x008a #define cfgPSWUSCFG0_1_MSI_CAP_LIST 0x00a0 #define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0x00a2 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgPSWUSCFG0_1_MSI_MSG_DATA 0x00a8 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0x00ac #define cfgPSWUSCFG0_1_SSID_CAP_LIST 0x00c0 #define cfgPSWUSCFG0_1_SSID_CAP 0x00c4 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0x011c #define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0x011e #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0x016c #define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0x0170 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0x0174 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0x0178 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0x0274 #define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0x02a4 #define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0x02a6 #define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgPSWUSCFG0_1_PCIE_MC_CAP 0x02f4 #define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0x02f6 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0x02f8 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0x02fc #define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0x0300 #define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0x0304 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0x030c #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0x0324 #define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0x032c #define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0x032e #define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0x0404 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgPSWUSCFG0_1_LINK_CAP_16GT 0x0414 #define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0x0418 #define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0x041c #define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0440 #define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0x0444 #define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0x0446 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0x0448 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0x044a #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0x044c #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0x044e #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0x0450 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0x0452 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0x0454 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0x0456 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0x0458 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0x045a #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0x045c #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0x045e #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0x0460 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0x0462 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0x0464 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0x0466 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0x0468 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0x046a #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0x046c #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0x046e #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0x0470 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0x0472 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0x0474 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0x0476 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0x0478 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0x047a #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0x047c #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0x047e #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0x0480 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0x0482 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0x0484 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0x0486 #define cfgPSWUSCFG0_1_LINK_CAP_32GT 0x0504 #define cfgPSWUSCFG0_1_LINK_CNTL_32GT 0x0508 #define cfgPSWUSCFG0_1_LINK_STATUS_32GT 0x050c // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_RC1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_RC1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_RC1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_RC1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_RC1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_RC1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_RC1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_RC1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_RC1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_RC1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_RC1_HEADER 0x000e #define cfgBIF_CFG_DEV0_RC1_BIST 0x000f #define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_RC1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY 0x0018 #define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT 0x001c #define cfgBIF_CFG_DEV0_RC1_SECONDARY_STATUS 0x001e #define cfgBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT 0x0020 #define cfgBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT 0x0024 #define cfgBIF_CFG_DEV0_RC1_PREF_BASE_UPPER 0x0028 #define cfgBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER 0x002c #define cfgBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI 0x0030 #define cfgBIF_CFG_DEV0_RC1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_RC1_ROM_BASE_ADDR 0x0038 #define cfgBIF_CFG_DEV0_RC1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_RC1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_RC1_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_RC1_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_RC1_PCIE_CAP_LIST 0x0058 #define cfgBIF_CFG_DEV0_RC1_PCIE_CAP 0x005a #define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP 0x005c #define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL 0x0060 #define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS 0x0062 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP 0x0064 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL 0x0068 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS 0x006a #define cfgBIF_CFG_DEV0_RC1_SLOT_CAP 0x006c #define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL 0x0070 #define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS 0x0072 #define cfgBIF_CFG_DEV0_RC1_DEVICE_CAP2 0x007c #define cfgBIF_CFG_DEV0_RC1_DEVICE_CNTL2 0x0080 #define cfgBIF_CFG_DEV0_RC1_DEVICE_STATUS2 0x0082 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP2 0x0084 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL2 0x0088 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS2 0x008a #define cfgBIF_CFG_DEV0_RC1_SLOT_CAP2 0x008c #define cfgBIF_CFG_DEV0_RC1_SLOT_CNTL2 0x0090 #define cfgBIF_CFG_DEV0_RC1_SLOT_STATUS2 0x0092 #define cfgBIF_CFG_DEV0_RC1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_RC1_SSID_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_RC1_SSID_CAP 0x00c4 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL 0x011c #define cfgBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS 0x011e #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP 0x0404 #define cfgBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP_16GT 0x0414 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_16GT 0x0418 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_16GT 0x041c #define cfgBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 #define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP 0x0454 #define cfgBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS 0x0456 #define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL 0x0458 #define cfgBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS 0x045a #define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL 0x045c #define cfgBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS 0x045e #define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL 0x0460 #define cfgBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS 0x0462 #define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL 0x0464 #define cfgBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS 0x0466 #define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL 0x0468 #define cfgBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS 0x046a #define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL 0x046c #define cfgBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS 0x046e #define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL 0x0470 #define cfgBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS 0x0472 #define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL 0x0474 #define cfgBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS 0x0476 #define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL 0x0478 #define cfgBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS 0x047a #define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL 0x047c #define cfgBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS 0x047e #define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL 0x0480 #define cfgBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS 0x0482 #define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL 0x0484 #define cfgBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS 0x0486 #define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL 0x0488 #define cfgBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS 0x048a #define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL 0x048c #define cfgBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS 0x048e #define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL 0x0490 #define cfgBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS 0x0492 #define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL 0x0494 #define cfgBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS 0x0496 #define cfgBIF_CFG_DEV0_RC1_LINK_CAP_32GT 0x0504 #define cfgBIF_CFG_DEV0_RC1_LINK_CNTL_32GT 0x0508 #define cfgBIF_CFG_DEV0_RC1_LINK_STATUS_32GT 0x050c // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0x011c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0x011e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0x02f4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0x02f6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0x02f8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0x02fc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0x0300 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0x0304 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0x030c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0x0324 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0x0334 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0x0338 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0x033a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0x033c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0x033e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0x0340 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0x0346 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0x0404 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0x0414 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0x0418 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0x041c #define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0x0454 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0x0456 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x0458 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x045a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x045c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x045e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x0460 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x0462 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x0464 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x0466 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x0468 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x046a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x046c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x046e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x0470 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x0472 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x0474 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x0476 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x0478 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x047a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x047c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x047e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x0480 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x0482 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x0484 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x0486 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x0488 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x048a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x048c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x048e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x0490 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x0492 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x0494 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x0496 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_32GT 0x0504 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_32GT 0x0508 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_32GT 0x050c // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF1_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0x02f4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0x02f6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0x02f8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0x02fc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0x0300 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0x0304 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0x030c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0x0324 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0x0334 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0x0338 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0x033a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0x033c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0x033e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0x0340 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0x0346 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0x034a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF2_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0x0060 #define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0x0061 #define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0x0062 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF3_1_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0x0060 #define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0x0061 #define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0x0062 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA 0x00aa #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 0x00ae #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0x032e #endif