/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_TPC3_QM_REGS_H_ #define ASIC_REG_TPC3_QM_REGS_H_ /* ***************************************** * TPC3_QM (Prototype: QMAN) ***************************************** */ #define mmTPC3_QM_GLBL_CFG0 0xEC8000 #define mmTPC3_QM_GLBL_CFG1 0xEC8004 #define mmTPC3_QM_GLBL_PROT 0xEC8008 #define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C #define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010 #define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014 #define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018 #define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C #define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034 #define mmTPC3_QM_GLBL_STS0 0xEC8038 #define mmTPC3_QM_GLBL_STS1_0 0xEC8040 #define mmTPC3_QM_GLBL_STS1_1 0xEC8044 #define mmTPC3_QM_GLBL_STS1_2 0xEC8048 #define mmTPC3_QM_GLBL_STS1_3 0xEC804C #define mmTPC3_QM_GLBL_STS1_4 0xEC8050 #define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054 #define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058 #define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C #define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060 #define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068 #define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070 #define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074 #define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078 #define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C #define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080 #define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084 #define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088 #define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C #define mmTPC3_QM_PQ_SIZE_0 0xEC8090 #define mmTPC3_QM_PQ_SIZE_1 0xEC8094 #define mmTPC3_QM_PQ_SIZE_2 0xEC8098 #define mmTPC3_QM_PQ_SIZE_3 0xEC809C #define mmTPC3_QM_PQ_PI_0 0xEC80A0 #define mmTPC3_QM_PQ_PI_1 0xEC80A4 #define mmTPC3_QM_PQ_PI_2 0xEC80A8 #define mmTPC3_QM_PQ_PI_3 0xEC80AC #define mmTPC3_QM_PQ_CI_0 0xEC80B0 #define mmTPC3_QM_PQ_CI_1 0xEC80B4 #define mmTPC3_QM_PQ_CI_2 0xEC80B8 #define mmTPC3_QM_PQ_CI_3 0xEC80BC #define mmTPC3_QM_PQ_CFG0_0 0xEC80C0 #define mmTPC3_QM_PQ_CFG0_1 0xEC80C4 #define mmTPC3_QM_PQ_CFG0_2 0xEC80C8 #define mmTPC3_QM_PQ_CFG0_3 0xEC80CC #define mmTPC3_QM_PQ_CFG1_0 0xEC80D0 #define mmTPC3_QM_PQ_CFG1_1 0xEC80D4 #define mmTPC3_QM_PQ_CFG1_2 0xEC80D8 #define mmTPC3_QM_PQ_CFG1_3 0xEC80DC #define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0 #define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4 #define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8 #define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC #define mmTPC3_QM_PQ_STS0_0 0xEC80F0 #define mmTPC3_QM_PQ_STS0_1 0xEC80F4 #define mmTPC3_QM_PQ_STS0_2 0xEC80F8 #define mmTPC3_QM_PQ_STS0_3 0xEC80FC #define mmTPC3_QM_PQ_STS1_0 0xEC8100 #define mmTPC3_QM_PQ_STS1_1 0xEC8104 #define mmTPC3_QM_PQ_STS1_2 0xEC8108 #define mmTPC3_QM_PQ_STS1_3 0xEC810C #define mmTPC3_QM_CQ_CFG0_0 0xEC8110 #define mmTPC3_QM_CQ_CFG0_1 0xEC8114 #define mmTPC3_QM_CQ_CFG0_2 0xEC8118 #define mmTPC3_QM_CQ_CFG0_3 0xEC811C #define mmTPC3_QM_CQ_CFG0_4 0xEC8120 #define mmTPC3_QM_CQ_CFG1_0 0xEC8124 #define mmTPC3_QM_CQ_CFG1_1 0xEC8128 #define mmTPC3_QM_CQ_CFG1_2 0xEC812C #define mmTPC3_QM_CQ_CFG1_3 0xEC8130 #define mmTPC3_QM_CQ_CFG1_4 0xEC8134 #define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138 #define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C #define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140 #define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144 #define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148 #define mmTPC3_QM_CQ_STS0_0 0xEC814C #define mmTPC3_QM_CQ_STS0_1 0xEC8150 #define mmTPC3_QM_CQ_STS0_2 0xEC8154 #define mmTPC3_QM_CQ_STS0_3 0xEC8158 #define mmTPC3_QM_CQ_STS0_4 0xEC815C #define mmTPC3_QM_CQ_STS1_0 0xEC8160 #define mmTPC3_QM_CQ_STS1_1 0xEC8164 #define mmTPC3_QM_CQ_STS1_2 0xEC8168 #define mmTPC3_QM_CQ_STS1_3 0xEC816C #define mmTPC3_QM_CQ_STS1_4 0xEC8170 #define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174 #define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178 #define mmTPC3_QM_CQ_TSIZE_0 0xEC817C #define mmTPC3_QM_CQ_CTL_0 0xEC8180 #define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184 #define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188 #define mmTPC3_QM_CQ_TSIZE_1 0xEC818C #define mmTPC3_QM_CQ_CTL_1 0xEC8190 #define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194 #define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198 #define mmTPC3_QM_CQ_TSIZE_2 0xEC819C #define mmTPC3_QM_CQ_CTL_2 0xEC81A0 #define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4 #define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8 #define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC #define mmTPC3_QM_CQ_CTL_3 0xEC81B0 #define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4 #define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8 #define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC #define mmTPC3_QM_CQ_CTL_4 0xEC81C0 #define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4 #define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8 #define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC #define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0 #define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4 #define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8 #define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC #define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0 #define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4 #define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8 #define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC #define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0 #define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4 #define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8 #define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC #define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200 #define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204 #define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208 #define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C #define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210 #define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214 #define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218 #define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C #define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220 #define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304 #define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308 #define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C #define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310 #define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314 #define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318 #define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C #define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320 #define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324 #define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328 #define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C #define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330 #define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334 #define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338 #define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C #define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340 #define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344 #define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348 #define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C #define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350 #define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354 #define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358 #define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C #define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360 #define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364 #define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368 #define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C #define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370 #define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374 #define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378 #define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C #define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380 #define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384 #define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388 #define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C #define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390 #define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394 #define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398 #define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C #define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0 #define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4 #define mmTPC3_QM_CP_STS_0 0xEC83A8 #define mmTPC3_QM_CP_STS_1 0xEC83AC #define mmTPC3_QM_CP_STS_2 0xEC83B0 #define mmTPC3_QM_CP_STS_3 0xEC83B4 #define mmTPC3_QM_CP_STS_4 0xEC83B8 #define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC #define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0 #define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4 #define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8 #define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC #define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0 #define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4 #define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8 #define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC #define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0 #define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4 #define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8 #define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC #define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400 #define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404 #define mmTPC3_QM_CP_DBG_0_0 0xEC8408 #define mmTPC3_QM_CP_DBG_0_1 0xEC840C #define mmTPC3_QM_CP_DBG_0_2 0xEC8410 #define mmTPC3_QM_CP_DBG_0_3 0xEC8414 #define mmTPC3_QM_CP_DBG_0_4 0xEC8418 #define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C #define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420 #define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424 #define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428 #define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C #define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430 #define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434 #define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438 #define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C #define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440 #define mmTPC3_QM_ARB_CFG_0 0xEC8A00 #define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04 #define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08 #define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C #define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10 #define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14 #define mmTPC3_QM_ARB_CFG_1 0xEC8A18 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C #define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C #define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20 #define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28 #define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C #define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34 #define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38 #define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C #define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44 #define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48 #define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C #define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50 #define mmTPC3_QM_ARB_BASE_LO 0xEC8B54 #define mmTPC3_QM_ARB_BASE_HI 0xEC8B58 #define mmTPC3_QM_ARB_STATE_STS 0xEC8B80 #define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84 #define mmTPC3_QM_ARB_MSG_STS 0xEC8B88 #define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C #define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C #define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0 #define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8 #define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0 #define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4 #define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8 #define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC #define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0 #define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4 #define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8 #define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC #define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0 #define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4 #define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8 #define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC #define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0 #define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4 #define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8 #define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC #define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0 #define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4 #define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8 #define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC #define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00 #define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04 #define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08 #define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C #define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10 #define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14 #define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18 #define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C #define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20 #define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24 #define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28 #define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C #define mmTPC3_QM_CGM_CFG 0xEC8C70 #define mmTPC3_QM_CGM_STS 0xEC8C74 #define mmTPC3_QM_CGM_CFG1 0xEC8C78 #define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80 #define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84 #define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90 #define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94 #define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98 #define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C #define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0 #define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4 #define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0 #define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4 #define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8 #define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC #define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0 #define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4 #define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8 #define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00 #endif /* ASIC_REG_TPC3_QM_REGS_H_ */