/*
	Copyright (c) 2002, Thomas Kurschel


	Part of Radeon driver
		
	General Purpose I/O control registers
*/

#ifndef _GPIOPAD_REGS_H
#define _GPIOPAD_REGS_H

#define RADEON_GPIOPAD_MASK			0x0198
#define RADEON_GPIOPAD_A			0x019c
#define RADEON_GPIOPAD_EN			0x01a0
#define RADEON_GPIOPAD_Y			0x01a4


#endif