/*- * Copyright (c) 2005 Olivier Houchard. All rights reserved. * Copyright (c) 2010 Greg Ansley. All rights reserved. * Copyright (c) 2012 M. Warner Losh.. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9x25.c 238376 2012-07-11 20:17:14Z imp $"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include struct at91sam9x25_softc { device_t dev; bus_space_tag_t sc_st; bus_space_handle_t sc_sh; bus_space_handle_t sc_sys_sh; bus_space_handle_t sc_aic_sh; }; /* * Standard priority levels for the system. 0 is lowest and 7 is highest. * These values are the ones Atmel uses for its Linux port */ static const int at91_irq_prio[32] = { 7, /* Advanced Interrupt Controller (FIQ) */ 7, /* System Peripherals */ 1, /* Parallel IO Controller A and B */ 1, /* Parallel IO Controller C and D */ 4, /* Soft Modem */ 5, /* USART 0 */ 5, /* USART 1 */ 5, /* USART 2 */ 5, /* USART 3 */ 6, /* Two-Wire Interface 0 */ 6, /* Two-Wire Interface 1 */ 6, /* Two-Wire Interface 2 */ 0, /* Multimedia Card Interface 0 */ 5, /* Serial Peripheral Interface 0 */ 5, /* Serial Peripheral Interface 1 */ 5, /* UART 0 */ 5, /* UART 1 */ 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 0, /* Pulse Width Modulation Controller */ 0, /* ADC Controller */ 0, /* DMA Controller 0 */ 0, /* DMA Controller 1 */ 2, /* USB Host High Speed port */ 2, /* USB Device High speed port */ 3, /* Ethernet MAC 0 */ 3, /* LDC Controller or Image Sensor Interface */ 0, /* Multimedia Card Interface 1 */ 3, /* Ethernet MAC 1 */ 4, /* Synchronous Serial Interface */ 4, /* CAN Controller 0 */ 4, /* CAN Controller 1 */ 0, /* Advanced Interrupt Controller (IRQ0) */ }; #define DEVICE(_name, _id, _unit) \ { \ _name, _unit, \ AT91SAM9X25_ ## _id ##_BASE, \ AT91SAM9X25_ ## _id ## _SIZE, \ AT91SAM9X25_IRQ_ ## _id \ } static const struct cpu_devs at91_devs[] = { DEVICE("at91_pmc", PMC, 0), DEVICE("at91_wdt", WDT, 0), DEVICE("at91_rst", RSTC, 0), DEVICE("at91_pit", PIT, 0), DEVICE("at91_pio", PIOA, 0), DEVICE("at91_pio", PIOB, 1), DEVICE("at91_pio", PIOC, 2), DEVICE("at91_pio", PIOD, 3), DEVICE("at91_twi", TWI0, 0), DEVICE("at91_twi", TWI1, 1), DEVICE("at91_twi", TWI2, 2), DEVICE("at91_mci", HSMCI0, 0), DEVICE("at91_mci", HSMCI1, 1), DEVICE("uart", DBGU, 0), DEVICE("uart", USART0, 1), DEVICE("uart", USART1, 2), DEVICE("uart", USART2, 3), DEVICE("uart", USART3, 4), DEVICE("spi", SPI0, 0), DEVICE("spi", SPI1, 1), DEVICE("macb", EMAC0, 0), DEVICE("macb", EMAC1, 0), DEVICE("nand", NAND, 0), DEVICE("ohci", OHCI, 0), DEVICE("ehci", EHCI, 0), { 0, 0, 0, 0, 0 } }; static void at91_cpu_add_builtin_children(device_t dev) { int i; const struct cpu_devs *walker; for (i = 1, walker = at91_devs; walker->name; i++, walker++) { at91_add_child(dev, i, walker->name, walker->unit, walker->mem_base, walker->mem_len, walker->irq0, walker->irq1, walker->irq2); } } static uint32_t at91_pll_outa(int freq) { switch (freq / 10000000) { case 747 ... 801: return ((1 << 29) | (0 << 14)); case 697 ... 746: return ((1 << 29) | (1 << 14)); case 647 ... 696: return ((1 << 29) | (2 << 14)); case 597 ... 646: return ((1 << 29) | (3 << 14)); case 547 ... 596: return ((1 << 29) | (1 << 14)); case 497 ... 546: return ((1 << 29) | (2 << 14)); case 447 ... 496: return ((1 << 29) | (3 << 14)); case 397 ... 446: return ((1 << 29) | (4 << 14)); default: return (1 << 29); } } static uint32_t at91_pll_outb(int freq) { return (0); } static void at91_identify(driver_t *drv, device_t parent) { if (soc_info.type == AT91_T_SAM9X5 && soc_info.subtype == AT91_ST_SAM9X25) { at91_add_child(parent, 0, "at91sam9x25", 0, 0, 0, -1, 0, 0); at91_cpu_add_builtin_children(parent); } } static int at91_probe(device_t dev) { device_set_desc(dev, "AT91SAM9X25"); return (0); } static int at91_attach(device_t dev) { struct at91_pmc_clock *clk; struct at91sam9x25_softc *sc = device_get_softc(dev); int i; struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); sc->sc_st = at91sc->sc_st; sc->sc_sh = at91sc->sc_sh; sc->dev = dev; /* * XXX These values work for the RM9200, SAM926[01], and SAM9X25 * will have to fix this when we want to support anything else. XXX */ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_SYS_BASE, AT91SAM9X25_SYS_SIZE, &sc->sc_sys_sh) != 0) panic("Enable to map system registers"); if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_AIC_BASE, AT91SAM9X25_AIC_SIZE, &sc->sc_aic_sh) != 0) panic("Enable to map system registers"); /* XXX Hack to tell atmelarm about the AIC */ at91sc->sc_aic_sh = sc->sc_aic_sh; for (i = 0; i < 32; i++) { bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + i * 4, i); /* Priority. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, at91_irq_prio[i]); if (i < 8) bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, 1); } bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); /* No debug. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); /* Disable and clear all interrupts. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); /* Update USB device port clock info */ clk = at91_pmc_clock_ref("udpck"); clk->pmc_mask = PMC_SCER_UDP_SAM9; at91_pmc_clock_deref(clk); /* Update USB host port clock info */ clk = at91_pmc_clock_ref("uhpck"); clk->pmc_mask = PMC_SCER_UHP_SAM9; at91_pmc_clock_deref(clk); /* Each SOC has different PLL contraints */ clk = at91_pmc_clock_ref("plla"); clk->pll_min_in = SAM9X25_PLL_A_MIN_IN_FREQ; /* 2 MHz */ clk->pll_max_in = SAM9X25_PLL_A_MAX_IN_FREQ; /* 32 MHz */ clk->pll_min_out = SAM9X25_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ clk->pll_max_out = SAM9X25_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ clk->pll_mul_shift = SAM9X25_PLL_A_MUL_SHIFT; clk->pll_mul_mask = SAM9X25_PLL_A_MUL_MASK; clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT; clk->pll_div_mask = SAM9X25_PLL_A_DIV_MASK; clk->set_outb = at91_pll_outa; at91_pmc_clock_deref(clk); clk = at91_pmc_clock_ref("pllb"); clk->pll_min_in = SAM9X25_PLL_B_MIN_IN_FREQ; /* 2 MHz */ clk->pll_max_in = SAM9X25_PLL_B_MAX_IN_FREQ; /* 32 MHz */ clk->pll_min_out = SAM9X25_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ clk->pll_max_out = SAM9X25_PLL_B_MAX_OUT_FREQ; /* 100 MHz */ clk->pll_mul_shift = SAM9X25_PLL_B_MUL_SHIFT; clk->pll_mul_mask = SAM9X25_PLL_B_MUL_MASK; clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT; clk->pll_div_mask = SAM9X25_PLL_B_DIV_MASK; clk->set_outb = at91_pll_outb; at91_pmc_clock_deref(clk); return (0); } static device_method_t at91sam9x25_methods[] = { DEVMETHOD(device_probe, at91_probe), DEVMETHOD(device_attach, at91_attach), DEVMETHOD(device_identify, at91_identify), {0, 0}, }; static driver_t at91sam9x25_driver = { "at91sam9x25", at91sam9x25_methods, sizeof(struct at91sam9x25_softc), }; static devclass_t at91sam9x25_devclass; DRIVER_MODULE(at91sam9x25, atmelarm, at91sam9x25_driver, at91sam9x25_devclass, 0, 0); static struct at91_soc_data soc_data = { .soc_delay = at91_pit_delay, .soc_reset = at91_rst_cpu_reset }; AT91_SOC_SUB(AT91_T_SAM9X5, AT91_ST_SAM9X25, &soc_data);