/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_abe_cm1.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_abe_cm1 msbfirst ( addr base ) "" {
    

    constants clkactivity_abe_24m_fclk_status width(1) "" {
        CLKACTIVITY_ABE_24M_FCLK_0_r = 0 "Corresponding clock is definitely gated";
        CLKACTIVITY_ABE_24M_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
    };

    constants clktrctrl_status width(2) "" {
        CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
        CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
        CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
        CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
    };
    
    register cm1_abe_clkstctrl addr(base, 0x0) "This register enables the ABE domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
        _ 18 mbz;
        clkactivity_abe_24m_fclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_24M_FCLK clock in the domain. [warm reset insensitive]";
        clkactivity_abe_alwon_32k_clk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_ALWON_32K_CLK clock in the domain. [warm reset insensitive]";
        clkactivity_abe_sysclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_SYSCLK clock in the domain. [warm reset insensitive]";
        clkactivity_24m_fclk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the 24M_FCLK clock in the domain. [warm reset insensitive]";
        clkactivity_abe_iclk2 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the ABE_ICLK2 interface clock in the domain. [warm reset insensitive]";
        clkactivity_dpll_abe_x2_clk 1 ro type(clkactivity_abe_24m_fclk_status) "This field indicates the state of the DPLL_ABE_X2_CLK clock in the domain. [warm reset insensitive]";
        _ 6 mbz;
        clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the ABE clock domain.";
    };

    constants idlest_status width(2) "" {
        IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
        IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
        IDLEST_2_r = 2 "Module is in Idle mode (only INTRCONN part). It is functional if using separate functional clock";
        IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
    };

    constants modulemode_status width(2) "" {
        MODULEMODE_1_r = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state.";
    };
    
    register cm1_abe_l4abe_clkctrl addr(base, 0x20) "This register manages the L4ABE clocks." {
        _ 14 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed.";
    };

    constants clksel_aess_fclk_status width(1) "" {
        CLKSEL_AESS_FCLK_0 = 0 "AESS_FCLK is divide by 1 of ABE_CLK";
        CLKSEL_AESS_FCLK_1 = 1 "AESS_FCLK is divide by 2 of ABE_CLK";
    };

    constants stbyst_status width(1) "" {
        STBYST_0_r = 0 "Module is functional (not in standby)";
        STBYST_1_r = 1 "Module is in standby";
    };

    constants modulemode_status1 width(2) "" {
        MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
        MODULEMODE_1_r_1 = 1 "Reserved";
        MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
        MODULEMODE_3_r = 3 "Reserved";
    };
    
    register cm1_abe_aess_clkctrl addr(base, 0x28) "This register manages the AESS clocks." {
        _ 7 mbz;
        clksel_aess_fclk 1 rw type(clksel_aess_fclk_status) "Selects the ratio of AESS_FCLK to ABE_CLK";
        _ 5 mbz;
        stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_pdm_clkctrl addr(base, 0x30) "This register manages the PDM clocks." {
        _ 14 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };

    constants clksel_internal_source_status width(2) "" {
        CLKSEL_INTERNAL_SOURCE_0 = 0 "24MHz clock derived from DPLL_ABE is selected";
        CLKSEL_INTERNAL_SOURCE_1 = 1 "ABE_SYSCLK is selected";
        CLKSEL_INTERNAL_SOURCE_2 = 2 "24MHz clock derived from DPLL_PER is selected";
        CLKSEL_INTERNAL_SOURCE_3 = 3 "Reserved";
    };

    constants clksel_source_status width(2) "" {
        CLKSEL_SOURCE_0 = 0 "Functional clock is sourced from an internal clock";
        CLKSEL_SOURCE_1 = 1 "Functional clock is sourced from CLKS pad";
        CLKSEL_SOURCE_2 = 2 "Functional clock is sourced from Audio SIMBUS pad";
        CLKSEL_SOURCE_3 = 3 "Reserved";
    };
    
    register cm1_abe_dmic_clkctrl addr(base, 0x38) "This register manages the DMIC clocks." {
        _ 4 mbz;
        clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
        clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_mcasp_clkctrl addr(base, 0x40) "This register manages the MCASP clocks." {
        _ 4 mbz;
        clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
        clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_mcbsp1_clkctrl addr(base, 0x48) "This register manages the MCBSP1 clocks." {
        _ 4 mbz;
        clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
        clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_mcbsp2_clkctrl addr(base, 0x50) "This register manages the MCBSP2 clocks." {
        _ 4 mbz;
        clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
        clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_mcbsp3_clkctrl addr(base, 0x58) "This register manages the MCBSP3 clocks." {
        _ 4 mbz;
        clksel_internal_source 2 rw type(clksel_internal_source_status) "Selects the internal clock to be used as the functional clock in case CLKSEL_SOURCE selects the internal clock source as the functional clock source.";
        clksel_source 2 rw type(clksel_source_status) "Selects the source of the functional clock between, internal source, CLKS pad and Audio SLIMBUS_CLK pad. The switching between the clocks is not guaranteed to be glitchless.";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };

    constants optfclken_slimbus_clk_status width(1) "" {
        OPTFCLKEN_SLIMBUS_CLK_0 = 0 "Optional functional clock is disabled";
        OPTFCLKEN_SLIMBUS_CLK_1 = 1 "Optional functional clock is enabled";
    };
    
    register cm1_abe_slimbus_clkctrl addr(base, 0x60) "This register manages the SLIMBUS clocks." {
        _ 14 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 4 mbz;
        optfclken_slimbus_clk 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
        optfclken_fclk2 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
        optfclken_fclk1 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
        optfclken_fclk0 1 rw type(optfclken_slimbus_clk_status) "Optional functional clock control.";
        _ 6 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };

    constants clksel_status width(1) "" {
        CLKSEL_0 = 0 "Selects ABE_SYSCLK as the functional clock";
        CLKSEL_1 = 1 "Selects ABE_ALWON_32K_CLK as the functional clock";
    };
    
    register cm1_abe_gptimer5_clkctrl addr(base, 0x68) "This register manages the TIMER5 clocks." {
        _ 7 mbz;
        clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_gptimer6_clkctrl addr(base, 0x70) "This register manages the TIMER6 clocks." {
        _ 7 mbz;
        clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_gptimer7_clkctrl addr(base, 0x78) "This register manages the TIMER7 clocks." {
        _ 7 mbz;
        clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_gptimer8_clkctrl addr(base, 0x80) "This register manages the TIMER8 clocks." {
        _ 7 mbz;
        clksel 1 rw type(clksel_status) "Selects between ABE_SYSCLK and ABE_ALWON_32K_CLK as the timer functional clock";
        _ 6 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
    
    register cm1_abe_wdtimer3_clkctrl addr(base, 0x88) "This register manages the WDT3 clocks." {
        _ 14 mbz;
        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
        _ 14 mbz;
        modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed.";
    };
};