#ifndef _RTL8367C_REG_H_ #define _RTL8367C_REG_H_ /************************************************************ auto-generated register address and field data *************************************************************/ /* (16'h0000)port_reg */ #define RTL8367C_REG_PORT0_CGST_HALF_CFG 0x0000 #define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT0_CTRL 0x0001 #define RTL8367C_PKTGEN_PORT0_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT0_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT0 0x0002 #define RTL8367C_TX_ERR_CNT_PORT0_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT0_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT0_DA0 0x0003 #define RTL8367C_REG_PKTGEN_PORT0_DA1 0x0004 #define RTL8367C_REG_PKTGEN_PORT0_DA2 0x0005 #define RTL8367C_REG_PKTGEN_PORT0_SA0 0x0006 #define RTL8367C_REG_PKTGEN_PORT0_SA1 0x0007 #define RTL8367C_REG_PKTGEN_PORT0_SA2 0x0008 #define RTL8367C_REG_PKTGEN_PORT0_COUNTER0 0x0009 #define RTL8367C_REG_PKTGEN_PORT0_COUNTER1 0x000a #define RTL8367C_PKTGEN_PORT0_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT0_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT0_TX_LENGTH 0x000b #define RTL8367C_PKTGEN_PORT0_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT0_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT0_TIMER 0x000d #define RTL8367C_PKTGEN_PORT0_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT0_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT0_MISC_CFG 0x000e #define RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT0_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT0_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT0_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT0_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL0 0x000f #define RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL1 0x0010 #define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT0_FORCE_RATE0 0x0011 #define RTL8367C_REG_PORT0_FORCE_RATE1 0x0012 #define RTL8367C_REG_PORT0_CURENT_RATE0 0x0013 #define RTL8367C_REG_PORT0_CURENT_RATE1 0x0014 #define RTL8367C_REG_PORT0_PAGE_COUNTER 0x0015 #define RTL8367C_PORT0_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT0_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT0_CTRL0 0x0016 #define RTL8367C_REG_PAGEMETER_PORT0_CTRL1 0x0017 #define RTL8367C_REG_PORT0_EEECFG 0x0018 #define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT0_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT0_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT0_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT0_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT0_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT0_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT0_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT0_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT0_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT0_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT0_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT0_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT0_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT0_EEETXMTR 0x0019 #define RTL8367C_REG_PORT0_EEERXMTR 0x001a #define RTL8367C_REG_PORT0_EEEPTXMTR 0x001b #define RTL8367C_REG_PORT0_EEEPRXMTR 0x001c #define RTL8367C_REG_PTP_PORT0_CFG1 0x001e #define RTL8367C_PTP_PORT0_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT0_CFG1_MASK 0xFF #define RTL8367C_REG_P0_MSIC1 0x001f #define RTL8367C_P0_MSIC1_OFFSET 0 #define RTL8367C_P0_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT1_CGST_HALF_CFG 0x0020 #define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT1_CTRL 0x0021 #define RTL8367C_PKTGEN_PORT1_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT1_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT1 0x0022 #define RTL8367C_TX_ERR_CNT_PORT1_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT1_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT1_DA0 0x0023 #define RTL8367C_REG_PKTGEN_PORT1_DA1 0x0024 #define RTL8367C_REG_PKTGEN_PORT1_DA2 0x0025 #define RTL8367C_REG_PKTGEN_PORT1_SA0 0x0026 #define RTL8367C_REG_PKTGEN_PORT1_SA1 0x0027 #define RTL8367C_REG_PKTGEN_PORT1_SA2 0x0028 #define RTL8367C_REG_PKTGEN_PORT1_COUNTER0 0x0029 #define RTL8367C_REG_PKTGEN_PORT1_COUNTER1 0x002a #define RTL8367C_PKTGEN_PORT1_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT1_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT1_TX_LENGTH 0x002b #define RTL8367C_PKTGEN_PORT1_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT1_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT1_TIMER 0x002d #define RTL8367C_PKTGEN_PORT1_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT1_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT1_MISC_CFG 0x002e #define RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT1_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT1_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT1_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT1_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL0 0x002f #define RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL1 0x0030 #define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT1_FORCE_RATE0 0x0031 #define RTL8367C_REG_PORT1_FORCE_RATE1 0x0032 #define RTL8367C_REG_PORT1_CURENT_RATE0 0x0033 #define RTL8367C_REG_PORT1_CURENT_RATE1 0x0034 #define RTL8367C_REG_PORT1_PAGE_COUNTER 0x0035 #define RTL8367C_PORT1_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT1_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT1_CTRL0 0x0036 #define RTL8367C_REG_PAGEMETER_PORT1_CTRL1 0x0037 #define RTL8367C_REG_PORT1_EEECFG 0x0038 #define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT1_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT1_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT1_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT1_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT1_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT1_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT1_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT1_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT1_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT1_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT1_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT1_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT1_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT1_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT1_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT1_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT1_EEETXMTR 0x0039 #define RTL8367C_REG_PORT1_EEERXMTR 0x003a #define RTL8367C_REG_PORT1_EEEPTXMTR 0x003b #define RTL8367C_REG_PORT1_EEEPRXMTR 0x003c #define RTL8367C_REG_PTP_PORT1_CFG1 0x003e #define RTL8367C_PTP_PORT1_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT1_CFG1_MASK 0xFF #define RTL8367C_REG_P1_MSIC1 0x003f #define RTL8367C_P1_MSIC1_OFFSET 0 #define RTL8367C_P1_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT2_CGST_HALF_CFG 0x0040 #define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT2_CTRL 0x0041 #define RTL8367C_PKTGEN_PORT2_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT2_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT2 0x0042 #define RTL8367C_TX_ERR_CNT_PORT2_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT2_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT2_DA0 0x0043 #define RTL8367C_REG_PKTGEN_PORT2_DA1 0x0044 #define RTL8367C_REG_PKTGEN_PORT2_DA2 0x0045 #define RTL8367C_REG_PKTGEN_PORT2_SA0 0x0046 #define RTL8367C_REG_PKTGEN_PORT2_SA1 0x0047 #define RTL8367C_REG_PKTGEN_PORT2_SA2 0x0048 #define RTL8367C_REG_PKTGEN_PORT2_COUNTER0 0x0049 #define RTL8367C_REG_PKTGEN_PORT2_COUNTER1 0x004a #define RTL8367C_PKTGEN_PORT2_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT2_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT2_TX_LENGTH 0x004b #define RTL8367C_PKTGEN_PORT2_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT2_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT2_TIMER 0x004d #define RTL8367C_PKTGEN_PORT2_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT2_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT2_MISC_CFG 0x004e #define RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT2_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT2_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT2_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT2_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL0 0x004f #define RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL1 0x0050 #define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT2_FORCE_RATE0 0x0051 #define RTL8367C_REG_PORT2_FORCE_RATE1 0x0052 #define RTL8367C_REG_PORT2_CURENT_RATE0 0x0053 #define RTL8367C_REG_PORT2_CURENT_RATE1 0x0054 #define RTL8367C_REG_PORT2_PAGE_COUNTER 0x0055 #define RTL8367C_PORT2_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT2_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT2_CTRL0 0x0056 #define RTL8367C_REG_PAGEMETER_PORT2_CTRL1 0x0057 #define RTL8367C_REG_PORT2_EEECFG 0x0058 #define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT2_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT2_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT2_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT2_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT2_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT2_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT2_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT2_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT2_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT2_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT2_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT2_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT2_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT2_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT2_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT2_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT2_EEETXMTR 0x0059 #define RTL8367C_REG_PORT2_EEERXMTR 0x005a #define RTL8367C_REG_PORT2_EEEPTXMTR 0x005b #define RTL8367C_REG_PORT2_EEEPRXMTR 0x005c #define RTL8367C_REG_PTP_PORT2_CFG1 0x005e #define RTL8367C_PTP_PORT2_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT2_CFG1_MASK 0xFF #define RTL8367C_REG_P2_MSIC1 0x005f #define RTL8367C_P2_MSIC1_OFFSET 0 #define RTL8367C_P2_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT3_CGST_HALF_CFG 0x0060 #define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT3_CTRL 0x0061 #define RTL8367C_PKTGEN_PORT3_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT3_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT3 0x0062 #define RTL8367C_TX_ERR_CNT_PORT3_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT3_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT3_DA0 0x0063 #define RTL8367C_REG_PKTGEN_PORT3_DA1 0x0064 #define RTL8367C_REG_PKTGEN_PORT3_DA2 0x0065 #define RTL8367C_REG_PKTGEN_PORT3_SA0 0x0066 #define RTL8367C_REG_PKTGEN_PORT3_SA1 0x0067 #define RTL8367C_REG_PKTGEN_PORT3_SA2 0x0068 #define RTL8367C_REG_PKTGEN_PORT3_COUNTER0 0x0069 #define RTL8367C_REG_PKTGEN_PORT3_COUNTER1 0x006a #define RTL8367C_PKTGEN_PORT3_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT3_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT3_TX_LENGTH 0x006b #define RTL8367C_PKTGEN_PORT3_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT3_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT3_TIMER 0x006d #define RTL8367C_PKTGEN_PORT3_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT3_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT3_MISC_CFG 0x006e #define RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT3_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT3_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT3_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT3_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL0 0x006f #define RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL1 0x0070 #define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT3_FORCE_RATE0 0x0071 #define RTL8367C_REG_PORT3_FORCE_RATE1 0x0072 #define RTL8367C_REG_PORT3_CURENT_RATE0 0x0073 #define RTL8367C_REG_PORT3_CURENT_RATE1 0x0074 #define RTL8367C_REG_PORT3_PAGE_COUNTER 0x0075 #define RTL8367C_PORT3_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT3_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT3_CTRL0 0x0076 #define RTL8367C_REG_PAGEMETER_PORT3_CTRL1 0x0077 #define RTL8367C_REG_PORT3_EEECFG 0x0078 #define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT3_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT3_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT3_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT3_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT3_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT3_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT3_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT3_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT3_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT3_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT3_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT3_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT3_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT3_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT3_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT3_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT3_EEETXMTR 0x0079 #define RTL8367C_REG_PORT3_EEERXMTR 0x007a #define RTL8367C_REG_PORT3_EEEPTXMTR 0x007b #define RTL8367C_REG_PORT3_EEEPRXMTR 0x007c #define RTL8367C_REG_PTP_PORT3_CFG1 0x007e #define RTL8367C_PTP_PORT3_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT3_CFG1_MASK 0xFF #define RTL8367C_REG_P3_MSIC1 0x007f #define RTL8367C_P3_MSIC1_OFFSET 0 #define RTL8367C_P3_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT4_CGST_HALF_CFG 0x0080 #define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT4_CTRL 0x0081 #define RTL8367C_PKTGEN_PORT4_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT4_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT4 0x0082 #define RTL8367C_TX_ERR_CNT_PORT4_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT4_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT4_DA0 0x0083 #define RTL8367C_REG_PKTGEN_PORT4_DA1 0x0084 #define RTL8367C_REG_PKTGEN_PORT4_DA2 0x0085 #define RTL8367C_REG_PKTGEN_PORT4_SA0 0x0086 #define RTL8367C_REG_PKTGEN_PORT4_SA1 0x0087 #define RTL8367C_REG_PKTGEN_PORT4_SA2 0x0088 #define RTL8367C_REG_PKTGEN_PORT4_COUNTER0 0x0089 #define RTL8367C_REG_PKTGEN_PORT4_COUNTER1 0x008a #define RTL8367C_PKTGEN_PORT4_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT4_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT4_TX_LENGTH 0x008b #define RTL8367C_PKTGEN_PORT4_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT4_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT4_TIMER 0x008d #define RTL8367C_PKTGEN_PORT4_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT4_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT4_MISC_CFG 0x008e #define RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT4_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT4_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT4_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT4_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL0 0x008f #define RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL1 0x0090 #define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT4_FORCE_RATE0 0x0091 #define RTL8367C_REG_PORT4_FORCE_RATE1 0x0092 #define RTL8367C_REG_PORT4_CURENT_RATE0 0x0093 #define RTL8367C_REG_PORT4_CURENT_RATE1 0x0094 #define RTL8367C_REG_PORT4_PAGE_COUNTER 0x0095 #define RTL8367C_PORT4_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT4_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT4_CTRL0 0x0096 #define RTL8367C_REG_PAGEMETER_PORT4_CTRL1 0x0097 #define RTL8367C_REG_PORT4_EEECFG 0x0098 #define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT4_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT4_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT4_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT4_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT4_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT4_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT4_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT4_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT4_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT4_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT4_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT4_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT4_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT4_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT4_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT4_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT4_EEETXMTR 0x0099 #define RTL8367C_REG_PORT4_EEERXMTR 0x009a #define RTL8367C_REG_PORT4_EEEPTXMTR 0x009b #define RTL8367C_REG_PORT4_EEEPRXMTR 0x009c #define RTL8367C_REG_PTP_PORT4_CFG1 0x009e #define RTL8367C_PTP_PORT4_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT4_CFG1_MASK 0xFF #define RTL8367C_REG_P4_MSIC1 0x009f #define RTL8367C_P4_MSIC1_OFFSET 0 #define RTL8367C_P4_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT5_CGST_HALF_CFG 0x00a0 #define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT5_CTRL 0x00a1 #define RTL8367C_PKTGEN_PORT5_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT5_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT5 0x00a2 #define RTL8367C_TX_ERR_CNT_PORT5_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT5_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT5_DA0 0x00a3 #define RTL8367C_REG_PKTGEN_PORT5_DA1 0x00a4 #define RTL8367C_REG_PKTGEN_PORT5_DA2 0x00a5 #define RTL8367C_REG_PKTGEN_PORT5_SA0 0x00a6 #define RTL8367C_REG_PKTGEN_PORT5_SA1 0x00a7 #define RTL8367C_REG_PKTGEN_PORT5_SA2 0x00a8 #define RTL8367C_REG_PKTGEN_PORT5_COUNTER0 0x00a9 #define RTL8367C_REG_PKTGEN_PORT5_COUNTER1 0x00aa #define RTL8367C_PKTGEN_PORT5_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT5_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT5_TX_LENGTH 0x00ab #define RTL8367C_PKTGEN_PORT5_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT5_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT5_TIMER 0x00ad #define RTL8367C_PKTGEN_PORT5_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT5_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT5_MISC_CFG 0x00ae #define RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT5_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT5_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT5_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT5_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL0 0x00af #define RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL1 0x00b0 #define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT5_FORCE_RATE0 0x00b1 #define RTL8367C_REG_PORT5_FORCE_RATE1 0x00b2 #define RTL8367C_REG_PORT5_CURENT_RATE0 0x00b3 #define RTL8367C_REG_PORT5_CURENT_RATE1 0x00b4 #define RTL8367C_REG_PORT5_PAGE_COUNTER 0x00b5 #define RTL8367C_PORT5_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT5_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT5_CTRL0 0x00b6 #define RTL8367C_REG_PAGEMETER_PORT5_CTRL1 0x00b7 #define RTL8367C_REG_PORT5_EEECFG 0x00b8 #define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT5_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT5_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT5_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT5_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT5_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT5_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT5_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT5_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT5_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT5_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT5_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT5_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT5_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT5_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT5_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT5_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT5_EEETXMTR 0x00b9 #define RTL8367C_REG_PORT5_EEERXMTR 0x00ba #define RTL8367C_REG_PORT5_EEEPTXMTR 0x00bb #define RTL8367C_REG_PORT5_EEEPRXMTR 0x00bc #define RTL8367C_REG_PTP_PORT5_CFG1 0x00be #define RTL8367C_PTP_PORT5_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT5_CFG1_MASK 0xFF #define RTL8367C_REG_P5_MSIC1 0x00bf #define RTL8367C_P5_MSIC1_OFFSET 0 #define RTL8367C_P5_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT6_CGST_HALF_CFG 0x00c0 #define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT6_CTRL 0x00c1 #define RTL8367C_PKTGEN_PORT6_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT6_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT6 0x00c2 #define RTL8367C_TX_ERR_CNT_PORT6_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT6_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT6_DA0 0x00c3 #define RTL8367C_REG_PKTGEN_PORT6_DA1 0x00c4 #define RTL8367C_REG_PKTGEN_PORT6_DA2 0x00c5 #define RTL8367C_REG_PKTGEN_PORT6_SA0 0x00c6 #define RTL8367C_REG_PKTGEN_PORT6_SA1 0x00c7 #define RTL8367C_REG_PKTGEN_PORT6_SA2 0x00c8 #define RTL8367C_REG_PKTGEN_PORT6_COUNTER0 0x00c9 #define RTL8367C_REG_PKTGEN_PORT6_COUNTER1 0x00ca #define RTL8367C_PKTGEN_PORT6_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT6_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT6_TX_LENGTH 0x00cb #define RTL8367C_PKTGEN_PORT6_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT6_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT6_TIMER 0x00cd #define RTL8367C_PKTGEN_PORT6_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT6_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT6_MISC_CFG 0x00ce #define RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT6_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT6_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT6_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT6_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL0 0x00cf #define RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL1 0x00d0 #define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT6_FORCE_RATE0 0x00d1 #define RTL8367C_REG_PORT6_FORCE_RATE1 0x00d2 #define RTL8367C_REG_PORT6_CURENT_RATE0 0x00d3 #define RTL8367C_REG_PORT6_CURENT_RATE1 0x00d4 #define RTL8367C_REG_PORT6_PAGE_COUNTER 0x00d5 #define RTL8367C_PORT6_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT6_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT6_CTRL0 0x00d6 #define RTL8367C_REG_PAGEMETER_PORT6_CTRL1 0x00d7 #define RTL8367C_REG_PORT6_EEECFG 0x00d8 #define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT6_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT6_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT6_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT6_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT6_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT6_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT6_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT6_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT6_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT6_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT6_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT6_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT6_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT6_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT6_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT6_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT6_EEETXMTR 0x00d9 #define RTL8367C_REG_PORT6_EEERXMTR 0x00da #define RTL8367C_REG_PORT6_EEEPTXMTR 0x00db #define RTL8367C_REG_PORT6_EEEPRXMTR 0x00dc #define RTL8367C_REG_PTP_PORT6_CFG1 0x00de #define RTL8367C_PTP_PORT6_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT6_CFG1_MASK 0xFF #define RTL8367C_REG_P6_MSIC1 0x00df #define RTL8367C_P6_MSIC1_OFFSET 0 #define RTL8367C_P6_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT7_CGST_HALF_CFG 0x00e0 #define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT7_CTRL 0x00e1 #define RTL8367C_PKTGEN_PORT7_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT7_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT7 0x00e2 #define RTL8367C_TX_ERR_CNT_PORT7_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT7_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT7_DA0 0x00e3 #define RTL8367C_REG_PKTGEN_PORT7_DA1 0x00e4 #define RTL8367C_REG_PKTGEN_PORT7_DA2 0x00e5 #define RTL8367C_REG_PKTGEN_PORT7_SA0 0x00e6 #define RTL8367C_REG_PKTGEN_PORT7_SA1 0x00e7 #define RTL8367C_REG_PKTGEN_PORT7_SA2 0x00e8 #define RTL8367C_REG_PKTGEN_PORT7_COUNTER0 0x00e9 #define RTL8367C_REG_PKTGEN_PORT7_COUNTER1 0x00ea #define RTL8367C_PKTGEN_PORT7_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT7_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT7_TX_LENGTH 0x00eb #define RTL8367C_PKTGEN_PORT7_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT7_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT7_TIMER 0x00ed #define RTL8367C_PKTGEN_PORT7_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT7_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT7_MISC_CFG 0x00ee #define RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT7_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT7_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT7_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT7_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL0 0x00ef #define RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL1 0x00f0 #define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT7_FORCE_RATE0 0x00f1 #define RTL8367C_REG_PORT7_FORCE_RATE1 0x00f2 #define RTL8367C_REG_PORT7_CURENT_RATE0 0x00f3 #define RTL8367C_REG_PORT7_CURENT_RATE1 0x00f4 #define RTL8367C_REG_PORT7_PAGE_COUNTER 0x00f5 #define RTL8367C_PORT7_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT7_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT7_CTRL0 0x00f6 #define RTL8367C_REG_PAGEMETER_PORT7_CTRL1 0x00f7 #define RTL8367C_REG_PORT7_EEECFG 0x00f8 #define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT7_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT7_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT7_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT7_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT7_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT7_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT7_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT7_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT7_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT7_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT7_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT7_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT7_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT7_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT7_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT7_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT7_EEETXMTR 0x00f9 #define RTL8367C_REG_PORT7_EEERXMTR 0x00fa #define RTL8367C_REG_PORT7_EEEPTXMTR 0x00fb #define RTL8367C_REG_PORT7_EEEPRXMTR 0x00fc #define RTL8367C_REG_PTP_PORT7_CFG1 0x00fe #define RTL8367C_PTP_PORT7_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT7_CFG1_MASK 0xFF #define RTL8367C_REG_P7_MSIC1 0x00ff #define RTL8367C_P7_MSIC1_OFFSET 0 #define RTL8367C_P7_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT8_CGST_HALF_CFG 0x0100 #define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT8_CTRL 0x0101 #define RTL8367C_PKTGEN_PORT8_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT8_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT8 0x0102 #define RTL8367C_TX_ERR_CNT_PORT8_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT8_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT8_DA0 0x0103 #define RTL8367C_REG_PKTGEN_PORT8_DA1 0x0104 #define RTL8367C_REG_PKTGEN_PORT8_DA2 0x0105 #define RTL8367C_REG_PKTGEN_PORT8_SA0 0x0106 #define RTL8367C_REG_PKTGEN_PORT8_SA1 0x0107 #define RTL8367C_REG_PKTGEN_PORT8_SA2 0x0108 #define RTL8367C_REG_PKTGEN_PORT8_COUNTER0 0x0109 #define RTL8367C_REG_PKTGEN_PORT8_COUNTER1 0x010a #define RTL8367C_PKTGEN_PORT8_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT8_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT8_TX_LENGTH 0x010b #define RTL8367C_PKTGEN_PORT8_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT8_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT8_TIMER 0x010d #define RTL8367C_PKTGEN_PORT8_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT8_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT8_MISC_CFG 0x010e #define RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT8_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT8_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT8_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT8_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL0 0x010f #define RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL1 0x0110 #define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT8_FORCE_RATE0 0x0111 #define RTL8367C_REG_PORT8_FORCE_RATE1 0x0112 #define RTL8367C_REG_PORT8_CURENT_RATE0 0x0113 #define RTL8367C_REG_PORT8_CURENT_RATE1 0x0114 #define RTL8367C_REG_PORT8_PAGE_COUNTER 0x0115 #define RTL8367C_PORT8_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT8_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT8_CTRL0 0x0116 #define RTL8367C_REG_PAGEMETER_PORT8_CTRL1 0x0117 #define RTL8367C_REG_PORT8_EEECFG 0x0118 #define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT8_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT8_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT8_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT8_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT8_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT8_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT8_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT8_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT8_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT8_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT8_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT8_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT8_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT8_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT8_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT8_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT8_EEETXMTR 0x0119 #define RTL8367C_REG_PORT8_EEERXMTR 0x011a #define RTL8367C_REG_PORT8_EEEPTXMTR 0x011b #define RTL8367C_REG_PORT8_EEEPRXMTR 0x011c #define RTL8367C_REG_PTP_PORT8_CFG1 0x011e #define RTL8367C_PTP_PORT8_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT8_CFG1_MASK 0xFF #define RTL8367C_REG_P8_MSIC1 0x011f #define RTL8367C_P8_MSIC1_OFFSET 0 #define RTL8367C_P8_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT9_CGST_HALF_CFG 0x0120 #define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT9_CTRL 0x0121 #define RTL8367C_PKTGEN_PORT9_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT9_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT9 0x0122 #define RTL8367C_TX_ERR_CNT_PORT9_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT9_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT9_DA0 0x0123 #define RTL8367C_REG_PKTGEN_PORT9_DA1 0x0124 #define RTL8367C_REG_PKTGEN_PORT9_DA2 0x0125 #define RTL8367C_REG_PKTGEN_PORT9_SA0 0x0126 #define RTL8367C_REG_PKTGEN_PORT9_SA1 0x0127 #define RTL8367C_REG_PKTGEN_PORT9_SA2 0x0128 #define RTL8367C_REG_PKTGEN_PORT9_COUNTER0 0x0129 #define RTL8367C_REG_PKTGEN_PORT9_COUNTER1 0x012a #define RTL8367C_PKTGEN_PORT9_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT9_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT9_TX_LENGTH 0x012b #define RTL8367C_PKTGEN_PORT9_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT9_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT9_TIMER 0x012d #define RTL8367C_PKTGEN_PORT9_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT9_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT9_MISC_CFG 0x012e #define RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT9_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT9_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT9_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT9_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL0 0x012f #define RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL1 0x0130 #define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT9_FORCE_RATE0 0x0131 #define RTL8367C_REG_PORT9_FORCE_RATE1 0x0132 #define RTL8367C_REG_PORT9_CURENT_RATE0 0x0133 #define RTL8367C_REG_PORT9_CURENT_RATE1 0x0134 #define RTL8367C_REG_PORT9_PAGE_COUNTER 0x0135 #define RTL8367C_PORT9_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT9_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT9_CTRL0 0x0136 #define RTL8367C_REG_PAGEMETER_PORT9_CTRL1 0x0137 #define RTL8367C_REG_PORT9_EEECFG 0x0138 #define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT9_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT9_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT9_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT9_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT9_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT9_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT9_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT9_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT9_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT9_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT9_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT9_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT9_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT9_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT9_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT9_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT9_EEETXMTR 0x0139 #define RTL8367C_REG_PORT9_EEERXMTR 0x013a #define RTL8367C_REG_PORT9_EEEPTXMTR 0x013b #define RTL8367C_REG_PORT9_EEEPRXMTR 0x013c #define RTL8367C_REG_PTP_PORT9_CFG1 0x013e #define RTL8367C_PTP_PORT9_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT9_CFG1_MASK 0xFF #define RTL8367C_REG_P9_MSIC1 0x013f #define RTL8367C_P9_MSIC1_OFFSET 0 #define RTL8367C_P9_MSIC1_MASK 0x1 #define RTL8367C_REG_PORT10_CGST_HALF_CFG 0x0140 #define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 #define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 #define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_PKTGEN_PORT10_CTRL 0x0141 #define RTL8367C_PKTGEN_PORT10_CTRL_STATUS_OFFSET 15 #define RTL8367C_PKTGEN_PORT10_CTRL_STATUS_MASK 0x8000 #define RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_OFFSET 13 #define RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_MASK 0x2000 #define RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_OFFSET 4 #define RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_MASK 0x10 #define RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_OFFSET 0 #define RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_MASK 0x1 #define RTL8367C_REG_TX_ERR_CNT_PORT10 0x0142 #define RTL8367C_TX_ERR_CNT_PORT10_OFFSET 0 #define RTL8367C_TX_ERR_CNT_PORT10_MASK 0x7 #define RTL8367C_REG_PKTGEN_PORT10_DA0 0x0143 #define RTL8367C_REG_PKTGEN_PORT10_DA1 0x0144 #define RTL8367C_REG_PKTGEN_PORT10_DA2 0x0145 #define RTL8367C_REG_PKTGEN_PORT10_SA0 0x0146 #define RTL8367C_REG_PKTGEN_PORT10_SA1 0x0147 #define RTL8367C_REG_PKTGEN_PORT10_SA2 0x0148 #define RTL8367C_REG_PKTGEN_PORT10_COUNTER0 0x0149 #define RTL8367C_REG_PKTGEN_PORT10_COUNTER1 0x014a #define RTL8367C_PKTGEN_PORT10_COUNTER1_OFFSET 0 #define RTL8367C_PKTGEN_PORT10_COUNTER1_MASK 0xFF #define RTL8367C_REG_PKTGEN_PORT10_TX_LENGTH 0x014b #define RTL8367C_PKTGEN_PORT10_TX_LENGTH_OFFSET 0 #define RTL8367C_PKTGEN_PORT10_TX_LENGTH_MASK 0x3FFF #define RTL8367C_REG_PKTGEN_PORT10_TIMER 0x014d #define RTL8367C_PKTGEN_PORT10_TIMER_TIMER_OFFSET 4 #define RTL8367C_PKTGEN_PORT10_TIMER_TIMER_MASK 0xF0 #define RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 #define RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 #define RTL8367C_REG_PORT10_MISC_CFG 0x014e #define RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 #define RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 #define RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 #define RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 #define RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 #define RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 #define RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 #define RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 #define RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 #define RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 #define RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_OFFSET 10 #define RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_MASK 0x400 #define RTL8367C_PORT10_MISC_CFG_RX_SPC_OFFSET 9 #define RTL8367C_PORT10_MISC_CFG_RX_SPC_MASK 0x200 #define RTL8367C_PORT10_MISC_CFG_CRC_SKIP_OFFSET 8 #define RTL8367C_PORT10_MISC_CFG_CRC_SKIP_MASK 0x100 #define RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 #define RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 #define RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_OFFSET 6 #define RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_MASK 0x40 #define RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 #define RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 #define RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 #define RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF #define RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL0 0x014f #define RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL1 0x0150 #define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_OFFSET 3 #define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_MASK 0xFFF8 #define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 #define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 #define RTL8367C_REG_PORT10_FORCE_RATE0 0x0151 #define RTL8367C_REG_PORT10_FORCE_RATE1 0x0152 #define RTL8367C_REG_PORT10_CURENT_RATE0 0x0153 #define RTL8367C_REG_PORT10_CURENT_RATE1 0x0154 #define RTL8367C_REG_PORT10_PAGE_COUNTER 0x0155 #define RTL8367C_PORT10_PAGE_COUNTER_OFFSET 0 #define RTL8367C_PORT10_PAGE_COUNTER_MASK 0x7F #define RTL8367C_REG_PAGEMETER_PORT10_CTRL0 0x0156 #define RTL8367C_REG_PAGEMETER_PORT10_CTRL1 0x0157 #define RTL8367C_REG_PORT10_EEECFG 0x0158 #define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_OFFSET 14 #define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 #define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_OFFSET 13 #define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 #define RTL8367C_PORT10_EEECFG_EEE_FORCE_OFFSET 12 #define RTL8367C_PORT10_EEECFG_EEE_FORCE_MASK 0x1000 #define RTL8367C_PORT10_EEECFG_EEE_100M_OFFSET 11 #define RTL8367C_PORT10_EEECFG_EEE_100M_MASK 0x800 #define RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_OFFSET 10 #define RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_MASK 0x400 #define RTL8367C_PORT10_EEECFG_EEE_TX_OFFSET 9 #define RTL8367C_PORT10_EEECFG_EEE_TX_MASK 0x200 #define RTL8367C_PORT10_EEECFG_EEE_RX_OFFSET 8 #define RTL8367C_PORT10_EEECFG_EEE_RX_MASK 0x100 #define RTL8367C_PORT10_EEECFG_EEE_DSP_RX_OFFSET 6 #define RTL8367C_PORT10_EEECFG_EEE_DSP_RX_MASK 0x40 #define RTL8367C_PORT10_EEECFG_EEE_LPI_OFFSET 5 #define RTL8367C_PORT10_EEECFG_EEE_LPI_MASK 0x20 #define RTL8367C_PORT10_EEECFG_EEE_TX_LPI_OFFSET 4 #define RTL8367C_PORT10_EEECFG_EEE_TX_LPI_MASK 0x10 #define RTL8367C_PORT10_EEECFG_EEE_RX_LPI_OFFSET 3 #define RTL8367C_PORT10_EEECFG_EEE_RX_LPI_MASK 0x8 #define RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 #define RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 #define RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_OFFSET 1 #define RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_MASK 0x2 #define RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_OFFSET 0 #define RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_MASK 0x1 #define RTL8367C_REG_PORT10_EEETXMTR 0x0159 #define RTL8367C_REG_PORT10_EEERXMTR 0x015a #define RTL8367C_REG_PORT10_EEEPTXMTR 0x015b #define RTL8367C_REG_PORT10_EEEPRXMTR 0x015c #define RTL8367C_REG_PTP_PORT10_CFG1 0x015e #define RTL8367C_PTP_PORT10_CFG1_OFFSET 7 #define RTL8367C_PTP_PORT10_CFG1_MASK 0xFF #define RTL8367C_REG_P10_MSIC1 0x015f #define RTL8367C_P10_MSIC1_OFFSET 0 #define RTL8367C_P10_MSIC1_MASK 0x1 /* (16'h0200)outq_reg */ #define RTL8367C_REG_FLOWCTRL_QUEUE0_DROP_ON 0x0200 #define RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE1_DROP_ON 0x0201 #define RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE2_DROP_ON 0x0202 #define RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE3_DROP_ON 0x0203 #define RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE4_DROP_ON 0x0204 #define RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE5_DROP_ON 0x0205 #define RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE6_DROP_ON 0x0206 #define RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE7_DROP_ON 0x0207 #define RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT0_DROP_ON 0x0208 #define RTL8367C_FLOWCTRL_PORT0_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT0_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT1_DROP_ON 0x0209 #define RTL8367C_FLOWCTRL_PORT1_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT1_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT2_DROP_ON 0x020a #define RTL8367C_FLOWCTRL_PORT2_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT2_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT3_DROP_ON 0x020b #define RTL8367C_FLOWCTRL_PORT3_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT3_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT4_DROP_ON 0x020c #define RTL8367C_FLOWCTRL_PORT4_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT4_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT5_DROP_ON 0x020d #define RTL8367C_FLOWCTRL_PORT5_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT5_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT6_DROP_ON 0x020e #define RTL8367C_FLOWCTRL_PORT6_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT6_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT7_DROP_ON 0x020f #define RTL8367C_FLOWCTRL_PORT7_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT7_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT8_DROP_ON 0x0210 #define RTL8367C_FLOWCTRL_PORT8_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT8_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT9_DROP_ON 0x0211 #define RTL8367C_FLOWCTRL_PORT9_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT9_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT10_DROP_ON 0x0212 #define RTL8367C_FLOWCTRL_PORT10_DROP_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT10_DROP_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_GAP 0x0218 #define RTL8367C_FLOWCTRL_PORT_GAP_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_GAP_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE_GAP 0x0219 #define RTL8367C_FLOWCTRL_QUEUE_GAP_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE_GAP_MASK 0x7FF #define RTL8367C_REG_PORT_QEMPTY 0x022d #define RTL8367C_PORT_QEMPTY_OFFSET 0 #define RTL8367C_PORT_QEMPTY_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_DEBUG_CTRL0 0x022e #define RTL8367C_FLOWCTRL_DEBUG_CTRL0_OFFSET 0 #define RTL8367C_FLOWCTRL_DEBUG_CTRL0_MASK 0xF #define RTL8367C_REG_FLOWCTRL_DEBUG_CTRL1 0x022f #define RTL8367C_TOTAL_OFFSET 9 #define RTL8367C_TOTAL_MASK 0x200 #define RTL8367C_PORT_MAX_OFFSET 8 #define RTL8367C_PORT_MAX_MASK 0x100 #define RTL8367C_QMAX_MASK_OFFSET 0 #define RTL8367C_QMAX_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCTRL_QUEUE0_PAGE_COUNT 0x0230 #define RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE1_PAGE_COUNT 0x0231 #define RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE2_PAGE_COUNT 0x0232 #define RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE3_PAGE_COUNT 0x0233 #define RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE4_PAGE_COUNT 0x0234 #define RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE5_PAGE_COUNT 0x0235 #define RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE6_PAGE_COUNT 0x0236 #define RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE7_PAGE_COUNT 0x0237 #define RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_PAGE_COUNT 0x0238 #define RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT 0x0239 #define RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT 0x023a #define RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT 0x023b #define RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT 0x023c #define RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT 0x023d #define RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT 0x023e #define RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT 0x023f #define RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT 0x0240 #define RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT 0x0241 #define RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_TOTAL_PACKET_COUNT 0x0243 #define RTL8367C_REG_HIGH_QUEUE_MASK0 0x0244 #define RTL8367C_PORT1_HIGH_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT1_HIGH_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT0_HIGH_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT0_HIGH_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_HIGH_QUEUE_MASK1 0x0245 #define RTL8367C_PORT3_HIGH_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT3_HIGH_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT2_HIGH_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT2_HIGH_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_HIGH_QUEUE_MASK2 0x0246 #define RTL8367C_PORT5_HIGH_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT5_HIGH_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT4_HIGH_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT4_HIGH_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_HIGH_QUEUE_MASK3 0x0247 #define RTL8367C_PORT7_HIGH_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT7_HIGH_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT6_HIGH_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT6_HIGH_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_HIGH_QUEUE_MASK4 0x0248 #define RTL8367C_PORT9_HIGH_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT9_HIGH_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT8_HIGH_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT8_HIGH_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_HIGH_QUEUE_MASK5 0x0249 #define RTL8367C_HIGH_QUEUE_MASK5_OFFSET 0 #define RTL8367C_HIGH_QUEUE_MASK5_MASK 0xFF #define RTL8367C_REG_LOW_QUEUE_TH 0x024c #define RTL8367C_LOW_QUEUE_TH_OFFSET 0 #define RTL8367C_LOW_QUEUE_TH_MASK 0x7FF #define RTL8367C_REG_TH_TX_PREFET 0x0250 #define RTL8367C_TH_TX_PREFET_OFFSET 0 #define RTL8367C_TH_TX_PREFET_MASK 0xFF #define RTL8367C_REG_DUMMY_0251 0x0251 #define RTL8367C_REG_DUMMY_0252 0x0252 #define RTL8367C_REG_DUMMY_0253 0x0253 #define RTL8367C_REG_DUMMY_0254 0x0254 #define RTL8367C_REG_DUMMY_0255 0x0255 #define RTL8367C_REG_DUMMY_0256 0x0256 #define RTL8367C_REG_DUMMY_0257 0x0257 #define RTL8367C_REG_DUMMY_0258 0x0258 #define RTL8367C_REG_DUMMY_0259 0x0259 #define RTL8367C_REG_DUMMY_025A 0x025A #define RTL8367C_REG_DUMMY_025B 0x025B #define RTL8367C_REG_DUMMY_025C 0x025C #define RTL8367C_REG_Q_TXPKT_CNT_CTL 0x025d #define RTL8367C_QUEUE_PKT_CNT_CLR_OFFSET 4 #define RTL8367C_QUEUE_PKT_CNT_CLR_MASK 0x10 #define RTL8367C_PORT_ID_QUEUE_PKT_CNT_OFFSET 0 #define RTL8367C_PORT_ID_QUEUE_PKT_CNT_MASK 0xF #define RTL8367C_REG_Q0_TXPKT_CNT_L 0x025e #define RTL8367C_REG_Q0_TXPKT_CNT_H 0x025f #define RTL8367C_REG_Q1_TXPKT_CNT_L 0x0260 #define RTL8367C_REG_Q1_TXPKT_CNT_H 0x0261 #define RTL8367C_REG_Q2_TXPKT_CNT_L 0x0262 #define RTL8367C_REG_Q2_TXPKT_CNT_H 0x0263 #define RTL8367C_REG_Q3_TXPKT_CNT_L 0x0264 #define RTL8367C_REG_Q3_TXPKT_CNT_H 0x0265 #define RTL8367C_REG_Q4_TXPKT_CNT_L 0x0266 #define RTL8367C_REG_Q4_TXPKT_CNT_H 0x0267 #define RTL8367C_REG_Q5_TXPKT_CNT_L 0x0268 #define RTL8367C_REG_Q5_TXPKT_CNT_H 0x0269 #define RTL8367C_REG_Q6_TXPKT_CNT_L 0x026a #define RTL8367C_REG_Q6_TXPKT_CNT_H 0x026b #define RTL8367C_REG_Q7_TXPKT_CNT_L 0x026c #define RTL8367C_REG_Q7_TXPKT_CNT_H 0x026d /* (16'h0300)sch_reg */ #define RTL8367C_REG_SCHEDULE_WFQ_CTRL 0x0300 #define RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET 0 #define RTL8367C_SCHEDULE_WFQ_CTRL_MASK 0x1 #define RTL8367C_REG_SCHEDULE_WFQ_BURST_SIZE 0x0301 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL0 0x0302 #define RTL8367C_PORT1_QUEUE7_TYPE_OFFSET 15 #define RTL8367C_PORT1_QUEUE7_TYPE_MASK 0x8000 #define RTL8367C_PORT1_QUEUE6_TYPE_OFFSET 14 #define RTL8367C_PORT1_QUEUE6_TYPE_MASK 0x4000 #define RTL8367C_PORT1_QUEUE5_TYPE_OFFSET 13 #define RTL8367C_PORT1_QUEUE5_TYPE_MASK 0x2000 #define RTL8367C_PORT1_QUEUE4_TYPE_OFFSET 12 #define RTL8367C_PORT1_QUEUE4_TYPE_MASK 0x1000 #define RTL8367C_PORT1_QUEUE3_TYPE_OFFSET 11 #define RTL8367C_PORT1_QUEUE3_TYPE_MASK 0x800 #define RTL8367C_PORT1_QUEUE2_TYPE_OFFSET 10 #define RTL8367C_PORT1_QUEUE2_TYPE_MASK 0x400 #define RTL8367C_PORT1_QUEUE1_TYPE_OFFSET 9 #define RTL8367C_PORT1_QUEUE1_TYPE_MASK 0x200 #define RTL8367C_PORT1_QUEUE0_TYPE_OFFSET 8 #define RTL8367C_PORT1_QUEUE0_TYPE_MASK 0x100 #define RTL8367C_PORT0_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT0_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT0_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT0_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT0_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT0_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT0_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT0_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT0_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT0_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT0_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT0_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT0_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT0_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_PORT0_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_PORT0_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL1 0x0303 #define RTL8367C_PORT3_QUEUE7_TYPE_OFFSET 15 #define RTL8367C_PORT3_QUEUE7_TYPE_MASK 0x8000 #define RTL8367C_PORT3_QUEUE6_TYPE_OFFSET 14 #define RTL8367C_PORT3_QUEUE6_TYPE_MASK 0x4000 #define RTL8367C_PORT3_QUEUE5_TYPE_OFFSET 13 #define RTL8367C_PORT3_QUEUE5_TYPE_MASK 0x2000 #define RTL8367C_PORT3_QUEUE4_TYPE_OFFSET 12 #define RTL8367C_PORT3_QUEUE4_TYPE_MASK 0x1000 #define RTL8367C_PORT3_QUEUE3_TYPE_OFFSET 11 #define RTL8367C_PORT3_QUEUE3_TYPE_MASK 0x800 #define RTL8367C_PORT3_QUEUE2_TYPE_OFFSET 10 #define RTL8367C_PORT3_QUEUE2_TYPE_MASK 0x400 #define RTL8367C_PORT3_QUEUE1_TYPE_OFFSET 9 #define RTL8367C_PORT3_QUEUE1_TYPE_MASK 0x200 #define RTL8367C_PORT3_QUEUE0_TYPE_OFFSET 8 #define RTL8367C_PORT3_QUEUE0_TYPE_MASK 0x100 #define RTL8367C_PORT2_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT2_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT2_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT2_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT2_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT2_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT2_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT2_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT2_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT2_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT2_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT2_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT2_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT2_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_PORT2_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_PORT2_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL2 0x0304 #define RTL8367C_PORT5_QUEUE7_TYPE_OFFSET 15 #define RTL8367C_PORT5_QUEUE7_TYPE_MASK 0x8000 #define RTL8367C_PORT5_QUEUE6_TYPE_OFFSET 14 #define RTL8367C_PORT5_QUEUE6_TYPE_MASK 0x4000 #define RTL8367C_PORT5_QUEUE5_TYPE_OFFSET 13 #define RTL8367C_PORT5_QUEUE5_TYPE_MASK 0x2000 #define RTL8367C_PORT5_QUEUE4_TYPE_OFFSET 12 #define RTL8367C_PORT5_QUEUE4_TYPE_MASK 0x1000 #define RTL8367C_PORT5_QUEUE3_TYPE_OFFSET 11 #define RTL8367C_PORT5_QUEUE3_TYPE_MASK 0x800 #define RTL8367C_PORT5_QUEUE2_TYPE_OFFSET 10 #define RTL8367C_PORT5_QUEUE2_TYPE_MASK 0x400 #define RTL8367C_PORT5_QUEUE1_TYPE_OFFSET 9 #define RTL8367C_PORT5_QUEUE1_TYPE_MASK 0x200 #define RTL8367C_PORT5_QUEUE0_TYPE_OFFSET 8 #define RTL8367C_PORT5_QUEUE0_TYPE_MASK 0x100 #define RTL8367C_PORT4_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT4_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT4_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT4_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT4_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT4_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT4_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT4_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT4_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT4_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT4_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT4_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT4_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT4_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_PORT4_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_PORT4_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL3 0x0305 #define RTL8367C_PORT7_QUEUE7_TYPE_OFFSET 15 #define RTL8367C_PORT7_QUEUE7_TYPE_MASK 0x8000 #define RTL8367C_PORT7_QUEUE6_TYPE_OFFSET 14 #define RTL8367C_PORT7_QUEUE6_TYPE_MASK 0x4000 #define RTL8367C_PORT7_QUEUE5_TYPE_OFFSET 13 #define RTL8367C_PORT7_QUEUE5_TYPE_MASK 0x2000 #define RTL8367C_PORT7_QUEUE4_TYPE_OFFSET 12 #define RTL8367C_PORT7_QUEUE4_TYPE_MASK 0x1000 #define RTL8367C_PORT7_QUEUE3_TYPE_OFFSET 11 #define RTL8367C_PORT7_QUEUE3_TYPE_MASK 0x800 #define RTL8367C_PORT7_QUEUE2_TYPE_OFFSET 10 #define RTL8367C_PORT7_QUEUE2_TYPE_MASK 0x400 #define RTL8367C_PORT7_QUEUE1_TYPE_OFFSET 9 #define RTL8367C_PORT7_QUEUE1_TYPE_MASK 0x200 #define RTL8367C_PORT7_QUEUE0_TYPE_OFFSET 8 #define RTL8367C_PORT7_QUEUE0_TYPE_MASK 0x100 #define RTL8367C_PORT6_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT6_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT6_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT6_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT6_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT6_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT6_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT6_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT6_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT6_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT6_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT6_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT6_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT6_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL4 0x0306 #define RTL8367C_PORT9_QUEUE7_TYPE_OFFSET 15 #define RTL8367C_PORT9_QUEUE7_TYPE_MASK 0x8000 #define RTL8367C_PORT9_QUEUE6_TYPE_OFFSET 14 #define RTL8367C_PORT9_QUEUE6_TYPE_MASK 0x4000 #define RTL8367C_PORT9_QUEUE5_TYPE_OFFSET 13 #define RTL8367C_PORT9_QUEUE5_TYPE_MASK 0x2000 #define RTL8367C_PORT9_QUEUE4_TYPE_OFFSET 12 #define RTL8367C_PORT9_QUEUE4_TYPE_MASK 0x1000 #define RTL8367C_PORT9_QUEUE3_TYPE_OFFSET 11 #define RTL8367C_PORT9_QUEUE3_TYPE_MASK 0x800 #define RTL8367C_PORT9_QUEUE2_TYPE_OFFSET 10 #define RTL8367C_PORT9_QUEUE2_TYPE_MASK 0x400 #define RTL8367C_PORT9_QUEUE1_TYPE_OFFSET 9 #define RTL8367C_PORT9_QUEUE1_TYPE_MASK 0x200 #define RTL8367C_PORT9_QUEUE0_TYPE_OFFSET 8 #define RTL8367C_PORT9_QUEUE0_TYPE_MASK 0x100 #define RTL8367C_PORT8_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT8_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT8_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT8_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT8_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT8_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT8_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT8_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT8_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT8_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT8_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT8_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT8_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT8_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL5 0x0307 #define RTL8367C_PORT10_QUEUE7_TYPE_OFFSET 7 #define RTL8367C_PORT10_QUEUE7_TYPE_MASK 0x80 #define RTL8367C_PORT10_QUEUE6_TYPE_OFFSET 6 #define RTL8367C_PORT10_QUEUE6_TYPE_MASK 0x40 #define RTL8367C_PORT10_QUEUE5_TYPE_OFFSET 5 #define RTL8367C_PORT10_QUEUE5_TYPE_MASK 0x20 #define RTL8367C_PORT10_QUEUE4_TYPE_OFFSET 4 #define RTL8367C_PORT10_QUEUE4_TYPE_MASK 0x10 #define RTL8367C_PORT10_QUEUE3_TYPE_OFFSET 3 #define RTL8367C_PORT10_QUEUE3_TYPE_MASK 0x8 #define RTL8367C_PORT10_QUEUE2_TYPE_OFFSET 2 #define RTL8367C_PORT10_QUEUE2_TYPE_MASK 0x4 #define RTL8367C_PORT10_QUEUE1_TYPE_OFFSET 1 #define RTL8367C_PORT10_QUEUE1_TYPE_MASK 0x2 #define RTL8367C_PORT10_QUEUE0_TYPE_OFFSET 0 #define RTL8367C_PORT10_QUEUE0_TYPE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_APR_CTRL0 0x030a #define RTL8367C_PORT10_APR_ENABLE_OFFSET 10 #define RTL8367C_PORT10_APR_ENABLE_MASK 0x400 #define RTL8367C_PORT9_APR_ENABLE_OFFSET 9 #define RTL8367C_PORT9_APR_ENABLE_MASK 0x200 #define RTL8367C_PORT8_APR_ENABLE_OFFSET 8 #define RTL8367C_PORT8_APR_ENABLE_MASK 0x100 #define RTL8367C_PORT7_APR_ENABLE_OFFSET 7 #define RTL8367C_PORT7_APR_ENABLE_MASK 0x80 #define RTL8367C_PORT6_APR_ENABLE_OFFSET 6 #define RTL8367C_PORT6_APR_ENABLE_MASK 0x40 #define RTL8367C_PORT5_APR_ENABLE_OFFSET 5 #define RTL8367C_PORT5_APR_ENABLE_MASK 0x20 #define RTL8367C_PORT4_APR_ENABLE_OFFSET 4 #define RTL8367C_PORT4_APR_ENABLE_MASK 0x10 #define RTL8367C_PORT3_APR_ENABLE_OFFSET 3 #define RTL8367C_PORT3_APR_ENABLE_MASK 0x8 #define RTL8367C_PORT2_APR_ENABLE_OFFSET 2 #define RTL8367C_PORT2_APR_ENABLE_MASK 0x4 #define RTL8367C_PORT1_APR_ENABLE_OFFSET 1 #define RTL8367C_PORT1_APR_ENABLE_MASK 0x2 #define RTL8367C_PORT0_APR_ENABLE_OFFSET 0 #define RTL8367C_PORT0_APR_ENABLE_MASK 0x1 #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT 0x030c #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT 0x030d #define RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT 0x030e #define RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT 0x030f #define RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT 0x0310 #define RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT 0x0311 #define RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT 0x0312 #define RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT 0x0313 #define RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT 0x0314 #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT 0x0315 #define RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT 0x0316 #define RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT 0x0317 #define RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT 0x0318 #define RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT 0x0319 #define RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT 0x031a #define RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT 0x031b #define RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT 0x031c #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT 0x031d #define RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT 0x031e #define RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT 0x031f #define RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT 0x0320 #define RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT 0x0321 #define RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT 0x0322 #define RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT 0x0323 #define RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT 0x0324 #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT 0x0325 #define RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT 0x0326 #define RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT 0x0327 #define RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT 0x0328 #define RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT 0x0329 #define RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT 0x032a #define RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT 0x032b #define RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT 0x032c #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT 0x032d #define RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT 0x032e #define RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT 0x032f #define RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT 0x0330 #define RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT 0x0331 #define RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT 0x0332 #define RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT 0x0333 #define RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT 0x0334 #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT 0x0335 #define RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT 0x0336 #define RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT 0x0337 #define RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT 0x0338 #define RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT 0x0339 #define RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT 0x033a #define RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT 0x033b #define RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT 0x033c #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT 0x033d #define RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT 0x033e #define RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT 0x033f #define RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT 0x0340 #define RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT 0x0341 #define RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT 0x0342 #define RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT 0x0343 #define RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT 0x0344 #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT 0x0345 #define RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT 0x0346 #define RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT 0x0347 #define RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT 0x0348 #define RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT 0x0349 #define RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT 0x034a #define RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT 0x034b #define RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT 0x034c #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT 0x034d #define RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT 0x034e #define RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT 0x034f #define RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT 0x0350 #define RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT 0x0351 #define RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT 0x0352 #define RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT 0x0353 #define RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT 0x0354 #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT 0x0355 #define RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT 0x0356 #define RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT 0x0357 #define RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT 0x0358 #define RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT 0x0359 #define RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT 0x035a #define RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT 0x035b #define RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT 0x035c #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT 0x035d #define RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT 0x035e #define RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT 0x035f #define RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT 0x0360 #define RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT 0x0361 #define RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT 0x0362 #define RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT 0x0363 #define RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_MASK 0x7F #define RTL8367C_REG_PORT0_EGRESSBW_CTRL0 0x038c #define RTL8367C_REG_PORT0_EGRESSBW_CTRL1 0x038d #define RTL8367C_PORT0_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT0_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT1_EGRESSBW_CTRL0 0x038e #define RTL8367C_REG_PORT1_EGRESSBW_CTRL1 0x038f #define RTL8367C_PORT1_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT1_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT2_EGRESSBW_CTRL0 0x0390 #define RTL8367C_REG_PORT2_EGRESSBW_CTRL1 0x0391 #define RTL8367C_PORT2_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT2_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT3_EGRESSBW_CTRL0 0x0392 #define RTL8367C_REG_PORT3_EGRESSBW_CTRL1 0x0393 #define RTL8367C_PORT3_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT3_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT4_EGRESSBW_CTRL0 0x0394 #define RTL8367C_REG_PORT4_EGRESSBW_CTRL1 0x0395 #define RTL8367C_PORT4_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT4_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT5_EGRESSBW_CTRL0 0x0396 #define RTL8367C_REG_PORT5_EGRESSBW_CTRL1 0x0397 #define RTL8367C_PORT5_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT5_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT6_EGRESSBW_CTRL0 0x0398 #define RTL8367C_REG_PORT6_EGRESSBW_CTRL1 0x0399 #define RTL8367C_PORT6_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT6_EGRESSBW_CTRL1_MASK 0x7 #define RTL8367C_REG_PORT7_EGRESSBW_CTRL0 0x039a #define RTL8367C_REG_PORT7_EGRESSBW_CTRL1 0x039b #define RTL8367C_PORT7_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT7_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT8_EGRESSBW_CTRL0 0x039c #define RTL8367C_REG_PORT8_EGRESSBW_CTRL1 0x039d #define RTL8367C_PORT8_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT8_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_PORT9_EGRESSBW_CTRL0 0x039e #define RTL8367C_REG_PORT9_EGRESSBW_CTRL1 0x039f #define RTL8367C_PORT9_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT9_EGRESSBW_CTRL1_MASK 0x7 #define RTL8367C_REG_PORT10_EGRESSBW_CTRL0 0x03a0 #define RTL8367C_REG_PORT10_EGRESSBW_CTRL1 0x03a1 #define RTL8367C_PORT10_EGRESSBW_CTRL1_OFFSET 0 #define RTL8367C_PORT10_EGRESSBW_CTRL1_MASK 0x1 #define RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL0 0x03ac #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL1 0x03ad #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL0 0x03b0 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL1 0x03b1 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL0 0x03b4 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL1 0x03b5 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL0 0x03b8 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL1 0x03b9 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL0 0x03bc #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL1 0x03bd #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL0 0x03c0 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL1 0x03c1 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL0 0x03c4 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL1 0x03c5 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL0 0x03c8 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL1 0x03c9 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 0x03ca #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL1 0x03cb #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL0 0x03cc #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL1 0x03cd #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL0 0x03ce #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 #define RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL1 0x03cf #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 #define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 #define RTL8367C_REG_LINE_RATE_1G_L 0x03ec #define RTL8367C_REG_LINE_RATE_1G_H 0x03ed #define RTL8367C_LINE_RATE_1G_H_OFFSET 0 #define RTL8367C_LINE_RATE_1G_H_MASK 0x1 #define RTL8367C_REG_LINE_RATE_100_L 0x03ee #define RTL8367C_REG_LINE_RATE_100_H 0x03ef #define RTL8367C_LINE_RATE_100_H_OFFSET 0 #define RTL8367C_LINE_RATE_100_H_MASK 0x1 #define RTL8367C_REG_LINE_RATE_10_L 0x03f0 #define RTL8367C_REG_LINE_RATE_10_H 0x03f1 #define RTL8367C_LINE_RATE_10_H_OFFSET 0 #define RTL8367C_LINE_RATE_10_H_MASK 0x1 #define RTL8367C_REG_DUMMY_03f2 0x03f2 #define RTL8367C_REG_DUMMY_03f3 0x03f3 #define RTL8367C_REG_DUMMY_03f4 0x03f4 #define RTL8367C_REG_DUMMY_03f5 0x03f5 #define RTL8367C_REG_DUMMY_03f6 0x03f6 #define RTL8367C_REG_BYPASS_LINE_RATE 0x03f7 #define RTL8367C_BYPASS_PORT10_CONSTRAINT_OFFSET 5 #define RTL8367C_BYPASS_PORT10_CONSTRAINT_MASK 0x20 #define RTL8367C_BYPASS_PORT9_CONSTRAINT_OFFSET 4 #define RTL8367C_BYPASS_PORT9_CONSTRAINT_MASK 0x10 #define RTL8367C_BYPASS_PORT8_CONSTRAINT_OFFSET 3 #define RTL8367C_BYPASS_PORT8_CONSTRAINT_MASK 0x8 #define RTL8367C_BYPASS_PORT7_CONSTRAINT_OFFSET 2 #define RTL8367C_BYPASS_PORT7_CONSTRAINT_MASK 0x4 #define RTL8367C_BYPASS_PORT6_CONSTRAINT_OFFSET 1 #define RTL8367C_BYPASS_PORT6_CONSTRAINT_MASK 0x2 #define RTL8367C_BYPASS_PORT5_CONSTRAINT_OFFSET 0 #define RTL8367C_BYPASS_PORT5_CONSTRAINT_MASK 0x1 #define RTL8367C_REG_LINE_RATE_500_H 0x03f8 #define RTL8367C_LINE_RATE_500_H_OFFSET 0 #define RTL8367C_LINE_RATE_500_H_MASK 0x7 #define RTL8367C_REG_LINE_RATE_500_L 0x03f9 #define RTL8367C_REG_LINE_RATE_HSG_H 0x03fa #define RTL8367C_LINE_RATE_HSG_H_OFFSET 0 #define RTL8367C_LINE_RATE_HSG_H_MASK 0x7 #define RTL8367C_REG_LINE_RATE_HSG_L 0x03fb /* (16'h0500)table_reg */ #define RTL8367C_REG_TABLE_ACCESS_CTRL 0x0500 #define RTL8367C_TABLE_ACCESS_CTRL_SPA_OFFSET 8 #define RTL8367C_TABLE_ACCESS_CTRL_SPA_MASK 0xF00 #define RTL8367C_ACCESS_METHOD_OFFSET 4 #define RTL8367C_ACCESS_METHOD_MASK 0x70 #define RTL8367C_COMMAND_TYPE_OFFSET 3 #define RTL8367C_COMMAND_TYPE_MASK 0x8 #define RTL8367C_TABLE_TYPE_OFFSET 0 #define RTL8367C_TABLE_TYPE_MASK 0x7 #define RTL8367C_REG_TABLE_ACCESS_ADDR 0x0501 #define RTL8367C_TABLE_ACCESS_ADDR_OFFSET 0 #define RTL8367C_TABLE_ACCESS_ADDR_MASK 0x1FFF #define RTL8367C_REG_TABLE_LUT_ADDR 0x0502 #define RTL8367C_ADDRESS2_OFFSET 14 #define RTL8367C_ADDRESS2_MASK 0x4000 #define RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET 13 #define RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_MASK 0x2000 #define RTL8367C_HIT_STATUS_OFFSET 12 #define RTL8367C_HIT_STATUS_MASK 0x1000 #define RTL8367C_TABLE_LUT_ADDR_TYPE_OFFSET 11 #define RTL8367C_TABLE_LUT_ADDR_TYPE_MASK 0x800 #define RTL8367C_TABLE_LUT_ADDR_ADDRESS_OFFSET 0 #define RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK 0x7FF #define RTL8367C_REG_HSA_HSB_LATCH 0x0503 #define RTL8367C_LATCH_ALWAYS_OFFSET 15 #define RTL8367C_LATCH_ALWAYS_MASK 0x8000 #define RTL8367C_LATCH_FIRST_OFFSET 14 #define RTL8367C_LATCH_FIRST_MASK 0x4000 #define RTL8367C_SPA_EN_OFFSET 13 #define RTL8367C_SPA_EN_MASK 0x2000 #define RTL8367C_FORWARD_EN_OFFSET 12 #define RTL8367C_FORWARD_EN_MASK 0x1000 #define RTL8367C_REASON_EN_OFFSET 11 #define RTL8367C_REASON_EN_MASK 0x800 #define RTL8367C_HSA_HSB_LATCH_SPA_OFFSET 8 #define RTL8367C_HSA_HSB_LATCH_SPA_MASK 0x700 #define RTL8367C_FORWARD_OFFSET 6 #define RTL8367C_FORWARD_MASK 0xC0 #define RTL8367C_REASON_OFFSET 0 #define RTL8367C_REASON_MASK 0x3F #define RTL8367C_REG_HSA_HSB_LATCH2 0x0504 #define RTL8367C_HSA_HSB_LATCH2_Reserved_OFFSET 1 #define RTL8367C_HSA_HSB_LATCH2_Reserved_MASK 0xFFFE #define RTL8367C_SPA2_OFFSET 0 #define RTL8367C_SPA2_MASK 0x1 #define RTL8367C_REG_TABLE_WRITE_DATA0 0x0510 #define RTL8367C_REG_TABLE_WRITE_DATA1 0x0511 #define RTL8367C_REG_TABLE_WRITE_DATA2 0x0512 #define RTL8367C_REG_TABLE_WRITE_DATA3 0x0513 #define RTL8367C_REG_TABLE_WRITE_DATA4 0x0514 #define RTL8367C_REG_TABLE_WRITE_DATA5 0x0515 #define RTL8367C_REG_TABLE_WRITE_DATA6 0x0516 #define RTL8367C_REG_TABLE_WRITE_DATA7 0x0517 #define RTL8367C_REG_TABLE_WRITE_DATA8 0x0518 #define RTL8367C_REG_TABLE_WRITE_DATA9 0x0519 #define RTL8367C_TABLE_WRITE_DATA9_OFFSET 0 #define RTL8367C_TABLE_WRITE_DATA9_MASK 0xF #define RTL8367C_REG_TABLE_READ_DATA0 0x0520 #define RTL8367C_REG_TABLE_READ_DATA1 0x0521 #define RTL8367C_REG_TABLE_READ_DATA2 0x0522 #define RTL8367C_REG_TABLE_READ_DATA3 0x0523 #define RTL8367C_REG_TABLE_READ_DATA4 0x0524 #define RTL8367C_REG_TABLE_READ_DATA5 0x0525 #define RTL8367C_REG_TABLE_READ_DATA6 0x0526 #define RTL8367C_REG_TABLE_READ_DATA7 0x0527 #define RTL8367C_REG_TABLE_READ_DATA8 0x0528 #define RTL8367C_REG_TABLE_READ_DATA9 0x0529 #define RTL8367C_TABLE_READ_DATA9_OFFSET 0 #define RTL8367C_TABLE_READ_DATA9_MASK 0xF #define RTL8367C_REG_TBL_DUMMY00 0x0550 #define RTL8367C_REG_TBL_DUMMY01 0x0551 /* (16'h0600)acl_reg */ #define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL0 0x0600 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL1 0x0601 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL2 0x0602 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL3 0x0603 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL0 0x0604 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL1 0x0605 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL2 0x0606 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL3 0x0607 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL0 0x0608 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL1 0x0609 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL2 0x060a #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL3 0x060b #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL0 0x060c #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL1 0x060d #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL2 0x060e #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL3 0x060f #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL0 0x0610 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL1 0x0611 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL2 0x0612 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_MASK 0x7F #define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL3 0x0613 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_OFFSET 8 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_MASK 0x7F00 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_OFFSET 0 #define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_MASK 0x7F #define RTL8367C_REG_ACL_ACTION_CTRL0 0x0614 #define RTL8367C_OP1_NOT_OFFSET 14 #define RTL8367C_OP1_NOT_MASK 0x4000 #define RTL8367C_ACT1_GPIO_OFFSET 13 #define RTL8367C_ACT1_GPIO_MASK 0x2000 #define RTL8367C_ACT1_FORWARD_OFFSET 12 #define RTL8367C_ACT1_FORWARD_MASK 0x1000 #define RTL8367C_ACT1_POLICING_OFFSET 11 #define RTL8367C_ACT1_POLICING_MASK 0x800 #define RTL8367C_ACT1_PRIORITY_OFFSET 10 #define RTL8367C_ACT1_PRIORITY_MASK 0x400 #define RTL8367C_ACT1_SVID_OFFSET 9 #define RTL8367C_ACT1_SVID_MASK 0x200 #define RTL8367C_ACT1_CVID_OFFSET 8 #define RTL8367C_ACT1_CVID_MASK 0x100 #define RTL8367C_OP0_NOT_OFFSET 6 #define RTL8367C_OP0_NOT_MASK 0x40 #define RTL8367C_ACT0_GPIO_OFFSET 5 #define RTL8367C_ACT0_GPIO_MASK 0x20 #define RTL8367C_ACT0_FORWARD_OFFSET 4 #define RTL8367C_ACT0_FORWARD_MASK 0x10 #define RTL8367C_ACT0_POLICING_OFFSET 3 #define RTL8367C_ACT0_POLICING_MASK 0x8 #define RTL8367C_ACT0_PRIORITY_OFFSET 2 #define RTL8367C_ACT0_PRIORITY_MASK 0x4 #define RTL8367C_ACT0_SVID_OFFSET 1 #define RTL8367C_ACT0_SVID_MASK 0x2 #define RTL8367C_ACT0_CVID_OFFSET 0 #define RTL8367C_ACT0_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL1 0x0615 #define RTL8367C_OP3_NOT_OFFSET 14 #define RTL8367C_OP3_NOT_MASK 0x4000 #define RTL8367C_ACT3_GPIO_OFFSET 13 #define RTL8367C_ACT3_GPIO_MASK 0x2000 #define RTL8367C_ACT3_FORWARD_OFFSET 12 #define RTL8367C_ACT3_FORWARD_MASK 0x1000 #define RTL8367C_ACT3_POLICING_OFFSET 11 #define RTL8367C_ACT3_POLICING_MASK 0x800 #define RTL8367C_ACT3_PRIORITY_OFFSET 10 #define RTL8367C_ACT3_PRIORITY_MASK 0x400 #define RTL8367C_ACT3_SVID_OFFSET 9 #define RTL8367C_ACT3_SVID_MASK 0x200 #define RTL8367C_ACT3_CVID_OFFSET 8 #define RTL8367C_ACT3_CVID_MASK 0x100 #define RTL8367C_OP2_NOT_OFFSET 6 #define RTL8367C_OP2_NOT_MASK 0x40 #define RTL8367C_ACT2_GPIO_OFFSET 5 #define RTL8367C_ACT2_GPIO_MASK 0x20 #define RTL8367C_ACT2_FORWARD_OFFSET 4 #define RTL8367C_ACT2_FORWARD_MASK 0x10 #define RTL8367C_ACT2_POLICING_OFFSET 3 #define RTL8367C_ACT2_POLICING_MASK 0x8 #define RTL8367C_ACT2_PRIORITY_OFFSET 2 #define RTL8367C_ACT2_PRIORITY_MASK 0x4 #define RTL8367C_ACT2_SVID_OFFSET 1 #define RTL8367C_ACT2_SVID_MASK 0x2 #define RTL8367C_ACT2_CVID_OFFSET 0 #define RTL8367C_ACT2_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL2 0x0616 #define RTL8367C_OP5_NOT_OFFSET 14 #define RTL8367C_OP5_NOT_MASK 0x4000 #define RTL8367C_ACT5_GPIO_OFFSET 13 #define RTL8367C_ACT5_GPIO_MASK 0x2000 #define RTL8367C_ACT5_FORWARD_OFFSET 12 #define RTL8367C_ACT5_FORWARD_MASK 0x1000 #define RTL8367C_ACT5_POLICING_OFFSET 11 #define RTL8367C_ACT5_POLICING_MASK 0x800 #define RTL8367C_ACT5_PRIORITY_OFFSET 10 #define RTL8367C_ACT5_PRIORITY_MASK 0x400 #define RTL8367C_ACT5_SVID_OFFSET 9 #define RTL8367C_ACT5_SVID_MASK 0x200 #define RTL8367C_ACT5_CVID_OFFSET 8 #define RTL8367C_ACT5_CVID_MASK 0x100 #define RTL8367C_OP4_NOT_OFFSET 6 #define RTL8367C_OP4_NOT_MASK 0x40 #define RTL8367C_ACT4_GPIO_OFFSET 5 #define RTL8367C_ACT4_GPIO_MASK 0x20 #define RTL8367C_ACT4_FORWARD_OFFSET 4 #define RTL8367C_ACT4_FORWARD_MASK 0x10 #define RTL8367C_ACT4_POLICING_OFFSET 3 #define RTL8367C_ACT4_POLICING_MASK 0x8 #define RTL8367C_ACT4_PRIORITY_OFFSET 2 #define RTL8367C_ACT4_PRIORITY_MASK 0x4 #define RTL8367C_ACT4_SVID_OFFSET 1 #define RTL8367C_ACT4_SVID_MASK 0x2 #define RTL8367C_ACT4_CVID_OFFSET 0 #define RTL8367C_ACT4_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL3 0x0617 #define RTL8367C_OP7_NOT_OFFSET 14 #define RTL8367C_OP7_NOT_MASK 0x4000 #define RTL8367C_ACT7_GPIO_OFFSET 13 #define RTL8367C_ACT7_GPIO_MASK 0x2000 #define RTL8367C_ACT7_FORWARD_OFFSET 12 #define RTL8367C_ACT7_FORWARD_MASK 0x1000 #define RTL8367C_ACT7_POLICING_OFFSET 11 #define RTL8367C_ACT7_POLICING_MASK 0x800 #define RTL8367C_ACT7_PRIORITY_OFFSET 10 #define RTL8367C_ACT7_PRIORITY_MASK 0x400 #define RTL8367C_ACT7_SVID_OFFSET 9 #define RTL8367C_ACT7_SVID_MASK 0x200 #define RTL8367C_ACT7_CVID_OFFSET 8 #define RTL8367C_ACT7_CVID_MASK 0x100 #define RTL8367C_OP6_NOT_OFFSET 6 #define RTL8367C_OP6_NOT_MASK 0x40 #define RTL8367C_ACT6_GPIO_OFFSET 5 #define RTL8367C_ACT6_GPIO_MASK 0x20 #define RTL8367C_ACT6_FORWARD_OFFSET 4 #define RTL8367C_ACT6_FORWARD_MASK 0x10 #define RTL8367C_ACT6_POLICING_OFFSET 3 #define RTL8367C_ACT6_POLICING_MASK 0x8 #define RTL8367C_ACT6_PRIORITY_OFFSET 2 #define RTL8367C_ACT6_PRIORITY_MASK 0x4 #define RTL8367C_ACT6_SVID_OFFSET 1 #define RTL8367C_ACT6_SVID_MASK 0x2 #define RTL8367C_ACT6_CVID_OFFSET 0 #define RTL8367C_ACT6_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL4 0x0618 #define RTL8367C_OP9_NOT_OFFSET 14 #define RTL8367C_OP9_NOT_MASK 0x4000 #define RTL8367C_ACT9_GPIO_OFFSET 13 #define RTL8367C_ACT9_GPIO_MASK 0x2000 #define RTL8367C_ACT9_FORWARD_OFFSET 12 #define RTL8367C_ACT9_FORWARD_MASK 0x1000 #define RTL8367C_ACT9_POLICING_OFFSET 11 #define RTL8367C_ACT9_POLICING_MASK 0x800 #define RTL8367C_ACT9_PRIORITY_OFFSET 10 #define RTL8367C_ACT9_PRIORITY_MASK 0x400 #define RTL8367C_ACT9_SVID_OFFSET 9 #define RTL8367C_ACT9_SVID_MASK 0x200 #define RTL8367C_ACT9_CVID_OFFSET 8 #define RTL8367C_ACT9_CVID_MASK 0x100 #define RTL8367C_OP8_NOT_OFFSET 6 #define RTL8367C_OP8_NOT_MASK 0x40 #define RTL8367C_ACT8_GPIO_OFFSET 5 #define RTL8367C_ACT8_GPIO_MASK 0x20 #define RTL8367C_ACT8_FORWARD_OFFSET 4 #define RTL8367C_ACT8_FORWARD_MASK 0x10 #define RTL8367C_ACT8_POLICING_OFFSET 3 #define RTL8367C_ACT8_POLICING_MASK 0x8 #define RTL8367C_ACT8_PRIORITY_OFFSET 2 #define RTL8367C_ACT8_PRIORITY_MASK 0x4 #define RTL8367C_ACT8_SVID_OFFSET 1 #define RTL8367C_ACT8_SVID_MASK 0x2 #define RTL8367C_ACT8_CVID_OFFSET 0 #define RTL8367C_ACT8_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL5 0x0619 #define RTL8367C_OP11_NOT_OFFSET 14 #define RTL8367C_OP11_NOT_MASK 0x4000 #define RTL8367C_ACT11_GPIO_OFFSET 13 #define RTL8367C_ACT11_GPIO_MASK 0x2000 #define RTL8367C_ACT11_FORWARD_OFFSET 12 #define RTL8367C_ACT11_FORWARD_MASK 0x1000 #define RTL8367C_ACT11_POLICING_OFFSET 11 #define RTL8367C_ACT11_POLICING_MASK 0x800 #define RTL8367C_ACT11_PRIORITY_OFFSET 10 #define RTL8367C_ACT11_PRIORITY_MASK 0x400 #define RTL8367C_ACT11_SVID_OFFSET 9 #define RTL8367C_ACT11_SVID_MASK 0x200 #define RTL8367C_ACT11_CVID_OFFSET 8 #define RTL8367C_ACT11_CVID_MASK 0x100 #define RTL8367C_OP10_NOT_OFFSET 6 #define RTL8367C_OP10_NOT_MASK 0x40 #define RTL8367C_ACT10_GPIO_OFFSET 5 #define RTL8367C_ACT10_GPIO_MASK 0x20 #define RTL8367C_ACT10_FORWARD_OFFSET 4 #define RTL8367C_ACT10_FORWARD_MASK 0x10 #define RTL8367C_ACT10_POLICING_OFFSET 3 #define RTL8367C_ACT10_POLICING_MASK 0x8 #define RTL8367C_ACT10_PRIORITY_OFFSET 2 #define RTL8367C_ACT10_PRIORITY_MASK 0x4 #define RTL8367C_ACT10_SVID_OFFSET 1 #define RTL8367C_ACT10_SVID_MASK 0x2 #define RTL8367C_ACT10_CVID_OFFSET 0 #define RTL8367C_ACT10_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL6 0x061a #define RTL8367C_OP13_NOT_OFFSET 14 #define RTL8367C_OP13_NOT_MASK 0x4000 #define RTL8367C_ACT13_GPIO_OFFSET 13 #define RTL8367C_ACT13_GPIO_MASK 0x2000 #define RTL8367C_ACT13_FORWARD_OFFSET 12 #define RTL8367C_ACT13_FORWARD_MASK 0x1000 #define RTL8367C_ACT13_POLICING_OFFSET 11 #define RTL8367C_ACT13_POLICING_MASK 0x800 #define RTL8367C_ACT13_PRIORITY_OFFSET 10 #define RTL8367C_ACT13_PRIORITY_MASK 0x400 #define RTL8367C_ACT13_SVID_OFFSET 9 #define RTL8367C_ACT13_SVID_MASK 0x200 #define RTL8367C_ACT13_CVID_OFFSET 8 #define RTL8367C_ACT13_CVID_MASK 0x100 #define RTL8367C_OP12_NOT_OFFSET 6 #define RTL8367C_OP12_NOT_MASK 0x40 #define RTL8367C_ACT12_GPIO_OFFSET 5 #define RTL8367C_ACT12_GPIO_MASK 0x20 #define RTL8367C_ACT12_FORWARD_OFFSET 4 #define RTL8367C_ACT12_FORWARD_MASK 0x10 #define RTL8367C_ACT12_POLICING_OFFSET 3 #define RTL8367C_ACT12_POLICING_MASK 0x8 #define RTL8367C_ACT12_PRIORITY_OFFSET 2 #define RTL8367C_ACT12_PRIORITY_MASK 0x4 #define RTL8367C_ACT12_SVID_OFFSET 1 #define RTL8367C_ACT12_SVID_MASK 0x2 #define RTL8367C_ACT12_CVID_OFFSET 0 #define RTL8367C_ACT12_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL7 0x061b #define RTL8367C_OP15_NOT_OFFSET 14 #define RTL8367C_OP15_NOT_MASK 0x4000 #define RTL8367C_ACT15_GPIO_OFFSET 13 #define RTL8367C_ACT15_GPIO_MASK 0x2000 #define RTL8367C_ACT15_FORWARD_OFFSET 12 #define RTL8367C_ACT15_FORWARD_MASK 0x1000 #define RTL8367C_ACT15_POLICING_OFFSET 11 #define RTL8367C_ACT15_POLICING_MASK 0x800 #define RTL8367C_ACT15_PRIORITY_OFFSET 10 #define RTL8367C_ACT15_PRIORITY_MASK 0x400 #define RTL8367C_ACT15_SVID_OFFSET 9 #define RTL8367C_ACT15_SVID_MASK 0x200 #define RTL8367C_ACT15_CVID_OFFSET 8 #define RTL8367C_ACT15_CVID_MASK 0x100 #define RTL8367C_OP14_NOT_OFFSET 6 #define RTL8367C_OP14_NOT_MASK 0x40 #define RTL8367C_ACT14_GPIO_OFFSET 5 #define RTL8367C_ACT14_GPIO_MASK 0x20 #define RTL8367C_ACT14_FORWARD_OFFSET 4 #define RTL8367C_ACT14_FORWARD_MASK 0x10 #define RTL8367C_ACT14_POLICING_OFFSET 3 #define RTL8367C_ACT14_POLICING_MASK 0x8 #define RTL8367C_ACT14_PRIORITY_OFFSET 2 #define RTL8367C_ACT14_PRIORITY_MASK 0x4 #define RTL8367C_ACT14_SVID_OFFSET 1 #define RTL8367C_ACT14_SVID_MASK 0x2 #define RTL8367C_ACT14_CVID_OFFSET 0 #define RTL8367C_ACT14_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL8 0x061c #define RTL8367C_OP17_NOT_OFFSET 14 #define RTL8367C_OP17_NOT_MASK 0x4000 #define RTL8367C_ACT17_GPIO_OFFSET 13 #define RTL8367C_ACT17_GPIO_MASK 0x2000 #define RTL8367C_ACT17_FORWARD_OFFSET 12 #define RTL8367C_ACT17_FORWARD_MASK 0x1000 #define RTL8367C_ACT17_POLICING_OFFSET 11 #define RTL8367C_ACT17_POLICING_MASK 0x800 #define RTL8367C_ACT17_PRIORITY_OFFSET 10 #define RTL8367C_ACT17_PRIORITY_MASK 0x400 #define RTL8367C_ACT17_SVID_OFFSET 9 #define RTL8367C_ACT17_SVID_MASK 0x200 #define RTL8367C_ACT17_CVID_OFFSET 8 #define RTL8367C_ACT17_CVID_MASK 0x100 #define RTL8367C_OP16_NOT_OFFSET 6 #define RTL8367C_OP16_NOT_MASK 0x40 #define RTL8367C_ACT16_GPIO_OFFSET 5 #define RTL8367C_ACT16_GPIO_MASK 0x20 #define RTL8367C_ACT16_FORWARD_OFFSET 4 #define RTL8367C_ACT16_FORWARD_MASK 0x10 #define RTL8367C_ACT16_POLICING_OFFSET 3 #define RTL8367C_ACT16_POLICING_MASK 0x8 #define RTL8367C_ACT16_PRIORITY_OFFSET 2 #define RTL8367C_ACT16_PRIORITY_MASK 0x4 #define RTL8367C_ACT16_SVID_OFFSET 1 #define RTL8367C_ACT16_SVID_MASK 0x2 #define RTL8367C_ACT16_CVID_OFFSET 0 #define RTL8367C_ACT16_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL9 0x061d #define RTL8367C_OP19_NOT_OFFSET 14 #define RTL8367C_OP19_NOT_MASK 0x4000 #define RTL8367C_ACT19_GPIO_OFFSET 13 #define RTL8367C_ACT19_GPIO_MASK 0x2000 #define RTL8367C_ACT19_FORWARD_OFFSET 12 #define RTL8367C_ACT19_FORWARD_MASK 0x1000 #define RTL8367C_ACT19_POLICING_OFFSET 11 #define RTL8367C_ACT19_POLICING_MASK 0x800 #define RTL8367C_ACT19_PRIORITY_OFFSET 10 #define RTL8367C_ACT19_PRIORITY_MASK 0x400 #define RTL8367C_ACT19_SVID_OFFSET 9 #define RTL8367C_ACT19_SVID_MASK 0x200 #define RTL8367C_ACT19_CVID_OFFSET 8 #define RTL8367C_ACT19_CVID_MASK 0x100 #define RTL8367C_OP18_NOT_OFFSET 6 #define RTL8367C_OP18_NOT_MASK 0x40 #define RTL8367C_ACT18_GPIO_OFFSET 5 #define RTL8367C_ACT18_GPIO_MASK 0x20 #define RTL8367C_ACT18_FORWARD_OFFSET 4 #define RTL8367C_ACT18_FORWARD_MASK 0x10 #define RTL8367C_ACT18_POLICING_OFFSET 3 #define RTL8367C_ACT18_POLICING_MASK 0x8 #define RTL8367C_ACT18_PRIORITY_OFFSET 2 #define RTL8367C_ACT18_PRIORITY_MASK 0x4 #define RTL8367C_ACT18_SVID_OFFSET 1 #define RTL8367C_ACT18_SVID_MASK 0x2 #define RTL8367C_ACT18_CVID_OFFSET 0 #define RTL8367C_ACT18_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL10 0x061e #define RTL8367C_OP21_NOT_OFFSET 14 #define RTL8367C_OP21_NOT_MASK 0x4000 #define RTL8367C_ACT21_GPIO_OFFSET 13 #define RTL8367C_ACT21_GPIO_MASK 0x2000 #define RTL8367C_ACT21_FORWARD_OFFSET 12 #define RTL8367C_ACT21_FORWARD_MASK 0x1000 #define RTL8367C_ACT21_POLICING_OFFSET 11 #define RTL8367C_ACT21_POLICING_MASK 0x800 #define RTL8367C_ACT21_PRIORITY_OFFSET 10 #define RTL8367C_ACT21_PRIORITY_MASK 0x400 #define RTL8367C_ACT21_SVID_OFFSET 9 #define RTL8367C_ACT21_SVID_MASK 0x200 #define RTL8367C_ACT21_CVID_OFFSET 8 #define RTL8367C_ACT21_CVID_MASK 0x100 #define RTL8367C_OP20_NOT_OFFSET 6 #define RTL8367C_OP20_NOT_MASK 0x40 #define RTL8367C_ACT20_GPIO_OFFSET 5 #define RTL8367C_ACT20_GPIO_MASK 0x20 #define RTL8367C_ACT20_FORWARD_OFFSET 4 #define RTL8367C_ACT20_FORWARD_MASK 0x10 #define RTL8367C_ACT20_POLICING_OFFSET 3 #define RTL8367C_ACT20_POLICING_MASK 0x8 #define RTL8367C_ACT20_PRIORITY_OFFSET 2 #define RTL8367C_ACT20_PRIORITY_MASK 0x4 #define RTL8367C_ACT20_SVID_OFFSET 1 #define RTL8367C_ACT20_SVID_MASK 0x2 #define RTL8367C_ACT20_CVID_OFFSET 0 #define RTL8367C_ACT20_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL11 0x061f #define RTL8367C_OP23_NOT_OFFSET 14 #define RTL8367C_OP23_NOT_MASK 0x4000 #define RTL8367C_ACT23_GPIO_OFFSET 13 #define RTL8367C_ACT23_GPIO_MASK 0x2000 #define RTL8367C_ACT23_FORWARD_OFFSET 12 #define RTL8367C_ACT23_FORWARD_MASK 0x1000 #define RTL8367C_ACT23_POLICING_OFFSET 11 #define RTL8367C_ACT23_POLICING_MASK 0x800 #define RTL8367C_ACT23_PRIORITY_OFFSET 10 #define RTL8367C_ACT23_PRIORITY_MASK 0x400 #define RTL8367C_ACT23_SVID_OFFSET 9 #define RTL8367C_ACT23_SVID_MASK 0x200 #define RTL8367C_ACT23_CVID_OFFSET 8 #define RTL8367C_ACT23_CVID_MASK 0x100 #define RTL8367C_OP22_NOT_OFFSET 6 #define RTL8367C_OP22_NOT_MASK 0x40 #define RTL8367C_ACT22_GPIO_OFFSET 5 #define RTL8367C_ACT22_GPIO_MASK 0x20 #define RTL8367C_ACT22_FORWARD_OFFSET 4 #define RTL8367C_ACT22_FORWARD_MASK 0x10 #define RTL8367C_ACT22_POLICING_OFFSET 3 #define RTL8367C_ACT22_POLICING_MASK 0x8 #define RTL8367C_ACT22_PRIORITY_OFFSET 2 #define RTL8367C_ACT22_PRIORITY_MASK 0x4 #define RTL8367C_ACT22_SVID_OFFSET 1 #define RTL8367C_ACT22_SVID_MASK 0x2 #define RTL8367C_ACT22_CVID_OFFSET 0 #define RTL8367C_ACT22_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL12 0x0620 #define RTL8367C_OP25_NOT_OFFSET 14 #define RTL8367C_OP25_NOT_MASK 0x4000 #define RTL8367C_ACT25_GPIO_OFFSET 13 #define RTL8367C_ACT25_GPIO_MASK 0x2000 #define RTL8367C_ACT25_FORWARD_OFFSET 12 #define RTL8367C_ACT25_FORWARD_MASK 0x1000 #define RTL8367C_ACT25_POLICING_OFFSET 11 #define RTL8367C_ACT25_POLICING_MASK 0x800 #define RTL8367C_ACT25_PRIORITY_OFFSET 10 #define RTL8367C_ACT25_PRIORITY_MASK 0x400 #define RTL8367C_ACT25_SVID_OFFSET 9 #define RTL8367C_ACT25_SVID_MASK 0x200 #define RTL8367C_ACT25_CVID_OFFSET 8 #define RTL8367C_ACT25_CVID_MASK 0x100 #define RTL8367C_OP24_NOT_OFFSET 6 #define RTL8367C_OP24_NOT_MASK 0x40 #define RTL8367C_ACT24_GPIO_OFFSET 5 #define RTL8367C_ACT24_GPIO_MASK 0x20 #define RTL8367C_ACT24_FORWARD_OFFSET 4 #define RTL8367C_ACT24_FORWARD_MASK 0x10 #define RTL8367C_ACT24_POLICING_OFFSET 3 #define RTL8367C_ACT24_POLICING_MASK 0x8 #define RTL8367C_ACT24_PRIORITY_OFFSET 2 #define RTL8367C_ACT24_PRIORITY_MASK 0x4 #define RTL8367C_ACT24_SVID_OFFSET 1 #define RTL8367C_ACT24_SVID_MASK 0x2 #define RTL8367C_ACT24_CVID_OFFSET 0 #define RTL8367C_ACT24_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL13 0x0621 #define RTL8367C_OP27_NOT_OFFSET 14 #define RTL8367C_OP27_NOT_MASK 0x4000 #define RTL8367C_ACT27_GPIO_OFFSET 13 #define RTL8367C_ACT27_GPIO_MASK 0x2000 #define RTL8367C_ACT27_FORWARD_OFFSET 12 #define RTL8367C_ACT27_FORWARD_MASK 0x1000 #define RTL8367C_ACT27_POLICING_OFFSET 11 #define RTL8367C_ACT27_POLICING_MASK 0x800 #define RTL8367C_ACT27_PRIORITY_OFFSET 10 #define RTL8367C_ACT27_PRIORITY_MASK 0x400 #define RTL8367C_ACT27_SVID_OFFSET 9 #define RTL8367C_ACT27_SVID_MASK 0x200 #define RTL8367C_ACT27_CVID_OFFSET 8 #define RTL8367C_ACT27_CVID_MASK 0x100 #define RTL8367C_OP26_NOT_OFFSET 6 #define RTL8367C_OP26_NOT_MASK 0x40 #define RTL8367C_ACT26_GPIO_OFFSET 5 #define RTL8367C_ACT26_GPIO_MASK 0x20 #define RTL8367C_ACT26_FORWARD_OFFSET 4 #define RTL8367C_ACT26_FORWARD_MASK 0x10 #define RTL8367C_ACT26_POLICING_OFFSET 3 #define RTL8367C_ACT26_POLICING_MASK 0x8 #define RTL8367C_ACT26_PRIORITY_OFFSET 2 #define RTL8367C_ACT26_PRIORITY_MASK 0x4 #define RTL8367C_ACT26_SVID_OFFSET 1 #define RTL8367C_ACT26_SVID_MASK 0x2 #define RTL8367C_ACT26_CVID_OFFSET 0 #define RTL8367C_ACT26_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL14 0x0622 #define RTL8367C_OP29_NOT_OFFSET 14 #define RTL8367C_OP29_NOT_MASK 0x4000 #define RTL8367C_ACT29_GPIO_OFFSET 13 #define RTL8367C_ACT29_GPIO_MASK 0x2000 #define RTL8367C_ACT29_FORWARD_OFFSET 12 #define RTL8367C_ACT29_FORWARD_MASK 0x1000 #define RTL8367C_ACT29_POLICING_OFFSET 11 #define RTL8367C_ACT29_POLICING_MASK 0x800 #define RTL8367C_ACT29_PRIORITY_OFFSET 10 #define RTL8367C_ACT29_PRIORITY_MASK 0x400 #define RTL8367C_ACT29_SVID_OFFSET 9 #define RTL8367C_ACT29_SVID_MASK 0x200 #define RTL8367C_ACT29_CVID_OFFSET 8 #define RTL8367C_ACT29_CVID_MASK 0x100 #define RTL8367C_OP28_NOT_OFFSET 6 #define RTL8367C_OP28_NOT_MASK 0x40 #define RTL8367C_ACT28_GPIO_OFFSET 5 #define RTL8367C_ACT28_GPIO_MASK 0x20 #define RTL8367C_ACT28_FORWARD_OFFSET 4 #define RTL8367C_ACT28_FORWARD_MASK 0x10 #define RTL8367C_ACT28_POLICING_OFFSET 3 #define RTL8367C_ACT28_POLICING_MASK 0x8 #define RTL8367C_ACT28_PRIORITY_OFFSET 2 #define RTL8367C_ACT28_PRIORITY_MASK 0x4 #define RTL8367C_ACT28_SVID_OFFSET 1 #define RTL8367C_ACT28_SVID_MASK 0x2 #define RTL8367C_ACT28_CVID_OFFSET 0 #define RTL8367C_ACT28_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL15 0x0623 #define RTL8367C_OP31_NOT_OFFSET 14 #define RTL8367C_OP31_NOT_MASK 0x4000 #define RTL8367C_ACT31_GPIO_OFFSET 13 #define RTL8367C_ACT31_GPIO_MASK 0x2000 #define RTL8367C_ACT31_FORWARD_OFFSET 12 #define RTL8367C_ACT31_FORWARD_MASK 0x1000 #define RTL8367C_ACT31_POLICING_OFFSET 11 #define RTL8367C_ACT31_POLICING_MASK 0x800 #define RTL8367C_ACT31_PRIORITY_OFFSET 10 #define RTL8367C_ACT31_PRIORITY_MASK 0x400 #define RTL8367C_ACT31_SVID_OFFSET 9 #define RTL8367C_ACT31_SVID_MASK 0x200 #define RTL8367C_ACT31_CVID_OFFSET 8 #define RTL8367C_ACT31_CVID_MASK 0x100 #define RTL8367C_OP30_NOT_OFFSET 6 #define RTL8367C_OP30_NOT_MASK 0x40 #define RTL8367C_ACT30_GPIO_OFFSET 5 #define RTL8367C_ACT30_GPIO_MASK 0x20 #define RTL8367C_ACT30_FORWARD_OFFSET 4 #define RTL8367C_ACT30_FORWARD_MASK 0x10 #define RTL8367C_ACT30_POLICING_OFFSET 3 #define RTL8367C_ACT30_POLICING_MASK 0x8 #define RTL8367C_ACT30_PRIORITY_OFFSET 2 #define RTL8367C_ACT30_PRIORITY_MASK 0x4 #define RTL8367C_ACT30_SVID_OFFSET 1 #define RTL8367C_ACT30_SVID_MASK 0x2 #define RTL8367C_ACT30_CVID_OFFSET 0 #define RTL8367C_ACT30_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL16 0x0624 #define RTL8367C_OP33_NOT_OFFSET 14 #define RTL8367C_OP33_NOT_MASK 0x4000 #define RTL8367C_ACT33_GPIO_OFFSET 13 #define RTL8367C_ACT33_GPIO_MASK 0x2000 #define RTL8367C_ACT33_FORWARD_OFFSET 12 #define RTL8367C_ACT33_FORWARD_MASK 0x1000 #define RTL8367C_ACT33_POLICING_OFFSET 11 #define RTL8367C_ACT33_POLICING_MASK 0x800 #define RTL8367C_ACT33_PRIORITY_OFFSET 10 #define RTL8367C_ACT33_PRIORITY_MASK 0x400 #define RTL8367C_ACT33_SVID_OFFSET 9 #define RTL8367C_ACT33_SVID_MASK 0x200 #define RTL8367C_ACT33_CVID_OFFSET 8 #define RTL8367C_ACT33_CVID_MASK 0x100 #define RTL8367C_OP32_NOT_OFFSET 6 #define RTL8367C_OP32_NOT_MASK 0x40 #define RTL8367C_ACT32_GPIO_OFFSET 5 #define RTL8367C_ACT32_GPIO_MASK 0x20 #define RTL8367C_ACT32_FORWARD_OFFSET 4 #define RTL8367C_ACT32_FORWARD_MASK 0x10 #define RTL8367C_ACT32_POLICING_OFFSET 3 #define RTL8367C_ACT32_POLICING_MASK 0x8 #define RTL8367C_ACT32_PRIORITY_OFFSET 2 #define RTL8367C_ACT32_PRIORITY_MASK 0x4 #define RTL8367C_ACT32_SVID_OFFSET 1 #define RTL8367C_ACT32_SVID_MASK 0x2 #define RTL8367C_ACT32_CVID_OFFSET 0 #define RTL8367C_ACT32_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL17 0x0625 #define RTL8367C_OP35_NOT_OFFSET 14 #define RTL8367C_OP35_NOT_MASK 0x4000 #define RTL8367C_ACT35_GPIO_OFFSET 13 #define RTL8367C_ACT35_GPIO_MASK 0x2000 #define RTL8367C_ACT35_FORWARD_OFFSET 12 #define RTL8367C_ACT35_FORWARD_MASK 0x1000 #define RTL8367C_ACT35_POLICING_OFFSET 11 #define RTL8367C_ACT35_POLICING_MASK 0x800 #define RTL8367C_ACT35_PRIORITY_OFFSET 10 #define RTL8367C_ACT35_PRIORITY_MASK 0x400 #define RTL8367C_ACT35_SVID_OFFSET 9 #define RTL8367C_ACT35_SVID_MASK 0x200 #define RTL8367C_ACT35_CVID_OFFSET 8 #define RTL8367C_ACT35_CVID_MASK 0x100 #define RTL8367C_OP34_NOT_OFFSET 6 #define RTL8367C_OP34_NOT_MASK 0x40 #define RTL8367C_ACT34_GPIO_OFFSET 5 #define RTL8367C_ACT34_GPIO_MASK 0x20 #define RTL8367C_ACT34_FORWARD_OFFSET 4 #define RTL8367C_ACT34_FORWARD_MASK 0x10 #define RTL8367C_ACT34_POLICING_OFFSET 3 #define RTL8367C_ACT34_POLICING_MASK 0x8 #define RTL8367C_ACT34_PRIORITY_OFFSET 2 #define RTL8367C_ACT34_PRIORITY_MASK 0x4 #define RTL8367C_ACT34_SVID_OFFSET 1 #define RTL8367C_ACT34_SVID_MASK 0x2 #define RTL8367C_ACT34_CVID_OFFSET 0 #define RTL8367C_ACT34_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL18 0x0626 #define RTL8367C_OP37_NOT_OFFSET 14 #define RTL8367C_OP37_NOT_MASK 0x4000 #define RTL8367C_ACT37_GPIO_OFFSET 13 #define RTL8367C_ACT37_GPIO_MASK 0x2000 #define RTL8367C_ACT37_FORWARD_OFFSET 12 #define RTL8367C_ACT37_FORWARD_MASK 0x1000 #define RTL8367C_ACT37_POLICING_OFFSET 11 #define RTL8367C_ACT37_POLICING_MASK 0x800 #define RTL8367C_ACT37_PRIORITY_OFFSET 10 #define RTL8367C_ACT37_PRIORITY_MASK 0x400 #define RTL8367C_ACT37_SVID_OFFSET 9 #define RTL8367C_ACT37_SVID_MASK 0x200 #define RTL8367C_ACT37_CVID_OFFSET 8 #define RTL8367C_ACT37_CVID_MASK 0x100 #define RTL8367C_OP36_NOT_OFFSET 6 #define RTL8367C_OP36_NOT_MASK 0x40 #define RTL8367C_ACT36_GPIO_OFFSET 5 #define RTL8367C_ACT36_GPIO_MASK 0x20 #define RTL8367C_ACT36_FORWARD_OFFSET 4 #define RTL8367C_ACT36_FORWARD_MASK 0x10 #define RTL8367C_ACT36_POLICING_OFFSET 3 #define RTL8367C_ACT36_POLICING_MASK 0x8 #define RTL8367C_ACT36_PRIORITY_OFFSET 2 #define RTL8367C_ACT36_PRIORITY_MASK 0x4 #define RTL8367C_ACT36_SVID_OFFSET 1 #define RTL8367C_ACT36_SVID_MASK 0x2 #define RTL8367C_ACT36_CVID_OFFSET 0 #define RTL8367C_ACT36_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL19 0x0627 #define RTL8367C_OP39_NOT_OFFSET 14 #define RTL8367C_OP39_NOT_MASK 0x4000 #define RTL8367C_ACT39_GPIO_OFFSET 13 #define RTL8367C_ACT39_GPIO_MASK 0x2000 #define RTL8367C_ACT39_FORWARD_OFFSET 12 #define RTL8367C_ACT39_FORWARD_MASK 0x1000 #define RTL8367C_ACT39_POLICING_OFFSET 11 #define RTL8367C_ACT39_POLICING_MASK 0x800 #define RTL8367C_ACT39_PRIORITY_OFFSET 10 #define RTL8367C_ACT39_PRIORITY_MASK 0x400 #define RTL8367C_ACT39_SVID_OFFSET 9 #define RTL8367C_ACT39_SVID_MASK 0x200 #define RTL8367C_ACT39_CVID_OFFSET 8 #define RTL8367C_ACT39_CVID_MASK 0x100 #define RTL8367C_OP38_NOT_OFFSET 6 #define RTL8367C_OP38_NOT_MASK 0x40 #define RTL8367C_ACT38_GPIO_OFFSET 5 #define RTL8367C_ACT38_GPIO_MASK 0x20 #define RTL8367C_ACT38_FORWARD_OFFSET 4 #define RTL8367C_ACT38_FORWARD_MASK 0x10 #define RTL8367C_ACT38_POLICING_OFFSET 3 #define RTL8367C_ACT38_POLICING_MASK 0x8 #define RTL8367C_ACT38_PRIORITY_OFFSET 2 #define RTL8367C_ACT38_PRIORITY_MASK 0x4 #define RTL8367C_ACT38_SVID_OFFSET 1 #define RTL8367C_ACT38_SVID_MASK 0x2 #define RTL8367C_ACT38_CVID_OFFSET 0 #define RTL8367C_ACT38_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL20 0x0628 #define RTL8367C_OP41_NOT_OFFSET 14 #define RTL8367C_OP41_NOT_MASK 0x4000 #define RTL8367C_ACT41_GPIO_OFFSET 13 #define RTL8367C_ACT41_GPIO_MASK 0x2000 #define RTL8367C_ACT41_FORWARD_OFFSET 12 #define RTL8367C_ACT41_FORWARD_MASK 0x1000 #define RTL8367C_ACT41_POLICING_OFFSET 11 #define RTL8367C_ACT41_POLICING_MASK 0x800 #define RTL8367C_ACT41_PRIORITY_OFFSET 10 #define RTL8367C_ACT41_PRIORITY_MASK 0x400 #define RTL8367C_ACT41_SVID_OFFSET 9 #define RTL8367C_ACT41_SVID_MASK 0x200 #define RTL8367C_ACT41_CVID_OFFSET 8 #define RTL8367C_ACT41_CVID_MASK 0x100 #define RTL8367C_OP40_NOT_OFFSET 6 #define RTL8367C_OP40_NOT_MASK 0x40 #define RTL8367C_ACT40_GPIO_OFFSET 5 #define RTL8367C_ACT40_GPIO_MASK 0x20 #define RTL8367C_ACT40_FORWARD_OFFSET 4 #define RTL8367C_ACT40_FORWARD_MASK 0x10 #define RTL8367C_ACT40_POLICING_OFFSET 3 #define RTL8367C_ACT40_POLICING_MASK 0x8 #define RTL8367C_ACT40_PRIORITY_OFFSET 2 #define RTL8367C_ACT40_PRIORITY_MASK 0x4 #define RTL8367C_ACT40_SVID_OFFSET 1 #define RTL8367C_ACT40_SVID_MASK 0x2 #define RTL8367C_ACT40_CVID_OFFSET 0 #define RTL8367C_ACT40_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL21 0x0629 #define RTL8367C_OP43_NOT_OFFSET 14 #define RTL8367C_OP43_NOT_MASK 0x4000 #define RTL8367C_ACT43_GPIO_OFFSET 13 #define RTL8367C_ACT43_GPIO_MASK 0x2000 #define RTL8367C_ACT43_FORWARD_OFFSET 12 #define RTL8367C_ACT43_FORWARD_MASK 0x1000 #define RTL8367C_ACT43_POLICING_OFFSET 11 #define RTL8367C_ACT43_POLICING_MASK 0x800 #define RTL8367C_ACT43_PRIORITY_OFFSET 10 #define RTL8367C_ACT43_PRIORITY_MASK 0x400 #define RTL8367C_ACT43_SVID_OFFSET 9 #define RTL8367C_ACT43_SVID_MASK 0x200 #define RTL8367C_ACT43_CVID_OFFSET 8 #define RTL8367C_ACT43_CVID_MASK 0x100 #define RTL8367C_OP42_NOT_OFFSET 6 #define RTL8367C_OP42_NOT_MASK 0x40 #define RTL8367C_ACT42_GPIO_OFFSET 5 #define RTL8367C_ACT42_GPIO_MASK 0x20 #define RTL8367C_ACT42_FORWARD_OFFSET 4 #define RTL8367C_ACT42_FORWARD_MASK 0x10 #define RTL8367C_ACT42_POLICING_OFFSET 3 #define RTL8367C_ACT42_POLICING_MASK 0x8 #define RTL8367C_ACT42_PRIORITY_OFFSET 2 #define RTL8367C_ACT42_PRIORITY_MASK 0x4 #define RTL8367C_ACT42_SVID_OFFSET 1 #define RTL8367C_ACT42_SVID_MASK 0x2 #define RTL8367C_ACT42_CVID_OFFSET 0 #define RTL8367C_ACT42_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL22 0x062a #define RTL8367C_OP45_NOT_OFFSET 14 #define RTL8367C_OP45_NOT_MASK 0x4000 #define RTL8367C_ACT45_GPIO_OFFSET 13 #define RTL8367C_ACT45_GPIO_MASK 0x2000 #define RTL8367C_ACT45_FORWARD_OFFSET 12 #define RTL8367C_ACT45_FORWARD_MASK 0x1000 #define RTL8367C_ACT45_POLICING_OFFSET 11 #define RTL8367C_ACT45_POLICING_MASK 0x800 #define RTL8367C_ACT45_PRIORITY_OFFSET 10 #define RTL8367C_ACT45_PRIORITY_MASK 0x400 #define RTL8367C_ACT45_SVID_OFFSET 9 #define RTL8367C_ACT45_SVID_MASK 0x200 #define RTL8367C_ACT45_CVID_OFFSET 8 #define RTL8367C_ACT45_CVID_MASK 0x100 #define RTL8367C_OP44_NOT_OFFSET 6 #define RTL8367C_OP44_NOT_MASK 0x40 #define RTL8367C_ACT44_GPIO_OFFSET 5 #define RTL8367C_ACT44_GPIO_MASK 0x20 #define RTL8367C_ACT44_FORWARD_OFFSET 4 #define RTL8367C_ACT44_FORWARD_MASK 0x10 #define RTL8367C_ACT44_POLICING_OFFSET 3 #define RTL8367C_ACT44_POLICING_MASK 0x8 #define RTL8367C_ACT44_PRIORITY_OFFSET 2 #define RTL8367C_ACT44_PRIORITY_MASK 0x4 #define RTL8367C_ACT44_SVID_OFFSET 1 #define RTL8367C_ACT44_SVID_MASK 0x2 #define RTL8367C_ACT44_CVID_OFFSET 0 #define RTL8367C_ACT44_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL23 0x062b #define RTL8367C_OP47_NOT_OFFSET 14 #define RTL8367C_OP47_NOT_MASK 0x4000 #define RTL8367C_ACT47_GPIO_OFFSET 13 #define RTL8367C_ACT47_GPIO_MASK 0x2000 #define RTL8367C_ACT47_FORWARD_OFFSET 12 #define RTL8367C_ACT47_FORWARD_MASK 0x1000 #define RTL8367C_ACT47_POLICING_OFFSET 11 #define RTL8367C_ACT47_POLICING_MASK 0x800 #define RTL8367C_ACT47_PRIORITY_OFFSET 10 #define RTL8367C_ACT47_PRIORITY_MASK 0x400 #define RTL8367C_ACT47_SVID_OFFSET 9 #define RTL8367C_ACT47_SVID_MASK 0x200 #define RTL8367C_ACT47_CVID_OFFSET 8 #define RTL8367C_ACT47_CVID_MASK 0x100 #define RTL8367C_OP46_NOT_OFFSET 6 #define RTL8367C_OP46_NOT_MASK 0x40 #define RTL8367C_ACT46_GPIO_OFFSET 5 #define RTL8367C_ACT46_GPIO_MASK 0x20 #define RTL8367C_ACT46_FORWARD_OFFSET 4 #define RTL8367C_ACT46_FORWARD_MASK 0x10 #define RTL8367C_ACT46_POLICING_OFFSET 3 #define RTL8367C_ACT46_POLICING_MASK 0x8 #define RTL8367C_ACT46_PRIORITY_OFFSET 2 #define RTL8367C_ACT46_PRIORITY_MASK 0x4 #define RTL8367C_ACT46_SVID_OFFSET 1 #define RTL8367C_ACT46_SVID_MASK 0x2 #define RTL8367C_ACT46_CVID_OFFSET 0 #define RTL8367C_ACT46_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL24 0x062c #define RTL8367C_OP49_NOT_OFFSET 14 #define RTL8367C_OP49_NOT_MASK 0x4000 #define RTL8367C_ACT49_GPIO_OFFSET 13 #define RTL8367C_ACT49_GPIO_MASK 0x2000 #define RTL8367C_ACT49_FORWARD_OFFSET 12 #define RTL8367C_ACT49_FORWARD_MASK 0x1000 #define RTL8367C_ACT49_POLICING_OFFSET 11 #define RTL8367C_ACT49_POLICING_MASK 0x800 #define RTL8367C_ACT49_PRIORITY_OFFSET 10 #define RTL8367C_ACT49_PRIORITY_MASK 0x400 #define RTL8367C_ACT49_SVID_OFFSET 9 #define RTL8367C_ACT49_SVID_MASK 0x200 #define RTL8367C_ACT49_CVID_OFFSET 8 #define RTL8367C_ACT49_CVID_MASK 0x100 #define RTL8367C_OP48_NOT_OFFSET 6 #define RTL8367C_OP48_NOT_MASK 0x40 #define RTL8367C_ACT48_GPIO_OFFSET 5 #define RTL8367C_ACT48_GPIO_MASK 0x20 #define RTL8367C_ACT48_FORWARD_OFFSET 4 #define RTL8367C_ACT48_FORWARD_MASK 0x10 #define RTL8367C_ACT48_POLICING_OFFSET 3 #define RTL8367C_ACT48_POLICING_MASK 0x8 #define RTL8367C_ACT48_PRIORITY_OFFSET 2 #define RTL8367C_ACT48_PRIORITY_MASK 0x4 #define RTL8367C_ACT48_SVID_OFFSET 1 #define RTL8367C_ACT48_SVID_MASK 0x2 #define RTL8367C_ACT48_CVID_OFFSET 0 #define RTL8367C_ACT48_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL25 0x062d #define RTL8367C_OP51_NOT_OFFSET 14 #define RTL8367C_OP51_NOT_MASK 0x4000 #define RTL8367C_ACT51_GPIO_OFFSET 13 #define RTL8367C_ACT51_GPIO_MASK 0x2000 #define RTL8367C_ACT51_FORWARD_OFFSET 12 #define RTL8367C_ACT51_FORWARD_MASK 0x1000 #define RTL8367C_ACT51_POLICING_OFFSET 11 #define RTL8367C_ACT51_POLICING_MASK 0x800 #define RTL8367C_ACT51_PRIORITY_OFFSET 10 #define RTL8367C_ACT51_PRIORITY_MASK 0x400 #define RTL8367C_ACT51_SVID_OFFSET 9 #define RTL8367C_ACT51_SVID_MASK 0x200 #define RTL8367C_ACT51_CVID_OFFSET 8 #define RTL8367C_ACT51_CVID_MASK 0x100 #define RTL8367C_OP50_NOT_OFFSET 6 #define RTL8367C_OP50_NOT_MASK 0x40 #define RTL8367C_ACT50_GPIO_OFFSET 5 #define RTL8367C_ACT50_GPIO_MASK 0x20 #define RTL8367C_ACT50_FORWARD_OFFSET 4 #define RTL8367C_ACT50_FORWARD_MASK 0x10 #define RTL8367C_ACT50_POLICING_OFFSET 3 #define RTL8367C_ACT50_POLICING_MASK 0x8 #define RTL8367C_ACT50_PRIORITY_OFFSET 2 #define RTL8367C_ACT50_PRIORITY_MASK 0x4 #define RTL8367C_ACT50_SVID_OFFSET 1 #define RTL8367C_ACT50_SVID_MASK 0x2 #define RTL8367C_ACT50_CVID_OFFSET 0 #define RTL8367C_ACT50_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL26 0x062e #define RTL8367C_OP53_NOT_OFFSET 14 #define RTL8367C_OP53_NOT_MASK 0x4000 #define RTL8367C_ACT53_GPIO_OFFSET 13 #define RTL8367C_ACT53_GPIO_MASK 0x2000 #define RTL8367C_ACT53_FORWARD_OFFSET 12 #define RTL8367C_ACT53_FORWARD_MASK 0x1000 #define RTL8367C_ACT53_POLICING_OFFSET 11 #define RTL8367C_ACT53_POLICING_MASK 0x800 #define RTL8367C_ACT53_PRIORITY_OFFSET 10 #define RTL8367C_ACT53_PRIORITY_MASK 0x400 #define RTL8367C_ACT53_SVID_OFFSET 9 #define RTL8367C_ACT53_SVID_MASK 0x200 #define RTL8367C_ACT53_CVID_OFFSET 8 #define RTL8367C_ACT53_CVID_MASK 0x100 #define RTL8367C_OP52_NOT_OFFSET 6 #define RTL8367C_OP52_NOT_MASK 0x40 #define RTL8367C_ACT52_GPIO_OFFSET 5 #define RTL8367C_ACT52_GPIO_MASK 0x20 #define RTL8367C_ACT52_FORWARD_OFFSET 4 #define RTL8367C_ACT52_FORWARD_MASK 0x10 #define RTL8367C_ACT52_POLICING_OFFSET 3 #define RTL8367C_ACT52_POLICING_MASK 0x8 #define RTL8367C_ACT52_PRIORITY_OFFSET 2 #define RTL8367C_ACT52_PRIORITY_MASK 0x4 #define RTL8367C_ACT52_SVID_OFFSET 1 #define RTL8367C_ACT52_SVID_MASK 0x2 #define RTL8367C_ACT52_CVID_OFFSET 0 #define RTL8367C_ACT52_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL27 0x062f #define RTL8367C_OP55_NOT_OFFSET 14 #define RTL8367C_OP55_NOT_MASK 0x4000 #define RTL8367C_ACT55_GPIO_OFFSET 13 #define RTL8367C_ACT55_GPIO_MASK 0x2000 #define RTL8367C_ACT55_FORWARD_OFFSET 12 #define RTL8367C_ACT55_FORWARD_MASK 0x1000 #define RTL8367C_ACT55_POLICING_OFFSET 11 #define RTL8367C_ACT55_POLICING_MASK 0x800 #define RTL8367C_ACT55_PRIORITY_OFFSET 10 #define RTL8367C_ACT55_PRIORITY_MASK 0x400 #define RTL8367C_ACT55_SVID_OFFSET 9 #define RTL8367C_ACT55_SVID_MASK 0x200 #define RTL8367C_ACT55_CVID_OFFSET 8 #define RTL8367C_ACT55_CVID_MASK 0x100 #define RTL8367C_OP54_NOT_OFFSET 6 #define RTL8367C_OP54_NOT_MASK 0x40 #define RTL8367C_ACT54_GPIO_OFFSET 5 #define RTL8367C_ACT54_GPIO_MASK 0x20 #define RTL8367C_ACT54_FORWARD_OFFSET 4 #define RTL8367C_ACT54_FORWARD_MASK 0x10 #define RTL8367C_ACT54_POLICING_OFFSET 3 #define RTL8367C_ACT54_POLICING_MASK 0x8 #define RTL8367C_ACT54_PRIORITY_OFFSET 2 #define RTL8367C_ACT54_PRIORITY_MASK 0x4 #define RTL8367C_ACT54_SVID_OFFSET 1 #define RTL8367C_ACT54_SVID_MASK 0x2 #define RTL8367C_ACT54_CVID_OFFSET 0 #define RTL8367C_ACT54_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL28 0x0630 #define RTL8367C_OP57_NOT_OFFSET 14 #define RTL8367C_OP57_NOT_MASK 0x4000 #define RTL8367C_ACT57_GPIO_OFFSET 13 #define RTL8367C_ACT57_GPIO_MASK 0x2000 #define RTL8367C_ACT57_FORWARD_OFFSET 12 #define RTL8367C_ACT57_FORWARD_MASK 0x1000 #define RTL8367C_ACT57_POLICING_OFFSET 11 #define RTL8367C_ACT57_POLICING_MASK 0x800 #define RTL8367C_ACT57_PRIORITY_OFFSET 10 #define RTL8367C_ACT57_PRIORITY_MASK 0x400 #define RTL8367C_ACT57_SVID_OFFSET 9 #define RTL8367C_ACT57_SVID_MASK 0x200 #define RTL8367C_ACT57_CVID_OFFSET 8 #define RTL8367C_ACT57_CVID_MASK 0x100 #define RTL8367C_OP56_NOT_OFFSET 6 #define RTL8367C_OP56_NOT_MASK 0x40 #define RTL8367C_ACT56_GPIO_OFFSET 5 #define RTL8367C_ACT56_GPIO_MASK 0x20 #define RTL8367C_ACT56_FORWARD_OFFSET 4 #define RTL8367C_ACT56_FORWARD_MASK 0x10 #define RTL8367C_ACT56_POLICING_OFFSET 3 #define RTL8367C_ACT56_POLICING_MASK 0x8 #define RTL8367C_ACT56_PRIORITY_OFFSET 2 #define RTL8367C_ACT56_PRIORITY_MASK 0x4 #define RTL8367C_ACT56_SVID_OFFSET 1 #define RTL8367C_ACT56_SVID_MASK 0x2 #define RTL8367C_ACT56_CVID_OFFSET 0 #define RTL8367C_ACT56_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL29 0x0631 #define RTL8367C_OP59_NOT_OFFSET 14 #define RTL8367C_OP59_NOT_MASK 0x4000 #define RTL8367C_ACT59_GPIO_OFFSET 13 #define RTL8367C_ACT59_GPIO_MASK 0x2000 #define RTL8367C_ACT59_FORWARD_OFFSET 12 #define RTL8367C_ACT59_FORWARD_MASK 0x1000 #define RTL8367C_ACT59_POLICING_OFFSET 11 #define RTL8367C_ACT59_POLICING_MASK 0x800 #define RTL8367C_ACT59_PRIORITY_OFFSET 10 #define RTL8367C_ACT59_PRIORITY_MASK 0x400 #define RTL8367C_ACT59_SVID_OFFSET 9 #define RTL8367C_ACT59_SVID_MASK 0x200 #define RTL8367C_ACT59_CVID_OFFSET 8 #define RTL8367C_ACT59_CVID_MASK 0x100 #define RTL8367C_OP58_NOT_OFFSET 6 #define RTL8367C_OP58_NOT_MASK 0x40 #define RTL8367C_ACT58_GPIO_OFFSET 5 #define RTL8367C_ACT58_GPIO_MASK 0x20 #define RTL8367C_ACT58_FORWARD_OFFSET 4 #define RTL8367C_ACT58_FORWARD_MASK 0x10 #define RTL8367C_ACT58_POLICING_OFFSET 3 #define RTL8367C_ACT58_POLICING_MASK 0x8 #define RTL8367C_ACT58_PRIORITY_OFFSET 2 #define RTL8367C_ACT58_PRIORITY_MASK 0x4 #define RTL8367C_ACT58_SVID_OFFSET 1 #define RTL8367C_ACT58_SVID_MASK 0x2 #define RTL8367C_ACT58_CVID_OFFSET 0 #define RTL8367C_ACT58_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL30 0x0632 #define RTL8367C_OP61_NOT_OFFSET 14 #define RTL8367C_OP61_NOT_MASK 0x4000 #define RTL8367C_ACT61_GPIO_OFFSET 13 #define RTL8367C_ACT61_GPIO_MASK 0x2000 #define RTL8367C_ACT61_FORWARD_OFFSET 12 #define RTL8367C_ACT61_FORWARD_MASK 0x1000 #define RTL8367C_ACT61_POLICING_OFFSET 11 #define RTL8367C_ACT61_POLICING_MASK 0x800 #define RTL8367C_ACT61_PRIORITY_OFFSET 10 #define RTL8367C_ACT61_PRIORITY_MASK 0x400 #define RTL8367C_ACT61_SVID_OFFSET 9 #define RTL8367C_ACT61_SVID_MASK 0x200 #define RTL8367C_ACT61_CVID_OFFSET 8 #define RTL8367C_ACT61_CVID_MASK 0x100 #define RTL8367C_OP60_NOT_OFFSET 6 #define RTL8367C_OP60_NOT_MASK 0x40 #define RTL8367C_ACT60_GPIO_OFFSET 5 #define RTL8367C_ACT60_GPIO_MASK 0x20 #define RTL8367C_ACT60_FORWARD_OFFSET 4 #define RTL8367C_ACT60_FORWARD_MASK 0x10 #define RTL8367C_ACT60_POLICING_OFFSET 3 #define RTL8367C_ACT60_POLICING_MASK 0x8 #define RTL8367C_ACT60_PRIORITY_OFFSET 2 #define RTL8367C_ACT60_PRIORITY_MASK 0x4 #define RTL8367C_ACT60_SVID_OFFSET 1 #define RTL8367C_ACT60_SVID_MASK 0x2 #define RTL8367C_ACT60_CVID_OFFSET 0 #define RTL8367C_ACT60_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL31 0x0633 #define RTL8367C_OP63_NOT_OFFSET 14 #define RTL8367C_OP63_NOT_MASK 0x4000 #define RTL8367C_ACT63_GPIO_OFFSET 13 #define RTL8367C_ACT63_GPIO_MASK 0x2000 #define RTL8367C_ACT63_FORWARD_OFFSET 12 #define RTL8367C_ACT63_FORWARD_MASK 0x1000 #define RTL8367C_ACT63_POLICING_OFFSET 11 #define RTL8367C_ACT63_POLICING_MASK 0x800 #define RTL8367C_ACT63_PRIORITY_OFFSET 10 #define RTL8367C_ACT63_PRIORITY_MASK 0x400 #define RTL8367C_ACT63_SVID_OFFSET 9 #define RTL8367C_ACT63_SVID_MASK 0x200 #define RTL8367C_ACT63_CVID_OFFSET 8 #define RTL8367C_ACT63_CVID_MASK 0x100 #define RTL8367C_OP62_NOT_OFFSET 6 #define RTL8367C_OP62_NOT_MASK 0x40 #define RTL8367C_ACT62_GPIO_OFFSET 5 #define RTL8367C_ACT62_GPIO_MASK 0x20 #define RTL8367C_ACT62_FORWARD_OFFSET 4 #define RTL8367C_ACT62_FORWARD_MASK 0x10 #define RTL8367C_ACT62_POLICING_OFFSET 3 #define RTL8367C_ACT62_POLICING_MASK 0x8 #define RTL8367C_ACT62_PRIORITY_OFFSET 2 #define RTL8367C_ACT62_PRIORITY_MASK 0x4 #define RTL8367C_ACT62_SVID_OFFSET 1 #define RTL8367C_ACT62_SVID_MASK 0x2 #define RTL8367C_ACT62_CVID_OFFSET 0 #define RTL8367C_ACT62_CVID_MASK 0x1 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 0x0635 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 0x0636 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 0x0637 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL0 0x0638 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL1 0x0639 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL2 0x063a #define RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL0 0x063b #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL1 0x063c #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL2 0x063d #define RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL0 0x063e #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL1 0x063f #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL2 0x0640 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL0 0x0641 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL1 0x0642 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL2 0x0643 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL0 0x0644 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL1 0x0645 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL2 0x0646 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL0 0x0647 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL1 0x0648 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL2 0x0649 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL0 0x064a #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL1 0x064b #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL2 0x064c #define RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL0 0x064d #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL1 0x064e #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL2 0x064f #define RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL0 0x0650 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL1 0x0651 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL2 0x0652 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL0 0x0653 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL1 0x0654 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL2 0x0655 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL0 0x0656 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL1 0x0657 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL2 0x0658 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL0 0x0659 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL1 0x065a #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL2 0x065b #define RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL0 0x065c #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL1 0x065d #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL2 0x065e #define RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL0 0x065f #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL1 0x0660 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL2 0x0661 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL0 0x0662 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL1 0x0663 #define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL2 0x0664 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_OFFSET 0 #define RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_MASK 0x3 #define RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 0x0665 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 0x0666 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL0 0x0667 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL1 0x0668 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL0 0x0669 #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL1 0x066a #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL0 0x066b #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL1 0x066c #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL0 0x066d #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL1 0x066e #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL0 0x066f #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL1 0x0670 #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL0 0x0671 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL1 0x0672 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL0 0x0673 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL1 0x0674 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL0 0x0675 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL1 0x0676 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL0 0x0677 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL1 0x0678 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL0 0x0679 #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL1 0x067a #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL0 0x067b #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL1 0x067c #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL0 0x067d #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL1 0x067e #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL0 0x067f #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL1 0x0680 #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL0 0x0681 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL1 0x0682 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL0 0x0683 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_MASK 0xFFF #define RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL1 0x0684 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_OFFSET 12 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_MASK 0x3000 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_OFFSET 0 #define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_MASK 0xFFF #define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 0x0685 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 0x0686 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 0x0687 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 0x0688 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 0x0689 #define RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL0 0x068a #define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL1 0x068b #define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL2 0x068c #define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL3 0x068d #define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL4 0x068e #define RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL0 0x068f #define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL1 0x0690 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL2 0x0691 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL3 0x0692 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL4 0x0693 #define RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL0 0x0694 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL1 0x0695 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL2 0x0696 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL3 0x0697 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL4 0x0698 #define RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL0 0x0699 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL1 0x069a #define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL2 0x069b #define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL3 0x069c #define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL4 0x069d #define RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL0 0x069e #define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL1 0x069f #define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL2 0x06a0 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL3 0x06a1 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL4 0x06a2 #define RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL0 0x06a3 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL1 0x06a4 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL2 0x06a5 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL3 0x06a6 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL4 0x06a7 #define RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL0 0x06a8 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL1 0x06a9 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL2 0x06aa #define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL3 0x06ab #define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL4 0x06ac #define RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL0 0x06ad #define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL1 0x06ae #define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL2 0x06af #define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL3 0x06b0 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL4 0x06b1 #define RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL0 0x06b2 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL1 0x06b3 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL2 0x06b4 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL3 0x06b5 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL4 0x06b6 #define RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL0 0x06b7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL1 0x06b8 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL2 0x06b9 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL3 0x06ba #define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL4 0x06bb #define RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL0 0x06bc #define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL1 0x06bd #define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL2 0x06be #define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL3 0x06bf #define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL4 0x06c0 #define RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL0 0x06c1 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL1 0x06c2 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL2 0x06c3 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL3 0x06c4 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL4 0x06c5 #define RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL0 0x06c6 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL1 0x06c7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL2 0x06c8 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL3 0x06c9 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL4 0x06ca #define RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL0 0x06cb #define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL1 0x06cc #define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL2 0x06cd #define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL3 0x06ce #define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL4 0x06cf #define RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL0 0x06d0 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL1 0x06d1 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL2 0x06d2 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL3 0x06d3 #define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL4 0x06d4 #define RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_OFFSET 0 #define RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_MASK 0x7 #define RTL8367C_REG_ACL_ENABLE 0x06d5 #define RTL8367C_PORT10_ENABLE_OFFSET 10 #define RTL8367C_PORT10_ENABLE_MASK 0x400 #define RTL8367C_PORT9_ENABLE_OFFSET 9 #define RTL8367C_PORT9_ENABLE_MASK 0x200 #define RTL8367C_PORT8_ENABLE_OFFSET 8 #define RTL8367C_PORT8_ENABLE_MASK 0x100 #define RTL8367C_PORT7_ENABLE_OFFSET 7 #define RTL8367C_PORT7_ENABLE_MASK 0x80 #define RTL8367C_PORT6_ENABLE_OFFSET 6 #define RTL8367C_PORT6_ENABLE_MASK 0x40 #define RTL8367C_PORT5_ENABLE_OFFSET 5 #define RTL8367C_PORT5_ENABLE_MASK 0x20 #define RTL8367C_PORT4_ENABLE_OFFSET 4 #define RTL8367C_PORT4_ENABLE_MASK 0x10 #define RTL8367C_PORT3_ENABLE_OFFSET 3 #define RTL8367C_PORT3_ENABLE_MASK 0x8 #define RTL8367C_PORT2_ENABLE_OFFSET 2 #define RTL8367C_PORT2_ENABLE_MASK 0x4 #define RTL8367C_PORT1_ENABLE_OFFSET 1 #define RTL8367C_PORT1_ENABLE_MASK 0x2 #define RTL8367C_PORT0_ENABLE_OFFSET 0 #define RTL8367C_PORT0_ENABLE_MASK 0x1 #define RTL8367C_REG_ACL_UNMATCH_PERMIT 0x06d6 #define RTL8367C_PORT10_PERMIT_OFFSET 10 #define RTL8367C_PORT10_PERMIT_MASK 0x400 #define RTL8367C_PORT9_PERMIT_OFFSET 9 #define RTL8367C_PORT9_PERMIT_MASK 0x200 #define RTL8367C_PORT8_PERMIT_OFFSET 8 #define RTL8367C_PORT8_PERMIT_MASK 0x100 #define RTL8367C_PORT7_PERMIT_OFFSET 7 #define RTL8367C_PORT7_PERMIT_MASK 0x80 #define RTL8367C_PORT6_PERMIT_OFFSET 6 #define RTL8367C_PORT6_PERMIT_MASK 0x40 #define RTL8367C_PORT5_PERMIT_OFFSET 5 #define RTL8367C_PORT5_PERMIT_MASK 0x20 #define RTL8367C_PORT4_PERMIT_OFFSET 4 #define RTL8367C_PORT4_PERMIT_MASK 0x10 #define RTL8367C_PORT3_PERMIT_OFFSET 3 #define RTL8367C_PORT3_PERMIT_MASK 0x8 #define RTL8367C_PORT2_PERMIT_OFFSET 2 #define RTL8367C_PORT2_PERMIT_MASK 0x4 #define RTL8367C_PORT1_PERMIT_OFFSET 1 #define RTL8367C_PORT1_PERMIT_MASK 0x2 #define RTL8367C_PORT0_PERMIT_OFFSET 0 #define RTL8367C_PORT0_PERMIT_MASK 0x1 #define RTL8367C_REG_ACL_GPIO_POLARITY 0x06d7 #define RTL8367C_ACL_GPIO_POLARITY_OFFSET 0 #define RTL8367C_ACL_GPIO_POLARITY_MASK 0x1 #define RTL8367C_REG_ACL_LOG_CNT_TYPE 0x06d8 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_OFFSET 15 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_MASK 0x8000 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_OFFSET 14 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_MASK 0x4000 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_OFFSET 13 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_MASK 0x2000 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_OFFSET 12 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_MASK 0x1000 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_OFFSET 11 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_MASK 0x800 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_OFFSET 10 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_MASK 0x400 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_OFFSET 9 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_MASK 0x200 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_OFFSET 8 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_MASK 0x100 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_OFFSET 7 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_MASK 0x80 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_OFFSET 6 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_MASK 0x40 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_OFFSET 5 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_MASK 0x20 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_OFFSET 4 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_MASK 0x10 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_OFFSET 3 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_MASK 0x8 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_OFFSET 2 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_MASK 0x4 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_OFFSET 1 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_MASK 0x2 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_OFFSET 0 #define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_MASK 0x1 #define RTL8367C_REG_ACL_RESET_CFG 0x06d9 #define RTL8367C_ACL_RESET_CFG_OFFSET 0 #define RTL8367C_ACL_RESET_CFG_MASK 0x1 #define RTL8367C_REG_ACL_DUMMY00 0x06E0 #define RTL8367C_REG_ACL_DUMMY01 0x06E1 #define RTL8367C_REG_ACL_DUMMY02 0x06E2 #define RTL8367C_REG_ACL_DUMMY03 0x06E3 #define RTL8367C_REG_ACL_DUMMY04 0x06E4 #define RTL8367C_REG_ACL_DUMMY05 0x06E5 #define RTL8367C_REG_ACL_DUMMY06 0x06E6 #define RTL8367C_REG_ACL_DUMMY07 0x06E7 #define RTL8367C_REG_ACL_REASON_01 0x06E8 #define RTL8367C_ACL_ACT_1_OFFSET 8 #define RTL8367C_ACL_ACT_1_MASK 0xFF00 #define RTL8367C_ACL_ACT_0_OFFSET 0 #define RTL8367C_ACL_ACT_0_MASK 0xFF #define RTL8367C_REG_ACL_REASON_23 0x06E9 #define RTL8367C_ACL_ACT_3_OFFSET 8 #define RTL8367C_ACL_ACT_3_MASK 0xFF00 #define RTL8367C_ACL_ACT_2_OFFSET 0 #define RTL8367C_ACL_ACT_2_MASK 0xFF #define RTL8367C_REG_ACL_REASON_45 0x06EA #define RTL8367C_ACL_ACT_5_OFFSET 8 #define RTL8367C_ACL_ACT_5_MASK 0xFF00 #define RTL8367C_ACL_ACT_4_OFFSET 0 #define RTL8367C_ACL_ACT_4_MASK 0xFF #define RTL8367C_REG_ACL_ACCESS_MODE 0x06EB #define RTL8367C_ACL_ACCESS_MODE_OFFSET 0 #define RTL8367C_ACL_ACCESS_MODE_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL32 0x06F0 #define RTL8367C_OP65_NOT_OFFSET 14 #define RTL8367C_OP65_NOT_MASK 0x4000 #define RTL8367C_ACT65_GPIO_OFFSET 13 #define RTL8367C_ACT65_GPIO_MASK 0x2000 #define RTL8367C_ACT65_FORWARD_OFFSET 12 #define RTL8367C_ACT65_FORWARD_MASK 0x1000 #define RTL8367C_ACT65_POLICING_OFFSET 11 #define RTL8367C_ACT65_POLICING_MASK 0x800 #define RTL8367C_ACT65_PRIORITY_OFFSET 10 #define RTL8367C_ACT65_PRIORITY_MASK 0x400 #define RTL8367C_ACT65_SVID_OFFSET 9 #define RTL8367C_ACT65_SVID_MASK 0x200 #define RTL8367C_ACT65_CVID_OFFSET 8 #define RTL8367C_ACT65_CVID_MASK 0x100 #define RTL8367C_OP64_NOT_OFFSET 6 #define RTL8367C_OP64_NOT_MASK 0x40 #define RTL8367C_ACT64_GPIO_OFFSET 5 #define RTL8367C_ACT64_GPIO_MASK 0x20 #define RTL8367C_ACT64_FORWARD_OFFSET 4 #define RTL8367C_ACT64_FORWARD_MASK 0x10 #define RTL8367C_ACT64_POLICING_OFFSET 3 #define RTL8367C_ACT64_POLICING_MASK 0x8 #define RTL8367C_ACT64_PRIORITY_OFFSET 2 #define RTL8367C_ACT64_PRIORITY_MASK 0x4 #define RTL8367C_ACT64_SVID_OFFSET 1 #define RTL8367C_ACT64_SVID_MASK 0x2 #define RTL8367C_ACT64_CVID_OFFSET 0 #define RTL8367C_ACT64_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL33 0x06F1 #define RTL8367C_OP67_NOT_OFFSET 14 #define RTL8367C_OP67_NOT_MASK 0x4000 #define RTL8367C_ACT67_GPIO_OFFSET 13 #define RTL8367C_ACT67_GPIO_MASK 0x2000 #define RTL8367C_ACT67_FORWARD_OFFSET 12 #define RTL8367C_ACT67_FORWARD_MASK 0x1000 #define RTL8367C_ACT67_POLICING_OFFSET 11 #define RTL8367C_ACT67_POLICING_MASK 0x800 #define RTL8367C_ACT67_PRIORITY_OFFSET 10 #define RTL8367C_ACT67_PRIORITY_MASK 0x400 #define RTL8367C_ACT67_SVID_OFFSET 9 #define RTL8367C_ACT67_SVID_MASK 0x200 #define RTL8367C_ACT67_CVID_OFFSET 8 #define RTL8367C_ACT67_CVID_MASK 0x100 #define RTL8367C_OP66_NOT_OFFSET 6 #define RTL8367C_OP66_NOT_MASK 0x40 #define RTL8367C_ACT66_GPIO_OFFSET 5 #define RTL8367C_ACT66_GPIO_MASK 0x20 #define RTL8367C_ACT66_FORWARD_OFFSET 4 #define RTL8367C_ACT66_FORWARD_MASK 0x10 #define RTL8367C_ACT66_POLICING_OFFSET 3 #define RTL8367C_ACT66_POLICING_MASK 0x8 #define RTL8367C_ACT66_PRIORITY_OFFSET 2 #define RTL8367C_ACT66_PRIORITY_MASK 0x4 #define RTL8367C_ACT66_SVID_OFFSET 1 #define RTL8367C_ACT66_SVID_MASK 0x2 #define RTL8367C_ACT66_CVID_OFFSET 0 #define RTL8367C_ACT66_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL34 0x06F2 #define RTL8367C_OP69_NOT_OFFSET 14 #define RTL8367C_OP69_NOT_MASK 0x4000 #define RTL8367C_ACT69_GPIO_OFFSET 13 #define RTL8367C_ACT69_GPIO_MASK 0x2000 #define RTL8367C_ACT69_FORWARD_OFFSET 12 #define RTL8367C_ACT69_FORWARD_MASK 0x1000 #define RTL8367C_ACT69_POLICING_OFFSET 11 #define RTL8367C_ACT69_POLICING_MASK 0x800 #define RTL8367C_ACT69_PRIORITY_OFFSET 10 #define RTL8367C_ACT69_PRIORITY_MASK 0x400 #define RTL8367C_ACT69_SVID_OFFSET 9 #define RTL8367C_ACT69_SVID_MASK 0x200 #define RTL8367C_ACT69_CVID_OFFSET 8 #define RTL8367C_ACT69_CVID_MASK 0x100 #define RTL8367C_OP68_NOT_OFFSET 6 #define RTL8367C_OP68_NOT_MASK 0x40 #define RTL8367C_ACT68_GPIO_OFFSET 5 #define RTL8367C_ACT68_GPIO_MASK 0x20 #define RTL8367C_ACT68_FORWARD_OFFSET 4 #define RTL8367C_ACT68_FORWARD_MASK 0x10 #define RTL8367C_ACT68_POLICING_OFFSET 3 #define RTL8367C_ACT68_POLICING_MASK 0x8 #define RTL8367C_ACT68_PRIORITY_OFFSET 2 #define RTL8367C_ACT68_PRIORITY_MASK 0x4 #define RTL8367C_ACT68_SVID_OFFSET 1 #define RTL8367C_ACT68_SVID_MASK 0x2 #define RTL8367C_ACT68_CVID_OFFSET 0 #define RTL8367C_ACT68_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL35 0x06F3 #define RTL8367C_OP71_NOT_OFFSET 14 #define RTL8367C_OP71_NOT_MASK 0x4000 #define RTL8367C_ACT71_GPIO_OFFSET 13 #define RTL8367C_ACT71_GPIO_MASK 0x2000 #define RTL8367C_ACT71_FORWARD_OFFSET 12 #define RTL8367C_ACT71_FORWARD_MASK 0x1000 #define RTL8367C_ACT71_POLICING_OFFSET 11 #define RTL8367C_ACT71_POLICING_MASK 0x800 #define RTL8367C_ACT71_PRIORITY_OFFSET 10 #define RTL8367C_ACT71_PRIORITY_MASK 0x400 #define RTL8367C_ACT71_SVID_OFFSET 9 #define RTL8367C_ACT71_SVID_MASK 0x200 #define RTL8367C_ACT71_CVID_OFFSET 8 #define RTL8367C_ACT71_CVID_MASK 0x100 #define RTL8367C_OP70_NOT_OFFSET 6 #define RTL8367C_OP70_NOT_MASK 0x40 #define RTL8367C_ACT70_GPIO_OFFSET 5 #define RTL8367C_ACT70_GPIO_MASK 0x20 #define RTL8367C_ACT70_FORWARD_OFFSET 4 #define RTL8367C_ACT70_FORWARD_MASK 0x10 #define RTL8367C_ACT70_POLICING_OFFSET 3 #define RTL8367C_ACT70_POLICING_MASK 0x8 #define RTL8367C_ACT70_PRIORITY_OFFSET 2 #define RTL8367C_ACT70_PRIORITY_MASK 0x4 #define RTL8367C_ACT70_SVID_OFFSET 1 #define RTL8367C_ACT70_SVID_MASK 0x2 #define RTL8367C_ACT70_CVID_OFFSET 0 #define RTL8367C_ACT70_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL36 0x06F4 #define RTL8367C_OP73_NOT_OFFSET 14 #define RTL8367C_OP73_NOT_MASK 0x4000 #define RTL8367C_ACT73_GPIO_OFFSET 13 #define RTL8367C_ACT73_GPIO_MASK 0x2000 #define RTL8367C_ACT73_FORWARD_OFFSET 12 #define RTL8367C_ACT73_FORWARD_MASK 0x1000 #define RTL8367C_ACT73_POLICING_OFFSET 11 #define RTL8367C_ACT73_POLICING_MASK 0x800 #define RTL8367C_ACT73_PRIORITY_OFFSET 10 #define RTL8367C_ACT73_PRIORITY_MASK 0x400 #define RTL8367C_ACT73_SVID_OFFSET 9 #define RTL8367C_ACT73_SVID_MASK 0x200 #define RTL8367C_ACT73_CVID_OFFSET 8 #define RTL8367C_ACT73_CVID_MASK 0x100 #define RTL8367C_OP72_NOT_OFFSET 6 #define RTL8367C_OP72_NOT_MASK 0x40 #define RTL8367C_ACT72_GPIO_OFFSET 5 #define RTL8367C_ACT72_GPIO_MASK 0x20 #define RTL8367C_ACT72_FORWARD_OFFSET 4 #define RTL8367C_ACT72_FORWARD_MASK 0x10 #define RTL8367C_ACT72_POLICING_OFFSET 3 #define RTL8367C_ACT72_POLICING_MASK 0x8 #define RTL8367C_ACT72_PRIORITY_OFFSET 2 #define RTL8367C_ACT72_PRIORITY_MASK 0x4 #define RTL8367C_ACT72_SVID_OFFSET 1 #define RTL8367C_ACT72_SVID_MASK 0x2 #define RTL8367C_ACT72_CVID_OFFSET 0 #define RTL8367C_ACT72_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL37 0x06F5 #define RTL8367C_OP75_NOT_OFFSET 14 #define RTL8367C_OP75_NOT_MASK 0x4000 #define RTL8367C_ACT75_GPIO_OFFSET 13 #define RTL8367C_ACT75_GPIO_MASK 0x2000 #define RTL8367C_ACT75_FORWARD_OFFSET 12 #define RTL8367C_ACT75_FORWARD_MASK 0x1000 #define RTL8367C_ACT75_POLICING_OFFSET 11 #define RTL8367C_ACT75_POLICING_MASK 0x800 #define RTL8367C_ACT75_PRIORITY_OFFSET 10 #define RTL8367C_ACT75_PRIORITY_MASK 0x400 #define RTL8367C_ACT75_SVID_OFFSET 9 #define RTL8367C_ACT75_SVID_MASK 0x200 #define RTL8367C_ACT75_CVID_OFFSET 8 #define RTL8367C_ACT75_CVID_MASK 0x100 #define RTL8367C_OP74_NOT_OFFSET 6 #define RTL8367C_OP74_NOT_MASK 0x40 #define RTL8367C_ACT74_GPIO_OFFSET 5 #define RTL8367C_ACT74_GPIO_MASK 0x20 #define RTL8367C_ACT74_FORWARD_OFFSET 4 #define RTL8367C_ACT74_FORWARD_MASK 0x10 #define RTL8367C_ACT74_POLICING_OFFSET 3 #define RTL8367C_ACT74_POLICING_MASK 0x8 #define RTL8367C_ACT74_PRIORITY_OFFSET 2 #define RTL8367C_ACT74_PRIORITY_MASK 0x4 #define RTL8367C_ACT74_SVID_OFFSET 1 #define RTL8367C_ACT74_SVID_MASK 0x2 #define RTL8367C_ACT74_CVID_OFFSET 0 #define RTL8367C_ACT74_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL38 0x06F6 #define RTL8367C_OP77_NOT_OFFSET 14 #define RTL8367C_OP77_NOT_MASK 0x4000 #define RTL8367C_ACT77_GPIO_OFFSET 13 #define RTL8367C_ACT77_GPIO_MASK 0x2000 #define RTL8367C_ACT77_FORWARD_OFFSET 12 #define RTL8367C_ACT77_FORWARD_MASK 0x1000 #define RTL8367C_ACT77_POLICING_OFFSET 11 #define RTL8367C_ACT77_POLICING_MASK 0x800 #define RTL8367C_ACT77_PRIORITY_OFFSET 10 #define RTL8367C_ACT77_PRIORITY_MASK 0x400 #define RTL8367C_ACT77_SVID_OFFSET 9 #define RTL8367C_ACT77_SVID_MASK 0x200 #define RTL8367C_ACT77_CVID_OFFSET 8 #define RTL8367C_ACT77_CVID_MASK 0x100 #define RTL8367C_OP76_NOT_OFFSET 6 #define RTL8367C_OP76_NOT_MASK 0x40 #define RTL8367C_ACT76_GPIO_OFFSET 5 #define RTL8367C_ACT76_GPIO_MASK 0x20 #define RTL8367C_ACT76_FORWARD_OFFSET 4 #define RTL8367C_ACT76_FORWARD_MASK 0x10 #define RTL8367C_ACT76_POLICING_OFFSET 3 #define RTL8367C_ACT76_POLICING_MASK 0x8 #define RTL8367C_ACT76_PRIORITY_OFFSET 2 #define RTL8367C_ACT76_PRIORITY_MASK 0x4 #define RTL8367C_ACT76_SVID_OFFSET 1 #define RTL8367C_ACT76_SVID_MASK 0x2 #define RTL8367C_ACT76_CVID_OFFSET 0 #define RTL8367C_ACT76_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL39 0x06F7 #define RTL8367C_OP79_NOT_OFFSET 14 #define RTL8367C_OP79_NOT_MASK 0x4000 #define RTL8367C_ACT79_GPIO_OFFSET 13 #define RTL8367C_ACT79_GPIO_MASK 0x2000 #define RTL8367C_ACT79_FORWARD_OFFSET 12 #define RTL8367C_ACT79_FORWARD_MASK 0x1000 #define RTL8367C_ACT79_POLICING_OFFSET 11 #define RTL8367C_ACT79_POLICING_MASK 0x800 #define RTL8367C_ACT79_PRIORITY_OFFSET 10 #define RTL8367C_ACT79_PRIORITY_MASK 0x400 #define RTL8367C_ACT79_SVID_OFFSET 9 #define RTL8367C_ACT79_SVID_MASK 0x200 #define RTL8367C_ACT79_CVID_OFFSET 8 #define RTL8367C_ACT79_CVID_MASK 0x100 #define RTL8367C_OP78_NOT_OFFSET 6 #define RTL8367C_OP78_NOT_MASK 0x40 #define RTL8367C_ACT78_GPIO_OFFSET 5 #define RTL8367C_ACT78_GPIO_MASK 0x20 #define RTL8367C_ACT78_FORWARD_OFFSET 4 #define RTL8367C_ACT78_FORWARD_MASK 0x10 #define RTL8367C_ACT78_POLICING_OFFSET 3 #define RTL8367C_ACT78_POLICING_MASK 0x8 #define RTL8367C_ACT78_PRIORITY_OFFSET 2 #define RTL8367C_ACT78_PRIORITY_MASK 0x4 #define RTL8367C_ACT78_SVID_OFFSET 1 #define RTL8367C_ACT78_SVID_MASK 0x2 #define RTL8367C_ACT78_CVID_OFFSET 0 #define RTL8367C_ACT78_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL40 0x06F8 #define RTL8367C_OP81_NOT_OFFSET 14 #define RTL8367C_OP81_NOT_MASK 0x4000 #define RTL8367C_ACT81_GPIO_OFFSET 13 #define RTL8367C_ACT81_GPIO_MASK 0x2000 #define RTL8367C_ACT81_FORWARD_OFFSET 12 #define RTL8367C_ACT81_FORWARD_MASK 0x1000 #define RTL8367C_ACT81_POLICING_OFFSET 11 #define RTL8367C_ACT81_POLICING_MASK 0x800 #define RTL8367C_ACT81_PRIORITY_OFFSET 10 #define RTL8367C_ACT81_PRIORITY_MASK 0x400 #define RTL8367C_ACT81_SVID_OFFSET 9 #define RTL8367C_ACT81_SVID_MASK 0x200 #define RTL8367C_ACT81_CVID_OFFSET 8 #define RTL8367C_ACT81_CVID_MASK 0x100 #define RTL8367C_OP80_NOT_OFFSET 6 #define RTL8367C_OP80_NOT_MASK 0x40 #define RTL8367C_ACT80_GPIO_OFFSET 5 #define RTL8367C_ACT80_GPIO_MASK 0x20 #define RTL8367C_ACT80_FORWARD_OFFSET 4 #define RTL8367C_ACT80_FORWARD_MASK 0x10 #define RTL8367C_ACT80_POLICING_OFFSET 3 #define RTL8367C_ACT80_POLICING_MASK 0x8 #define RTL8367C_ACT80_PRIORITY_OFFSET 2 #define RTL8367C_ACT80_PRIORITY_MASK 0x4 #define RTL8367C_ACT80_SVID_OFFSET 1 #define RTL8367C_ACT80_SVID_MASK 0x2 #define RTL8367C_ACT80_CVID_OFFSET 0 #define RTL8367C_ACT80_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL41 0x06F9 #define RTL8367C_OP83_NOT_OFFSET 14 #define RTL8367C_OP83_NOT_MASK 0x4000 #define RTL8367C_ACT83_GPIO_OFFSET 13 #define RTL8367C_ACT83_GPIO_MASK 0x2000 #define RTL8367C_ACT83_FORWARD_OFFSET 12 #define RTL8367C_ACT83_FORWARD_MASK 0x1000 #define RTL8367C_ACT83_POLICING_OFFSET 11 #define RTL8367C_ACT83_POLICING_MASK 0x800 #define RTL8367C_ACT83_PRIORITY_OFFSET 10 #define RTL8367C_ACT83_PRIORITY_MASK 0x400 #define RTL8367C_ACT83_SVID_OFFSET 9 #define RTL8367C_ACT83_SVID_MASK 0x200 #define RTL8367C_ACT83_CVID_OFFSET 8 #define RTL8367C_ACT83_CVID_MASK 0x100 #define RTL8367C_OP82_NOT_OFFSET 6 #define RTL8367C_OP82_NOT_MASK 0x40 #define RTL8367C_ACT82_GPIO_OFFSET 5 #define RTL8367C_ACT82_GPIO_MASK 0x20 #define RTL8367C_ACT82_FORWARD_OFFSET 4 #define RTL8367C_ACT82_FORWARD_MASK 0x10 #define RTL8367C_ACT82_POLICING_OFFSET 3 #define RTL8367C_ACT82_POLICING_MASK 0x8 #define RTL8367C_ACT82_PRIORITY_OFFSET 2 #define RTL8367C_ACT82_PRIORITY_MASK 0x4 #define RTL8367C_ACT82_SVID_OFFSET 1 #define RTL8367C_ACT82_SVID_MASK 0x2 #define RTL8367C_ACT82_CVID_OFFSET 0 #define RTL8367C_ACT82_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL42 0x06FA #define RTL8367C_OP85_NOT_OFFSET 14 #define RTL8367C_OP85_NOT_MASK 0x4000 #define RTL8367C_ACT85_GPIO_OFFSET 13 #define RTL8367C_ACT85_GPIO_MASK 0x2000 #define RTL8367C_ACT85_FORWARD_OFFSET 12 #define RTL8367C_ACT85_FORWARD_MASK 0x1000 #define RTL8367C_ACT85_POLICING_OFFSET 11 #define RTL8367C_ACT85_POLICING_MASK 0x800 #define RTL8367C_ACT85_PRIORITY_OFFSET 10 #define RTL8367C_ACT85_PRIORITY_MASK 0x400 #define RTL8367C_ACT85_SVID_OFFSET 9 #define RTL8367C_ACT85_SVID_MASK 0x200 #define RTL8367C_ACT85_CVID_OFFSET 8 #define RTL8367C_ACT85_CVID_MASK 0x100 #define RTL8367C_OP84_NOT_OFFSET 6 #define RTL8367C_OP84_NOT_MASK 0x40 #define RTL8367C_ACT84_GPIO_OFFSET 5 #define RTL8367C_ACT84_GPIO_MASK 0x20 #define RTL8367C_ACT84_FORWARD_OFFSET 4 #define RTL8367C_ACT84_FORWARD_MASK 0x10 #define RTL8367C_ACT84_POLICING_OFFSET 3 #define RTL8367C_ACT84_POLICING_MASK 0x8 #define RTL8367C_ACT84_PRIORITY_OFFSET 2 #define RTL8367C_ACT84_PRIORITY_MASK 0x4 #define RTL8367C_ACT84_SVID_OFFSET 1 #define RTL8367C_ACT84_SVID_MASK 0x2 #define RTL8367C_ACT84_CVID_OFFSET 0 #define RTL8367C_ACT84_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL43 0x06FB #define RTL8367C_OP87_NOT_OFFSET 14 #define RTL8367C_OP87_NOT_MASK 0x4000 #define RTL8367C_ACT87_GPIO_OFFSET 13 #define RTL8367C_ACT87_GPIO_MASK 0x2000 #define RTL8367C_ACT87_FORWARD_OFFSET 12 #define RTL8367C_ACT87_FORWARD_MASK 0x1000 #define RTL8367C_ACT87_POLICING_OFFSET 11 #define RTL8367C_ACT87_POLICING_MASK 0x800 #define RTL8367C_ACT87_PRIORITY_OFFSET 10 #define RTL8367C_ACT87_PRIORITY_MASK 0x400 #define RTL8367C_ACT87_SVID_OFFSET 9 #define RTL8367C_ACT87_SVID_MASK 0x200 #define RTL8367C_ACT87_CVID_OFFSET 8 #define RTL8367C_ACT87_CVID_MASK 0x100 #define RTL8367C_OP86_NOT_OFFSET 6 #define RTL8367C_OP86_NOT_MASK 0x40 #define RTL8367C_ACT86_GPIO_OFFSET 5 #define RTL8367C_ACT86_GPIO_MASK 0x20 #define RTL8367C_ACT86_FORWARD_OFFSET 4 #define RTL8367C_ACT86_FORWARD_MASK 0x10 #define RTL8367C_ACT86_POLICING_OFFSET 3 #define RTL8367C_ACT86_POLICING_MASK 0x8 #define RTL8367C_ACT86_PRIORITY_OFFSET 2 #define RTL8367C_ACT86_PRIORITY_MASK 0x4 #define RTL8367C_ACT86_SVID_OFFSET 1 #define RTL8367C_ACT86_SVID_MASK 0x2 #define RTL8367C_ACT86_CVID_OFFSET 0 #define RTL8367C_ACT86_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL44 0x06FC #define RTL8367C_OP89_NOT_OFFSET 14 #define RTL8367C_OP89_NOT_MASK 0x4000 #define RTL8367C_ACT89_GPIO_OFFSET 13 #define RTL8367C_ACT89_GPIO_MASK 0x2000 #define RTL8367C_ACT89_FORWARD_OFFSET 12 #define RTL8367C_ACT89_FORWARD_MASK 0x1000 #define RTL8367C_ACT89_POLICING_OFFSET 11 #define RTL8367C_ACT89_POLICING_MASK 0x800 #define RTL8367C_ACT89_PRIORITY_OFFSET 10 #define RTL8367C_ACT89_PRIORITY_MASK 0x400 #define RTL8367C_ACT89_SVID_OFFSET 9 #define RTL8367C_ACT89_SVID_MASK 0x200 #define RTL8367C_ACT89_CVID_OFFSET 8 #define RTL8367C_ACT89_CVID_MASK 0x100 #define RTL8367C_OP88_NOT_OFFSET 6 #define RTL8367C_OP88_NOT_MASK 0x40 #define RTL8367C_ACT88_GPIO_OFFSET 5 #define RTL8367C_ACT88_GPIO_MASK 0x20 #define RTL8367C_ACT88_FORWARD_OFFSET 4 #define RTL8367C_ACT88_FORWARD_MASK 0x10 #define RTL8367C_ACT88_POLICING_OFFSET 3 #define RTL8367C_ACT88_POLICING_MASK 0x8 #define RTL8367C_ACT88_PRIORITY_OFFSET 2 #define RTL8367C_ACT88_PRIORITY_MASK 0x4 #define RTL8367C_ACT88_SVID_OFFSET 1 #define RTL8367C_ACT88_SVID_MASK 0x2 #define RTL8367C_ACT88_CVID_OFFSET 0 #define RTL8367C_ACT88_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL45 0x06FD #define RTL8367C_OP91_NOT_OFFSET 14 #define RTL8367C_OP91_NOT_MASK 0x4000 #define RTL8367C_ACT91_GPIO_OFFSET 13 #define RTL8367C_ACT91_GPIO_MASK 0x2000 #define RTL8367C_ACT91_FORWARD_OFFSET 12 #define RTL8367C_ACT91_FORWARD_MASK 0x1000 #define RTL8367C_ACT91_POLICING_OFFSET 11 #define RTL8367C_ACT91_POLICING_MASK 0x800 #define RTL8367C_ACT91_PRIORITY_OFFSET 10 #define RTL8367C_ACT91_PRIORITY_MASK 0x400 #define RTL8367C_ACT91_SVID_OFFSET 9 #define RTL8367C_ACT91_SVID_MASK 0x200 #define RTL8367C_ACT91_CVID_OFFSET 8 #define RTL8367C_ACT91_CVID_MASK 0x100 #define RTL8367C_OP90_NOT_OFFSET 6 #define RTL8367C_OP90_NOT_MASK 0x40 #define RTL8367C_ACT90_GPIO_OFFSET 5 #define RTL8367C_ACT90_GPIO_MASK 0x20 #define RTL8367C_ACT90_FORWARD_OFFSET 4 #define RTL8367C_ACT90_FORWARD_MASK 0x10 #define RTL8367C_ACT90_POLICING_OFFSET 3 #define RTL8367C_ACT90_POLICING_MASK 0x8 #define RTL8367C_ACT90_PRIORITY_OFFSET 2 #define RTL8367C_ACT90_PRIORITY_MASK 0x4 #define RTL8367C_ACT90_SVID_OFFSET 1 #define RTL8367C_ACT90_SVID_MASK 0x2 #define RTL8367C_ACT90_CVID_OFFSET 0 #define RTL8367C_ACT90_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL46 0x06FE #define RTL8367C_OP93_NOT_OFFSET 14 #define RTL8367C_OP93_NOT_MASK 0x4000 #define RTL8367C_ACT93_GPIO_OFFSET 13 #define RTL8367C_ACT93_GPIO_MASK 0x2000 #define RTL8367C_ACT93_FORWARD_OFFSET 12 #define RTL8367C_ACT93_FORWARD_MASK 0x1000 #define RTL8367C_ACT93_POLICING_OFFSET 11 #define RTL8367C_ACT93_POLICING_MASK 0x800 #define RTL8367C_ACT93_PRIORITY_OFFSET 10 #define RTL8367C_ACT93_PRIORITY_MASK 0x400 #define RTL8367C_ACT93_SVID_OFFSET 9 #define RTL8367C_ACT93_SVID_MASK 0x200 #define RTL8367C_ACT93_CVID_OFFSET 8 #define RTL8367C_ACT93_CVID_MASK 0x100 #define RTL8367C_OP92_NOT_OFFSET 6 #define RTL8367C_OP92_NOT_MASK 0x40 #define RTL8367C_ACT92_GPIO_OFFSET 5 #define RTL8367C_ACT92_GPIO_MASK 0x20 #define RTL8367C_ACT92_FORWARD_OFFSET 4 #define RTL8367C_ACT92_FORWARD_MASK 0x10 #define RTL8367C_ACT92_POLICING_OFFSET 3 #define RTL8367C_ACT92_POLICING_MASK 0x8 #define RTL8367C_ACT92_PRIORITY_OFFSET 2 #define RTL8367C_ACT92_PRIORITY_MASK 0x4 #define RTL8367C_ACT92_SVID_OFFSET 1 #define RTL8367C_ACT92_SVID_MASK 0x2 #define RTL8367C_ACT92_CVID_OFFSET 0 #define RTL8367C_ACT92_CVID_MASK 0x1 #define RTL8367C_REG_ACL_ACTION_CTRL47 0x06FF #define RTL8367C_OP95_NOT_OFFSET 14 #define RTL8367C_OP95_NOT_MASK 0x4000 #define RTL8367C_ACT95_GPIO_OFFSET 13 #define RTL8367C_ACT95_GPIO_MASK 0x2000 #define RTL8367C_ACT95_FORWARD_OFFSET 12 #define RTL8367C_ACT95_FORWARD_MASK 0x1000 #define RTL8367C_ACT95_POLICING_OFFSET 11 #define RTL8367C_ACT95_POLICING_MASK 0x800 #define RTL8367C_ACT95_PRIORITY_OFFSET 10 #define RTL8367C_ACT95_PRIORITY_MASK 0x400 #define RTL8367C_ACT95_SVID_OFFSET 9 #define RTL8367C_ACT95_SVID_MASK 0x200 #define RTL8367C_ACT95_CVID_OFFSET 8 #define RTL8367C_ACT95_CVID_MASK 0x100 #define RTL8367C_OP94_NOT_OFFSET 6 #define RTL8367C_OP94_NOT_MASK 0x40 #define RTL8367C_ACT94_GPIO_OFFSET 5 #define RTL8367C_ACT94_GPIO_MASK 0x20 #define RTL8367C_ACT94_FORWARD_OFFSET 4 #define RTL8367C_ACT94_FORWARD_MASK 0x10 #define RTL8367C_ACT94_POLICING_OFFSET 3 #define RTL8367C_ACT94_POLICING_MASK 0x8 #define RTL8367C_ACT94_PRIORITY_OFFSET 2 #define RTL8367C_ACT94_PRIORITY_MASK 0x4 #define RTL8367C_ACT94_SVID_OFFSET 1 #define RTL8367C_ACT94_SVID_MASK 0x2 #define RTL8367C_ACT94_CVID_OFFSET 0 #define RTL8367C_ACT94_CVID_MASK 0x1 /* (16'h0700)cvlan_reg */ #define RTL8367C_REG_VLAN_PVID_CTRL0 0x0700 #define RTL8367C_PORT1_VIDX_OFFSET 8 #define RTL8367C_PORT1_VIDX_MASK 0x1F00 #define RTL8367C_PORT0_VIDX_OFFSET 0 #define RTL8367C_PORT0_VIDX_MASK 0x1F #define RTL8367C_REG_VLAN_PVID_CTRL1 0x0701 #define RTL8367C_PORT3_VIDX_OFFSET 8 #define RTL8367C_PORT3_VIDX_MASK 0x1F00 #define RTL8367C_PORT2_VIDX_OFFSET 0 #define RTL8367C_PORT2_VIDX_MASK 0x1F #define RTL8367C_REG_VLAN_PVID_CTRL2 0x0702 #define RTL8367C_PORT5_VIDX_OFFSET 8 #define RTL8367C_PORT5_VIDX_MASK 0x1F00 #define RTL8367C_PORT4_VIDX_OFFSET 0 #define RTL8367C_PORT4_VIDX_MASK 0x1F #define RTL8367C_REG_VLAN_PVID_CTRL3 0x0703 #define RTL8367C_PORT7_VIDX_OFFSET 8 #define RTL8367C_PORT7_VIDX_MASK 0x1F00 #define RTL8367C_PORT6_VIDX_OFFSET 0 #define RTL8367C_PORT6_VIDX_MASK 0x1F #define RTL8367C_REG_VLAN_PVID_CTRL4 0x0704 #define RTL8367C_PORT9_VIDX_OFFSET 8 #define RTL8367C_PORT9_VIDX_MASK 0x1F00 #define RTL8367C_PORT8_VIDX_OFFSET 0 #define RTL8367C_PORT8_VIDX_MASK 0x1F #define RTL8367C_REG_VLAN_PVID_CTRL5 0x0705 #define RTL8367C_VLAN_PVID_CTRL5_OFFSET 0 #define RTL8367C_VLAN_PVID_CTRL5_MASK 0x1F #define RTL8367C_REG_VLAN_PPB0_VALID 0x0708 #define RTL8367C_VLAN_PPB0_VALID_VALID_EXT_OFFSET 8 #define RTL8367C_VLAN_PPB0_VALID_VALID_EXT_MASK 0x700 #define RTL8367C_VLAN_PPB0_VALID_VALID_OFFSET 0 #define RTL8367C_VLAN_PPB0_VALID_VALID_MASK 0xFF #define RTL8367C_REG_VLAN_PPB0_CTRL0 0x0709 #define RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB0_CTRL1 0x070a #define RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB0_CTRL2 0x070b #define RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_OFFSET 10 #define RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_MASK 0xC00 #define RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB0_CTRL4 0x070c #define RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB0_CTRL3 0x070f #define RTL8367C_REG_VLAN_PPB1_VALID 0x0710 #define RTL8367C_VLAN_PPB1_VALID_VALID_EXT_OFFSET 8 #define RTL8367C_VLAN_PPB1_VALID_VALID_EXT_MASK 0x700 #define RTL8367C_VLAN_PPB1_VALID_VALID_OFFSET 0 #define RTL8367C_VLAN_PPB1_VALID_VALID_MASK 0xFF #define RTL8367C_REG_VLAN_PPB1_CTRL0 0x0711 #define RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB1_CTRL1 0x0712 #define RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB1_CTRL2 0x0713 #define RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_OFFSET 10 #define RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_MASK 0xC00 #define RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB1_CTRL4 0x0714 #define RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB1_CTRL3 0x0717 #define RTL8367C_REG_VLAN_PPB2_VALID 0x0718 #define RTL8367C_VLAN_PPB2_VALID_VALID_EXT_OFFSET 8 #define RTL8367C_VLAN_PPB2_VALID_VALID_EXT_MASK 0x700 #define RTL8367C_VLAN_PPB2_VALID_VALID_OFFSET 0 #define RTL8367C_VLAN_PPB2_VALID_VALID_MASK 0xFF #define RTL8367C_REG_VLAN_PPB2_CTRL0 0x0719 #define RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB2_CTRL1 0x071a #define RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB2_CTRL2 0x071b #define RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_OFFSET 10 #define RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_MASK 0xC00 #define RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB2_CTRL4 0x071c #define RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB2_CTRL3 0x071f #define RTL8367C_REG_VLAN_PPB3_VALID 0x0720 #define RTL8367C_VLAN_PPB3_VALID_VALID_EXT_OFFSET 8 #define RTL8367C_VLAN_PPB3_VALID_VALID_EXT_MASK 0x700 #define RTL8367C_VLAN_PPB3_VALID_VALID_OFFSET 0 #define RTL8367C_VLAN_PPB3_VALID_VALID_MASK 0xFF #define RTL8367C_REG_VLAN_PPB3_CTRL0 0x0721 #define RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB3_CTRL1 0x0722 #define RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB3_CTRL2 0x0723 #define RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_OFFSET 10 #define RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_MASK 0xC00 #define RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB3_CTRL4 0x0724 #define RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_OFFSET 10 #define RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_MASK 0x7C00 #define RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_OFFSET 5 #define RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_MASK 0x3E0 #define RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_OFFSET 0 #define RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_MASK 0x1F #define RTL8367C_REG_VLAN_PPB3_CTRL3 0x0727 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0 0x0728 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL1 0x0729 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL2 0x072a #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL3 0x072b #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL0 0x072c #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL1 0x072d #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL2 0x072e #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL3 0x072f #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL0 0x0730 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL1 0x0731 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL2 0x0732 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL3 0x0733 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL0 0x0734 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL1 0x0735 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL2 0x0736 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL3 0x0737 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL0 0x0738 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL1 0x0739 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL2 0x073a #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL3 0x073b #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL0 0x073c #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL1 0x073d #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL2 0x073e #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL3 0x073f #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL0 0x0740 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL1 0x0741 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL2 0x0742 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL3 0x0743 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL0 0x0744 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL1 0x0745 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL2 0x0746 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL3 0x0747 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL0 0x0748 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL1 0x0749 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL2 0x074a #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL3 0x074b #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL0 0x074c #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL1 0x074d #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL2 0x074e #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL3 0x074f #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL0 0x0750 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL1 0x0751 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL2 0x0752 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL3 0x0753 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL0 0x0754 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL1 0x0755 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL2 0x0756 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL3 0x0757 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL0 0x0758 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL1 0x0759 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL2 0x075a #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL3 0x075b #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL0 0x075c #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL1 0x075d #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL2 0x075e #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL3 0x075f #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL0 0x0760 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL1 0x0761 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL2 0x0762 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL3 0x0763 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL0 0x0764 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL1 0x0765 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL2 0x0766 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL3 0x0767 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL0 0x0768 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL1 0x0769 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL2 0x076a #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL3 0x076b #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL0 0x076c #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL1 0x076d #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL2 0x076e #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL3 0x076f #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL0 0x0770 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL1 0x0771 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL2 0x0772 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL3 0x0773 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL0 0x0774 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL1 0x0775 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL2 0x0776 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL3 0x0777 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL0 0x0778 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL1 0x0779 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL2 0x077a #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL3 0x077b #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL0 0x077c #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL1 0x077d #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL2 0x077e #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL3 0x077f #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL0 0x0780 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL1 0x0781 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL2 0x0782 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL3 0x0783 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL0 0x0784 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL1 0x0785 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL2 0x0786 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL3 0x0787 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL0 0x0788 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL1 0x0789 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL2 0x078a #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL3 0x078b #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL0 0x078c #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL1 0x078d #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL2 0x078e #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL3 0x078f #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL0 0x0790 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL1 0x0791 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL2 0x0792 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL3 0x0793 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL0 0x0794 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL1 0x0795 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL2 0x0796 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL3 0x0797 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL0 0x0798 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL1 0x0799 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL2 0x079a #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL3 0x079b #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL0 0x079c #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL1 0x079d #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL2 0x079e #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL3 0x079f #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL0 0x07a0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL1 0x07a1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL2 0x07a2 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL3 0x07a3 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL0 0x07a4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_OFFSET 8 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_MASK 0x700 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_MASK 0xFF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL1 0x07a5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_MASK 0xF #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL2 0x07a6 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_OFFSET 10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_MASK 0x400 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_OFFSET 5 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_MASK 0x3E0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_OFFSET 4 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_MASK 0x10 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_OFFSET 1 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_MASK 0xE #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_MASK 0x1 #define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL3 0x07a7 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_OFFSET 0 #define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_MASK 0x1FFF #define RTL8367C_REG_VLAN_CTRL 0x07a8 #define RTL8367C_VLAN_CTRL_OFFSET 0 #define RTL8367C_VLAN_CTRL_MASK 0x1 #define RTL8367C_REG_VLAN_INGRESS 0x07a9 #define RTL8367C_VLAN_INGRESS_OFFSET 0 #define RTL8367C_VLAN_INGRESS_MASK 0x7FF #define RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0 0x07aa #define RTL8367C_PORT7_FRAME_TYPE_OFFSET 14 #define RTL8367C_PORT7_FRAME_TYPE_MASK 0xC000 #define RTL8367C_PORT6_FRAME_TYPE_OFFSET 12 #define RTL8367C_PORT6_FRAME_TYPE_MASK 0x3000 #define RTL8367C_PORT5_FRAME_TYPE_OFFSET 10 #define RTL8367C_PORT5_FRAME_TYPE_MASK 0xC00 #define RTL8367C_PORT4_FRAME_TYPE_OFFSET 8 #define RTL8367C_PORT4_FRAME_TYPE_MASK 0x300 #define RTL8367C_PORT3_FRAME_TYPE_OFFSET 6 #define RTL8367C_PORT3_FRAME_TYPE_MASK 0xC0 #define RTL8367C_PORT2_FRAME_TYPE_OFFSET 4 #define RTL8367C_PORT2_FRAME_TYPE_MASK 0x30 #define RTL8367C_PORT1_FRAME_TYPE_OFFSET 2 #define RTL8367C_PORT1_FRAME_TYPE_MASK 0xC #define RTL8367C_PORT0_FRAME_TYPE_OFFSET 0 #define RTL8367C_PORT0_FRAME_TYPE_MASK 0x3 #define RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL1 0x07ab #define RTL8367C_PORT10_FRAME_TYPE_OFFSET 4 #define RTL8367C_PORT10_FRAME_TYPE_MASK 0x30 #define RTL8367C_PORT9_FRAME_TYPE_OFFSET 2 #define RTL8367C_PORT9_FRAME_TYPE_MASK 0xC #define RTL8367C_PORT8_FRAME_TYPE_OFFSET 0 #define RTL8367C_PORT8_FRAME_TYPE_MASK 0x3 #define RTL8367C_REG_PORT_PBFIDEN 0x07ac #define RTL8367C_PORT_PBFIDEN_OFFSET 0 #define RTL8367C_PORT_PBFIDEN_MASK 0x7FF #define RTL8367C_REG_PORT0_PBFID 0x07ad #define RTL8367C_PORT0_PBFID_OFFSET 0 #define RTL8367C_PORT0_PBFID_MASK 0xF #define RTL8367C_REG_PORT1_PBFID 0x07ae #define RTL8367C_PORT1_PBFID_OFFSET 0 #define RTL8367C_PORT1_PBFID_MASK 0xF #define RTL8367C_REG_PORT2_PBFID 0x07af #define RTL8367C_PORT2_PBFID_OFFSET 0 #define RTL8367C_PORT2_PBFID_MASK 0xF #define RTL8367C_REG_PORT3_PBFID 0x07b0 #define RTL8367C_PORT3_PBFID_OFFSET 0 #define RTL8367C_PORT3_PBFID_MASK 0xF #define RTL8367C_REG_PORT4_PBFID 0x07b1 #define RTL8367C_PORT4_PBFID_OFFSET 0 #define RTL8367C_PORT4_PBFID_MASK 0xF #define RTL8367C_REG_PORT5_PBFID 0x07b2 #define RTL8367C_PORT5_PBFID_OFFSET 0 #define RTL8367C_PORT5_PBFID_MASK 0xF #define RTL8367C_REG_PORT6_PBFID 0x07b3 #define RTL8367C_PORT6_PBFID_OFFSET 0 #define RTL8367C_PORT6_PBFID_MASK 0xF #define RTL8367C_REG_PORT7_PBFID 0x07b4 #define RTL8367C_PORT7_PBFID_OFFSET 0 #define RTL8367C_PORT7_PBFID_MASK 0xF #define RTL8367C_REG_VLAN_EXT_CTRL 0x07b5 #define RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET 2 #define RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_MASK 0x4 #define RTL8367C_VLAN_VID4095_TYPE_OFFSET 1 #define RTL8367C_VLAN_VID4095_TYPE_MASK 0x2 #define RTL8367C_VLAN_VID0_TYPE_OFFSET 0 #define RTL8367C_VLAN_VID0_TYPE_MASK 0x1 #define RTL8367C_REG_VLAN_EXT_CTRL2 0x07b6 #define RTL8367C_VLAN_EXT_CTRL2_OFFSET 0 #define RTL8367C_VLAN_EXT_CTRL2_MASK 0x1 #define RTL8367C_REG_PORT8_PBFID 0x07b7 #define RTL8367C_PORT8_PBFID_OFFSET 0 #define RTL8367C_PORT8_PBFID_MASK 0xF #define RTL8367C_REG_PORT9_PBFID 0x07b8 #define RTL8367C_PORT9_PBFID_OFFSET 0 #define RTL8367C_PORT9_PBFID_MASK 0xF #define RTL8367C_REG_PORT10_PBFID 0x07b9 #define RTL8367C_PORT10_PBFID_OFFSET 0 #define RTL8367C_PORT10_PBFID_MASK 0xF #define RTL8367C_REG_CVLAN_DUMMY00 0x07E0 #define RTL8367C_REG_CVLAN_DUMMY01 0x07E1 #define RTL8367C_REG_CVLAN_DUMMY02 0x07E2 #define RTL8367C_REG_CVLAN_DUMMY03 0x07E3 #define RTL8367C_REG_CVLAN_DUMMY04 0x07E4 #define RTL8367C_REG_CVLAN_DUMMY05 0x07E5 #define RTL8367C_REG_CVLAN_DUMMY06 0x07E6 #define RTL8367C_REG_CVLAN_DUMMY07 0x07E7 #define RTL8367C_REG_CVLAN_DUMMY08 0x07E8 #define RTL8367C_REG_CVLAN_DUMMY09 0x07E9 #define RTL8367C_REG_CVLAN_DUMMY10 0x07EA #define RTL8367C_REG_CVLAN_DUMMY11 0x07EB #define RTL8367C_REG_CVLAN_DUMMY12 0x07EC #define RTL8367C_REG_CVLAN_DUMMY13 0x07ED #define RTL8367C_REG_CVLAN_DUMMY14 0x07EE #define RTL8367C_REG_CVLAN_DUMMY15 0x07EF /* (16'h0800)dpm_reg */ #define RTL8367C_REG_RMA_CTRL00 0x0800 #define RTL8367C_RMA_CTRL00_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL00_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_TRAP_PRIORITY_OFFSET 3 #define RTL8367C_TRAP_PRIORITY_MASK 0x38 #define RTL8367C_RMA_CTRL00_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL00_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL00_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL00_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL00_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL00_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL01 0x0801 #define RTL8367C_RMA_CTRL01_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL01_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL01_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL01_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL01_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL01_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL01_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL01_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL02 0x0802 #define RTL8367C_RMA_CTRL02_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL02_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL02_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL02_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL02_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL02_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL02_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL02_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL03 0x0803 #define RTL8367C_RMA_CTRL03_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL03_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL03_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL03_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL03_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL03_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL03_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL03_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL04 0x0804 #define RTL8367C_RMA_CTRL04_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL04_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL04_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL04_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL04_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL04_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL04_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL04_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL08 0x0808 #define RTL8367C_RMA_CTRL08_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL08_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL08_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL08_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL08_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL08_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL08_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL08_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL0D 0x080d #define RTL8367C_RMA_CTRL0D_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL0D_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL0D_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL0D_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL0D_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL0D_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL0E 0x080e #define RTL8367C_RMA_CTRL0E_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL0E_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL0E_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL0E_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL0E_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL0E_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL10 0x0810 #define RTL8367C_RMA_CTRL10_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL10_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL10_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL10_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL10_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL10_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL10_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL10_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL11 0x0811 #define RTL8367C_RMA_CTRL11_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL11_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL11_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL11_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL11_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL11_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL11_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL11_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL12 0x0812 #define RTL8367C_RMA_CTRL12_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL12_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL12_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL12_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL12_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL12_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL12_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL12_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL13 0x0813 #define RTL8367C_RMA_CTRL13_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL13_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL13_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL13_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL13_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL13_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL13_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL13_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL18 0x0818 #define RTL8367C_RMA_CTRL18_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL18_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL18_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL18_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL18_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL18_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL18_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL18_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL1A 0x081a #define RTL8367C_RMA_CTRL1A_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL1A_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL1A_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL1A_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL1A_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL1A_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL20 0x0820 #define RTL8367C_RMA_CTRL20_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL20_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL20_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL20_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL20_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL20_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL20_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL20_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL21 0x0821 #define RTL8367C_RMA_CTRL21_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL21_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL21_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL21_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL21_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL21_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL21_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL21_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL22 0x0822 #define RTL8367C_RMA_CTRL22_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL22_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL22_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL22_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL22_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL22_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL22_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL22_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL_CDP 0x0830 #define RTL8367C_RMA_CTRL_CDP_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL_CDP_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL_CSSTP 0x0831 #define RTL8367C_RMA_CTRL_CSSTP_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL_CSSTP_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_CTRL_LLDP 0x0832 #define RTL8367C_RMA_CTRL_LLDP_OPERATION_OFFSET 7 #define RTL8367C_RMA_CTRL_LLDP_OPERATION_MASK 0x180 #define RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET 6 #define RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_MASK 0x40 #define RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET 2 #define RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_MASK 0x4 #define RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET 1 #define RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_MASK 0x2 #define RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_MASK 0x1 #define RTL8367C_REG_RMA_LLDP_EN 0x0833 #define RTL8367C_RMA_LLDP_EN_OFFSET 0 #define RTL8367C_RMA_LLDP_EN_MASK 0x1 #define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0 0x0851 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL1 0x0852 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL2 0x0853 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0 0x0855 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL1 0x0856 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL2 0x0857 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL0 0x0859 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL1 0x085a #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL2 0x085b #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL0 0x085d #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL1 0x085e #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL2 0x085f #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL0 0x0861 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL1 0x0862 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL2 0x0863 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 0x0865 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET 12 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK 0x7000 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET 8 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK 0x700 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET 4 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK 0x70 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET 0 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK 0x7 #define RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1 0x0866 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET 12 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK 0x7000 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET 8 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK 0x700 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET 4 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK 0x70 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET 0 #define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL0 0x0867 #define RTL8367C_DSCP3_PRIORITY_OFFSET 12 #define RTL8367C_DSCP3_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP2_PRIORITY_OFFSET 8 #define RTL8367C_DSCP2_PRIORITY_MASK 0x700 #define RTL8367C_DSCP1_PRIORITY_OFFSET 4 #define RTL8367C_DSCP1_PRIORITY_MASK 0x70 #define RTL8367C_DSCP0_PRIORITY_OFFSET 0 #define RTL8367C_DSCP0_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL1 0x0868 #define RTL8367C_DSCP7_PRIORITY_OFFSET 12 #define RTL8367C_DSCP7_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP6_PRIORITY_OFFSET 8 #define RTL8367C_DSCP6_PRIORITY_MASK 0x700 #define RTL8367C_DSCP5_PRIORITY_OFFSET 4 #define RTL8367C_DSCP5_PRIORITY_MASK 0x70 #define RTL8367C_DSCP4_PRIORITY_OFFSET 0 #define RTL8367C_DSCP4_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL2 0x0869 #define RTL8367C_DSCP11_PRIORITY_OFFSET 12 #define RTL8367C_DSCP11_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP10_PRIORITY_OFFSET 8 #define RTL8367C_DSCP10_PRIORITY_MASK 0x700 #define RTL8367C_DSCP9_PRIORITY_OFFSET 4 #define RTL8367C_DSCP9_PRIORITY_MASK 0x70 #define RTL8367C_DSCP8_PRIORITY_OFFSET 0 #define RTL8367C_DSCP8_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL3 0x086a #define RTL8367C_DSCP15_PRIORITY_OFFSET 12 #define RTL8367C_DSCP15_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP14_PRIORITY_OFFSET 8 #define RTL8367C_DSCP14_PRIORITY_MASK 0x700 #define RTL8367C_DSCP13_PRIORITY_OFFSET 4 #define RTL8367C_DSCP13_PRIORITY_MASK 0x70 #define RTL8367C_DSCP12_PRIORITY_OFFSET 0 #define RTL8367C_DSCP12_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL4 0x086b #define RTL8367C_DSCP19_PRIORITY_OFFSET 12 #define RTL8367C_DSCP19_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP18_PRIORITY_OFFSET 8 #define RTL8367C_DSCP18_PRIORITY_MASK 0x700 #define RTL8367C_DSCP17_PRIORITY_OFFSET 4 #define RTL8367C_DSCP17_PRIORITY_MASK 0x70 #define RTL8367C_DSCP16_PRIORITY_OFFSET 0 #define RTL8367C_DSCP16_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL5 0x086c #define RTL8367C_DSCP23_PRIORITY_OFFSET 12 #define RTL8367C_DSCP23_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP22_PRIORITY_OFFSET 8 #define RTL8367C_DSCP22_PRIORITY_MASK 0x700 #define RTL8367C_DSCP21_PRIORITY_OFFSET 4 #define RTL8367C_DSCP21_PRIORITY_MASK 0x70 #define RTL8367C_DSCP20_PRIORITY_OFFSET 0 #define RTL8367C_DSCP20_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL6 0x086d #define RTL8367C_DSCP27_PRIORITY_OFFSET 12 #define RTL8367C_DSCP27_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP26_PRIORITY_OFFSET 8 #define RTL8367C_DSCP26_PRIORITY_MASK 0x700 #define RTL8367C_DSCP25_PRIORITY_OFFSET 4 #define RTL8367C_DSCP25_PRIORITY_MASK 0x70 #define RTL8367C_DSCP24_PRIORITY_OFFSET 0 #define RTL8367C_DSCP24_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL7 0x086e #define RTL8367C_DSCP31_PRIORITY_OFFSET 12 #define RTL8367C_DSCP31_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP30_PRIORITY_OFFSET 8 #define RTL8367C_DSCP30_PRIORITY_MASK 0x700 #define RTL8367C_DSCP29_PRIORITY_OFFSET 4 #define RTL8367C_DSCP29_PRIORITY_MASK 0x70 #define RTL8367C_DSCP28_PRIORITY_OFFSET 0 #define RTL8367C_DSCP28_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL8 0x086f #define RTL8367C_DSCP35_PRIORITY_OFFSET 12 #define RTL8367C_DSCP35_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP34_PRIORITY_OFFSET 8 #define RTL8367C_DSCP34_PRIORITY_MASK 0x700 #define RTL8367C_DSCP33_PRIORITY_OFFSET 4 #define RTL8367C_DSCP33_PRIORITY_MASK 0x70 #define RTL8367C_DSCP32_PRIORITY_OFFSET 0 #define RTL8367C_DSCP32_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL9 0x0870 #define RTL8367C_DSCP39_PRIORITY_OFFSET 12 #define RTL8367C_DSCP39_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP38_PRIORITY_OFFSET 8 #define RTL8367C_DSCP38_PRIORITY_MASK 0x700 #define RTL8367C_DSCP37_PRIORITY_OFFSET 4 #define RTL8367C_DSCP37_PRIORITY_MASK 0x70 #define RTL8367C_DSCP36_PRIORITY_OFFSET 0 #define RTL8367C_DSCP36_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL10 0x0871 #define RTL8367C_DSCP43_PRIORITY_OFFSET 12 #define RTL8367C_DSCP43_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP42_PRIORITY_OFFSET 8 #define RTL8367C_DSCP42_PRIORITY_MASK 0x700 #define RTL8367C_DSCP41_PRIORITY_OFFSET 4 #define RTL8367C_DSCP41_PRIORITY_MASK 0x70 #define RTL8367C_DSCP40_PRIORITY_OFFSET 0 #define RTL8367C_DSCP40_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL11 0x0872 #define RTL8367C_DSCP47_PRIORITY_OFFSET 12 #define RTL8367C_DSCP47_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP46_PRIORITY_OFFSET 8 #define RTL8367C_DSCP46_PRIORITY_MASK 0x700 #define RTL8367C_DSCP45_PRIORITY_OFFSET 4 #define RTL8367C_DSCP45_PRIORITY_MASK 0x70 #define RTL8367C_DSCP44_PRIORITY_OFFSET 0 #define RTL8367C_DSCP44_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL12 0x0873 #define RTL8367C_DSCP51_PRIORITY_OFFSET 12 #define RTL8367C_DSCP51_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP50_PRIORITY_OFFSET 8 #define RTL8367C_DSCP50_PRIORITY_MASK 0x700 #define RTL8367C_DSCP49_PRIORITY_OFFSET 4 #define RTL8367C_DSCP49_PRIORITY_MASK 0x70 #define RTL8367C_DSCP48_PRIORITY_OFFSET 0 #define RTL8367C_DSCP48_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL13 0x0874 #define RTL8367C_DSCP55_PRIORITY_OFFSET 12 #define RTL8367C_DSCP55_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP54_PRIORITY_OFFSET 8 #define RTL8367C_DSCP54_PRIORITY_MASK 0x700 #define RTL8367C_DSCP53_PRIORITY_OFFSET 4 #define RTL8367C_DSCP53_PRIORITY_MASK 0x70 #define RTL8367C_DSCP52_PRIORITY_OFFSET 0 #define RTL8367C_DSCP52_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL14 0x0875 #define RTL8367C_DSCP59_PRIORITY_OFFSET 12 #define RTL8367C_DSCP59_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP58_PRIORITY_OFFSET 8 #define RTL8367C_DSCP58_PRIORITY_MASK 0x700 #define RTL8367C_DSCP57_PRIORITY_OFFSET 4 #define RTL8367C_DSCP57_PRIORITY_MASK 0x70 #define RTL8367C_DSCP56_PRIORITY_OFFSET 0 #define RTL8367C_DSCP56_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL15 0x0876 #define RTL8367C_DSCP63_PRIORITY_OFFSET 12 #define RTL8367C_DSCP63_PRIORITY_MASK 0x7000 #define RTL8367C_DSCP62_PRIORITY_OFFSET 8 #define RTL8367C_DSCP62_PRIORITY_MASK 0x700 #define RTL8367C_DSCP61_PRIORITY_OFFSET 4 #define RTL8367C_DSCP61_PRIORITY_MASK 0x70 #define RTL8367C_DSCP60_PRIORITY_OFFSET 0 #define RTL8367C_DSCP60_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL0 0x0877 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET 12 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK 0x7000 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET 8 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK 0x700 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET 4 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK 0x70 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET 0 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL1 0x0878 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET 12 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK 0x7000 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET 8 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK 0x700 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET 4 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK 0x70 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET 0 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK 0x7 #define RTL8367C_REG_DUMMY0879 0x0879 #define RTL8367C_DUMMY0879_OFFSET 0 #define RTL8367C_DUMMY0879_MASK 0x1 #define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2 0x087a #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET 8 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK 0x700 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET 4 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK 0x70 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET 0 #define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK 0x7 #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 0x087b #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1 0x087c #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2 0x087d #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL3 0x087e #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 0x087f #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET 12 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK 0x7000 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET 8 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK 0x700 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET 4 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK 0x70 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET 0 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK 0x7 #define RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1 0x0880 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET 12 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK 0x7000 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET 8 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK 0x700 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET 4 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK 0x70 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET 0 #define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK 0x7 #define RTL8367C_REG_QOS_TRAP_PRIORITY0 0x0881 #define RTL8367C_UNKNOWN_MC_PRIORTY_OFFSET 12 #define RTL8367C_UNKNOWN_MC_PRIORTY_MASK 0x7000 #define RTL8367C_SVLAN_PRIOIRTY_OFFSET 8 #define RTL8367C_SVLAN_PRIOIRTY_MASK 0x700 #define RTL8367C_OAM_PRIOIRTY_OFFSET 4 #define RTL8367C_OAM_PRIOIRTY_MASK 0x70 #define RTL8367C_DOT1X_PRIORTY_OFFSET 0 #define RTL8367C_DOT1X_PRIORTY_MASK 0x7 #define RTL8367C_REG_QOS_TRAP_PRIORITY1 0x0882 #define RTL8367C_DW8051_TRAP_PRI_OFFSET 4 #define RTL8367C_DW8051_TRAP_PRI_MASK 0x70 #define RTL8367C_EEELLDP_TRAP_PRI_OFFSET 0 #define RTL8367C_EEELLDP_TRAP_PRI_MASK 0x7 #define RTL8367C_REG_MAX_LENGTH_CFG 0x0883 #define RTL8367C_MAX_LENGTH_GIGA_OFFSET 8 #define RTL8367C_MAX_LENGTH_GIGA_MASK 0xFF00 #define RTL8367C_MAX_LENGTH_10_100M_OFFSET 0 #define RTL8367C_MAX_LENGTH_10_100M_MASK 0xFF #define RTL8367C_REG_MAX_LEN_RX_TX 0x0884 #define RTL8367C_MAX_LEN_RX_TX_OFFSET 0 #define RTL8367C_MAX_LEN_RX_TX_MASK 0x3 #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 0x0885 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1 0x0886 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2 0x0887 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3 0x0888 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_OFFSET 8 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_MASK 0xFF00 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_MASK 0xFF #define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX 0x0889 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_OFFSET 0 #define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_MASK 0x7FF #define RTL8367C_REG_MAX_LENGTH_CFG_EXT 0x088a #define RTL8367C_MAX_LENGTH_GIGA_EXT_OFFSET 3 #define RTL8367C_MAX_LENGTH_GIGA_EXT_MASK 0x38 #define RTL8367C_MAX_LENGTH_10_100M_EXT_OFFSET 0 #define RTL8367C_MAX_LENGTH_10_100M_EXT_MASK 0x7 #define RTL8367C_REG_MAX_LEN_RX_TX_CFG0 0x088c #define RTL8367C_MAX_LEN_RX_TX_CFG0_OFFSET 0 #define RTL8367C_MAX_LEN_RX_TX_CFG0_MASK 0x3FFF #define RTL8367C_REG_MAX_LEN_RX_TX_CFG1 0x088d #define RTL8367C_MAX_LEN_RX_TX_CFG1_OFFSET 0 #define RTL8367C_MAX_LEN_RX_TX_CFG1_MASK 0x3FFF #define RTL8367C_REG_UNDA_FLOODING_PMSK 0x0890 #define RTL8367C_UNDA_FLOODING_PMSK_OFFSET 0 #define RTL8367C_UNDA_FLOODING_PMSK_MASK 0x7FF #define RTL8367C_REG_UNMCAST_FLOADING_PMSK 0x0891 #define RTL8367C_UNMCAST_FLOADING_PMSK_OFFSET 0 #define RTL8367C_UNMCAST_FLOADING_PMSK_MASK 0x7FF #define RTL8367C_REG_BCAST_FLOADING_PMSK 0x0892 #define RTL8367C_BCAST_FLOADING_PMSK_OFFSET 0 #define RTL8367C_BCAST_FLOADING_PMSK_MASK 0x7FF #define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2 0x08a0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_OFFSET 14 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_MASK 0xC000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_OFFSET 12 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_MASK 0x3000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_OFFSET 10 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_MASK 0xC00 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_OFFSET 8 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_MASK 0x300 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_OFFSET 6 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_MASK 0xC0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_OFFSET 4 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_MASK 0x30 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_OFFSET 2 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_MASK 0xC #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_OFFSET 0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK 0x3 #define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3 0x08a1 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_OFFSET 14 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_MASK 0xC000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_OFFSET 12 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_MASK 0x3000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_OFFSET 10 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_MASK 0xC00 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_OFFSET 8 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_MASK 0x300 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_OFFSET 6 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_MASK 0xC0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_OFFSET 4 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_MASK 0x30 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_OFFSET 2 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_MASK 0xC #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_OFFSET 0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK 0x3 #define RTL8367C_REG_PORT_ISOLATION_PORT0_MASK 0x08a2 #define RTL8367C_PORT_ISOLATION_PORT0_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT0_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT1_MASK 0x08a3 #define RTL8367C_PORT_ISOLATION_PORT1_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT1_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT2_MASK 0x08a4 #define RTL8367C_PORT_ISOLATION_PORT2_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT2_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT3_MASK 0x08a5 #define RTL8367C_PORT_ISOLATION_PORT3_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT3_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT4_MASK 0x08a6 #define RTL8367C_PORT_ISOLATION_PORT4_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT4_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT5_MASK 0x08a7 #define RTL8367C_PORT_ISOLATION_PORT5_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT5_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT6_MASK 0x08a8 #define RTL8367C_PORT_ISOLATION_PORT6_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT6_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT7_MASK 0x08a9 #define RTL8367C_PORT_ISOLATION_PORT7_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT7_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT8_MASK 0x08aa #define RTL8367C_PORT_ISOLATION_PORT8_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT8_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT9_MASK 0x08ab #define RTL8367C_PORT_ISOLATION_PORT9_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT9_MASK_MASK 0x7FF #define RTL8367C_REG_PORT_ISOLATION_PORT10_MASK 0x08ac #define RTL8367C_PORT_ISOLATION_PORT10_MASK_OFFSET 0 #define RTL8367C_PORT_ISOLATION_PORT10_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_CTRL 0x08b4 #define RTL8367C_FORCE_CTRL_OFFSET 0 #define RTL8367C_FORCE_CTRL_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT0_MASK 0x08b5 #define RTL8367C_FORCE_PORT0_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT0_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT1_MASK 0x08b6 #define RTL8367C_FORCE_PORT1_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT1_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT2_MASK 0x08b7 #define RTL8367C_FORCE_PORT2_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT2_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT3_MASK 0x08b8 #define RTL8367C_FORCE_PORT3_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT3_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT4_MASK 0x08b9 #define RTL8367C_FORCE_PORT4_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT4_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT5_MASK 0x08ba #define RTL8367C_FORCE_PORT5_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT5_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT6_MASK 0x08bb #define RTL8367C_FORCE_PORT6_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT6_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT7_MASK 0x08bc #define RTL8367C_FORCE_PORT7_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT7_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT8_MASK 0x08bd #define RTL8367C_FORCE_PORT8_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT8_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT9_MASK 0x08be #define RTL8367C_FORCE_PORT9_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT9_MASK_MASK 0x7FF #define RTL8367C_REG_FORCE_PORT10_MASK 0x08bf #define RTL8367C_FORCE_PORT10_MASK_OFFSET 0 #define RTL8367C_FORCE_PORT10_MASK_MASK 0x7FF #define RTL8367C_REG_SOURCE_PORT_PERMIT 0x08c5 #define RTL8367C_SOURCE_PORT_PERMIT_OFFSET 0 #define RTL8367C_SOURCE_PORT_PERMIT_MASK 0x7FF #define RTL8367C_REG_IPMCAST_VLAN_LEAKY 0x08c6 #define RTL8367C_IPMCAST_VLAN_LEAKY_OFFSET 0 #define RTL8367C_IPMCAST_VLAN_LEAKY_MASK 0x7FF #define RTL8367C_REG_IPMCAST_PORTISO_LEAKY 0x08c7 #define RTL8367C_IPMCAST_PORTISO_LEAKY_OFFSET 0 #define RTL8367C_IPMCAST_PORTISO_LEAKY_MASK 0x7FF #define RTL8367C_REG_PORT_SECURITY_CTRL 0x08c8 #define RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_OFFSET 6 #define RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK 0xC0 #define RTL8367C_LUT_LEARN_OVER_ACT_OFFSET 4 #define RTL8367C_LUT_LEARN_OVER_ACT_MASK 0x30 #define RTL8367C_UNMATCHED_SA_BEHAVE_OFFSET 2 #define RTL8367C_UNMATCHED_SA_BEHAVE_MASK 0xC #define RTL8367C_UNKNOWN_SA_BEHAVE_OFFSET 0 #define RTL8367C_UNKNOWN_SA_BEHAVE_MASK 0x3 #define RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL0 0x08c9 #define RTL8367C_PORT7_UNKNOWN_IP4_MCAST_OFFSET 14 #define RTL8367C_PORT7_UNKNOWN_IP4_MCAST_MASK 0xC000 #define RTL8367C_PORT6_UNKNOWN_IP4_MCAST_OFFSET 12 #define RTL8367C_PORT6_UNKNOWN_IP4_MCAST_MASK 0x3000 #define RTL8367C_PORT5_UNKNOWN_IP4_MCAST_OFFSET 10 #define RTL8367C_PORT5_UNKNOWN_IP4_MCAST_MASK 0xC00 #define RTL8367C_PORT4_UNKNOWN_IP4_MCAST_OFFSET 8 #define RTL8367C_PORT4_UNKNOWN_IP4_MCAST_MASK 0x300 #define RTL8367C_PORT3_UNKNOWN_IP4_MCAST_OFFSET 6 #define RTL8367C_PORT3_UNKNOWN_IP4_MCAST_MASK 0xC0 #define RTL8367C_PORT2_UNKNOWN_IP4_MCAST_OFFSET 4 #define RTL8367C_PORT2_UNKNOWN_IP4_MCAST_MASK 0x30 #define RTL8367C_PORT1_UNKNOWN_IP4_MCAST_OFFSET 2 #define RTL8367C_PORT1_UNKNOWN_IP4_MCAST_MASK 0xC #define RTL8367C_PORT0_UNKNOWN_IP4_MCAST_OFFSET 0 #define RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK 0x3 #define RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL1 0x08ca #define RTL8367C_PORT10_UNKNOWN_IP4_MCAST_OFFSET 4 #define RTL8367C_PORT10_UNKNOWN_IP4_MCAST_MASK 0x30 #define RTL8367C_PORT9_UNKNOWN_IP4_MCAST_OFFSET 2 #define RTL8367C_PORT9_UNKNOWN_IP4_MCAST_MASK 0xC #define RTL8367C_PORT8_UNKNOWN_IP4_MCAST_OFFSET 0 #define RTL8367C_PORT8_UNKNOWN_IP4_MCAST_MASK 0x3 #define RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL0 0x08cb #define RTL8367C_PORT7_UNKNOWN_IP6_MCAST_OFFSET 14 #define RTL8367C_PORT7_UNKNOWN_IP6_MCAST_MASK 0xC000 #define RTL8367C_PORT6_UNKNOWN_IP6_MCAST_OFFSET 12 #define RTL8367C_PORT6_UNKNOWN_IP6_MCAST_MASK 0x3000 #define RTL8367C_PORT5_UNKNOWN_IP6_MCAST_OFFSET 10 #define RTL8367C_PORT5_UNKNOWN_IP6_MCAST_MASK 0xC00 #define RTL8367C_PORT4_UNKNOWN_IP6_MCAST_OFFSET 8 #define RTL8367C_PORT4_UNKNOWN_IP6_MCAST_MASK 0x300 #define RTL8367C_PORT3_UNKNOWN_IP6_MCAST_OFFSET 6 #define RTL8367C_PORT3_UNKNOWN_IP6_MCAST_MASK 0xC0 #define RTL8367C_PORT2_UNKNOWN_IP6_MCAST_OFFSET 4 #define RTL8367C_PORT2_UNKNOWN_IP6_MCAST_MASK 0x30 #define RTL8367C_PORT1_UNKNOWN_IP6_MCAST_OFFSET 2 #define RTL8367C_PORT1_UNKNOWN_IP6_MCAST_MASK 0xC #define RTL8367C_PORT0_UNKNOWN_IP6_MCAST_OFFSET 0 #define RTL8367C_PORT0_UNKNOWN_IP6_MCAST_MASK 0x3 #define RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL1 0x08cc #define RTL8367C_PORT10_UNKNOWN_IP6_MCAST_OFFSET 4 #define RTL8367C_PORT10_UNKNOWN_IP6_MCAST_MASK 0x30 #define RTL8367C_PORT9_UNKNOWN_IP6_MCAST_OFFSET 2 #define RTL8367C_PORT9_UNKNOWN_IP6_MCAST_MASK 0xC #define RTL8367C_PORT8_UNKNOWN_IP6_MCAST_OFFSET 0 #define RTL8367C_PORT8_UNKNOWN_IP6_MCAST_MASK 0x3 #define RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL0 0x08cd #define RTL8367C_PORT7_UNKNOWN_L2_MCAST_OFFSET 14 #define RTL8367C_PORT7_UNKNOWN_L2_MCAST_MASK 0xC000 #define RTL8367C_PORT6_UNKNOWN_L2_MCAST_OFFSET 12 #define RTL8367C_PORT6_UNKNOWN_L2_MCAST_MASK 0x3000 #define RTL8367C_PORT5_UNKNOWN_L2_MCAST_OFFSET 10 #define RTL8367C_PORT5_UNKNOWN_L2_MCAST_MASK 0xC00 #define RTL8367C_PORT4_UNKNOWN_L2_MCAST_OFFSET 8 #define RTL8367C_PORT4_UNKNOWN_L2_MCAST_MASK 0x300 #define RTL8367C_PORT3_UNKNOWN_L2_MCAST_OFFSET 6 #define RTL8367C_PORT3_UNKNOWN_L2_MCAST_MASK 0xC0 #define RTL8367C_PORT2_UNKNOWN_L2_MCAST_OFFSET 4 #define RTL8367C_PORT2_UNKNOWN_L2_MCAST_MASK 0x30 #define RTL8367C_PORT1_UNKNOWN_L2_MCAST_OFFSET 2 #define RTL8367C_PORT1_UNKNOWN_L2_MCAST_MASK 0xC #define RTL8367C_PORT0_UNKNOWN_L2_MCAST_OFFSET 0 #define RTL8367C_PORT0_UNKNOWN_L2_MCAST_MASK 0x3 #define RTL8367C_REG_PORT_TRUNK_DROP_CTRL 0x08ce #define RTL8367C_PORT_TRUNK_DROP_CTRL_OFFSET 0 #define RTL8367C_PORT_TRUNK_DROP_CTRL_MASK 0x1 #define RTL8367C_REG_PORT_TRUNK_CTRL 0x08cf #define RTL8367C_PORT_TRUNK_DUMB_OFFSET 8 #define RTL8367C_PORT_TRUNK_DUMB_MASK 0x100 #define RTL8367C_PORT_TRUNK_FLOOD_OFFSET 7 #define RTL8367C_PORT_TRUNK_FLOOD_MASK 0x80 #define RTL8367C_DPORT_HASH_OFFSET 6 #define RTL8367C_DPORT_HASH_MASK 0x40 #define RTL8367C_SPORT_HASH_OFFSET 5 #define RTL8367C_SPORT_HASH_MASK 0x20 #define RTL8367C_DIP_HASH_OFFSET 4 #define RTL8367C_DIP_HASH_MASK 0x10 #define RTL8367C_SIP_HASH_OFFSET 3 #define RTL8367C_SIP_HASH_MASK 0x8 #define RTL8367C_DMAC_HASH_OFFSET 2 #define RTL8367C_DMAC_HASH_MASK 0x4 #define RTL8367C_SMAC_HASH_OFFSET 1 #define RTL8367C_SMAC_HASH_MASK 0x2 #define RTL8367C_SPA_HASH_OFFSET 0 #define RTL8367C_SPA_HASH_MASK 0x1 #define RTL8367C_REG_PORT_TRUNK_GROUP_MASK 0x08d0 #define RTL8367C_PORT_TRUNK_GROUP2_MASK_OFFSET 8 #define RTL8367C_PORT_TRUNK_GROUP2_MASK_MASK 0x300 #define RTL8367C_PORT_TRUNK_GROUP1_MASK_OFFSET 4 #define RTL8367C_PORT_TRUNK_GROUP1_MASK_MASK 0xF0 #define RTL8367C_PORT_TRUNK_GROUP0_MASK_OFFSET 0 #define RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK 0xF #define RTL8367C_REG_PORT_TRUNK_FLOWCTRL 0x08d1 #define RTL8367C_EN_FLOWCTRL_TG2_OFFSET 2 #define RTL8367C_EN_FLOWCTRL_TG2_MASK 0x4 #define RTL8367C_EN_FLOWCTRL_TG1_OFFSET 1 #define RTL8367C_EN_FLOWCTRL_TG1_MASK 0x2 #define RTL8367C_EN_FLOWCTRL_TG0_OFFSET 0 #define RTL8367C_EN_FLOWCTRL_TG0_MASK 0x1 #define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0 0x08d2 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_OFFSET 14 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_MASK 0xC000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_OFFSET 12 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_MASK 0x3000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_OFFSET 10 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_MASK 0xC00 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_OFFSET 8 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_MASK 0x300 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_OFFSET 6 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_MASK 0xC0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_OFFSET 4 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_MASK 0x30 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_OFFSET 2 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_MASK 0xC #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_OFFSET 0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK 0x3 #define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1 0x08d3 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_OFFSET 14 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_MASK 0xC000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_OFFSET 12 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_MASK 0x3000 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_OFFSET 10 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_MASK 0xC00 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_OFFSET 8 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_MASK 0x300 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_OFFSET 6 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_MASK 0xC0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_OFFSET 4 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_MASK 0x30 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_OFFSET 2 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_MASK 0xC #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_OFFSET 0 #define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK 0x3 #define RTL8367C_REG_DOS_CFG 0x08d4 #define RTL8367C_DROP_ICMPFRAGMENT_OFFSET 9 #define RTL8367C_DROP_ICMPFRAGMENT_MASK 0x200 #define RTL8367C_DROP_TCPFRAGERROR_OFFSET 8 #define RTL8367C_DROP_TCPFRAGERROR_MASK 0x100 #define RTL8367C_DROP_TCPSHORTHDR_OFFSET 7 #define RTL8367C_DROP_TCPSHORTHDR_MASK 0x80 #define RTL8367C_DROP_SYN1024_OFFSET 6 #define RTL8367C_DROP_SYN1024_MASK 0x40 #define RTL8367C_DROP_NULLSCAN_OFFSET 5 #define RTL8367C_DROP_NULLSCAN_MASK 0x20 #define RTL8367C_DROP_XMASCAN_OFFSET 4 #define RTL8367C_DROP_XMASCAN_MASK 0x10 #define RTL8367C_DROP_SYNFINSCAN_OFFSET 3 #define RTL8367C_DROP_SYNFINSCAN_MASK 0x8 #define RTL8367C_DROP_BLATATTACKS_OFFSET 2 #define RTL8367C_DROP_BLATATTACKS_MASK 0x4 #define RTL8367C_DROP_LANDATTACKS_OFFSET 1 #define RTL8367C_DROP_LANDATTACKS_MASK 0x2 #define RTL8367C_DROP_DAEQSA_OFFSET 0 #define RTL8367C_DROP_DAEQSA_MASK 0x1 #define RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1 0x08d5 #define RTL8367C_PORT10_UNKNOWN_L2_MCAST_OFFSET 4 #define RTL8367C_PORT10_UNKNOWN_L2_MCAST_MASK 0x30 #define RTL8367C_PORT9_UNKNOWN_L2_MCAST_OFFSET 2 #define RTL8367C_PORT9_UNKNOWN_L2_MCAST_MASK 0xC #define RTL8367C_PORT8_UNKNOWN_L2_MCAST_OFFSET 0 #define RTL8367C_PORT8_UNKNOWN_L2_MCAST_MASK 0x3 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4 0x08d6 #define RTL8367C_PORT9_VLAN_KEEP_MASK_OFFSET 8 #define RTL8367C_PORT9_VLAN_KEEP_MASK_MASK 0xFF00 #define RTL8367C_PORT8_VLAN_KEEP_MASK_OFFSET 0 #define RTL8367C_PORT8_VLAN_KEEP_MASK_MASK 0xFF #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5 0x08d7 #define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_OFFSET 0 #define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK 0xFF #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT 0x08d8 #define RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_OFFSET 3 #define RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_MASK 0x38 #define RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_OFFSET 0 #define RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1_EXT 0x08d9 #define RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_OFFSET 3 #define RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_MASK 0x38 #define RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_OFFSET 0 #define RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2_EXT 0x08da #define RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_OFFSET 3 #define RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_MASK 0x38 #define RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_OFFSET 0 #define RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3_EXT 0x08db #define RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_OFFSET 3 #define RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_MASK 0x38 #define RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_OFFSET 0 #define RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT 0x08dc #define RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_OFFSET 3 #define RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK 0x38 #define RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_OFFSET 0 #define RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT 0x08dd #define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_OFFSET 0 #define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK 0x7 #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL10 0x08de #define RTL8367C_VLAN_EGRESS_TRANS_CTRL10_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL10_MASK 0x7FF #define RTL8367C_REG_FPGA_VER_CEN 0x08e0 #define RTL8367C_REG_FPGA_TIME_CEN 0x08e1 #define RTL8367C_REG_FPGA_DATE_CEN 0x08e2 #define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 0x0900 #define RTL8367C_PORT3_NUMBER_OFFSET 12 #define RTL8367C_PORT3_NUMBER_MASK 0x7000 #define RTL8367C_PORT2_NUMBER_OFFSET 8 #define RTL8367C_PORT2_NUMBER_MASK 0x700 #define RTL8367C_PORT1_NUMBER_OFFSET 4 #define RTL8367C_PORT1_NUMBER_MASK 0x70 #define RTL8367C_PORT0_NUMBER_OFFSET 0 #define RTL8367C_PORT0_NUMBER_MASK 0x7 #define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL1 0x0901 #define RTL8367C_PORT7_NUMBER_OFFSET 12 #define RTL8367C_PORT7_NUMBER_MASK 0x7000 #define RTL8367C_PORT6_NUMBER_OFFSET 8 #define RTL8367C_PORT6_NUMBER_MASK 0x700 #define RTL8367C_PORT5_NUMBER_OFFSET 4 #define RTL8367C_PORT5_NUMBER_MASK 0x70 #define RTL8367C_PORT4_NUMBER_OFFSET 0 #define RTL8367C_PORT4_NUMBER_MASK 0x7 #define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL2 0x0902 #define RTL8367C_PORT10_NUMBER_OFFSET 8 #define RTL8367C_PORT10_NUMBER_MASK 0x700 #define RTL8367C_PORT9_NUMBER_OFFSET 4 #define RTL8367C_PORT9_NUMBER_MASK 0x70 #define RTL8367C_PORT8_NUMBER_OFFSET 0 #define RTL8367C_PORT8_NUMBER_MASK 0x7 #define RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 0x0904 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1 0x0905 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0 0x0906 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1 0x0907 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0 0x0908 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1 0x0909 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0 0x090a #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1 0x090b #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0 0x090c #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1 0x090d #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0 0x090e #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1 0x090f #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0 0x0910 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1 0x0911 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0 0x0912 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 #define RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1 0x0913 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 #define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 #define RTL8367C_REG_HIGHPRI_INDICATOR 0x0915 #define RTL8367C_PORT10_INDICATOR_OFFSET 10 #define RTL8367C_PORT10_INDICATOR_MASK 0x400 #define RTL8367C_PORT9_INDICATOR_OFFSET 9 #define RTL8367C_PORT9_INDICATOR_MASK 0x200 #define RTL8367C_PORT8_INDICATOR_OFFSET 8 #define RTL8367C_PORT8_INDICATOR_MASK 0x100 #define RTL8367C_PORT7_INDICATOR_OFFSET 7 #define RTL8367C_PORT7_INDICATOR_MASK 0x80 #define RTL8367C_PORT6_INDICATOR_OFFSET 6 #define RTL8367C_PORT6_INDICATOR_MASK 0x40 #define RTL8367C_PORT5_INDICATOR_OFFSET 5 #define RTL8367C_PORT5_INDICATOR_MASK 0x20 #define RTL8367C_PORT4_INDICATOR_OFFSET 4 #define RTL8367C_PORT4_INDICATOR_MASK 0x10 #define RTL8367C_PORT3_INDICATOR_OFFSET 3 #define RTL8367C_PORT3_INDICATOR_MASK 0x8 #define RTL8367C_PORT2_INDICATOR_OFFSET 2 #define RTL8367C_PORT2_INDICATOR_MASK 0x4 #define RTL8367C_PORT1_INDICATOR_OFFSET 1 #define RTL8367C_PORT1_INDICATOR_MASK 0x2 #define RTL8367C_PORT0_INDICATOR_OFFSET 0 #define RTL8367C_PORT0_INDICATOR_MASK 0x1 #define RTL8367C_REG_HIGHPRI_CFG 0x0916 #define RTL8367C_HIGHPRI_CFG_OFFSET 0 #define RTL8367C_HIGHPRI_CFG_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL0 0x0917 #define RTL8367C_PORT1_DEBUG_INFO_OFFSET 8 #define RTL8367C_PORT1_DEBUG_INFO_MASK 0xFF00 #define RTL8367C_PORT0_DEBUG_INFO_OFFSET 0 #define RTL8367C_PORT0_DEBUG_INFO_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL1 0x0918 #define RTL8367C_PORT3_DEBUG_INFO_OFFSET 8 #define RTL8367C_PORT3_DEBUG_INFO_MASK 0xFF00 #define RTL8367C_PORT2_DEBUG_INFO_OFFSET 0 #define RTL8367C_PORT2_DEBUG_INFO_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL2 0x0919 #define RTL8367C_PORT5_DEBUG_INFO_OFFSET 8 #define RTL8367C_PORT5_DEBUG_INFO_MASK 0xFF00 #define RTL8367C_PORT4_DEBUG_INFO_OFFSET 0 #define RTL8367C_PORT4_DEBUG_INFO_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL3 0x091a #define RTL8367C_PORT7_DEBUG_INFO_OFFSET 8 #define RTL8367C_PORT7_DEBUG_INFO_MASK 0xFF00 #define RTL8367C_PORT6_DEBUG_INFO_OFFSET 0 #define RTL8367C_PORT6_DEBUG_INFO_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL5 0x091b #define RTL8367C_PORT9_DEBUG_INFO_OFFSET 8 #define RTL8367C_PORT9_DEBUG_INFO_MASK 0xFF00 #define RTL8367C_PORT8_DEBUG_INFO_OFFSET 0 #define RTL8367C_PORT8_DEBUG_INFO_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL6 0x091c #define RTL8367C_PORT_DEBUG_INFO_CTRL6_OFFSET 0 #define RTL8367C_PORT_DEBUG_INFO_CTRL6_MASK 0xFF #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL4 0x091d #define RTL8367C_PORT7_DEBUG_INDICATOR_OFFSET 14 #define RTL8367C_PORT7_DEBUG_INDICATOR_MASK 0xC000 #define RTL8367C_PORT6_DEBUG_INDICATOR_OFFSET 12 #define RTL8367C_PORT6_DEBUG_INDICATOR_MASK 0x3000 #define RTL8367C_PORT5_DEBUG_INDICATOR_OFFSET 10 #define RTL8367C_PORT5_DEBUG_INDICATOR_MASK 0xC00 #define RTL8367C_PORT4_DEBUG_INDICATOR_OFFSET 8 #define RTL8367C_PORT4_DEBUG_INDICATOR_MASK 0x300 #define RTL8367C_PORT3_DEBUG_INDICATOR_OFFSET 6 #define RTL8367C_PORT3_DEBUG_INDICATOR_MASK 0xC0 #define RTL8367C_PORT2_DEBUG_INDICATOR_OFFSET 4 #define RTL8367C_PORT2_DEBUG_INDICATOR_MASK 0x30 #define RTL8367C_PORT1_DEBUG_INDICATOR_OFFSET 2 #define RTL8367C_PORT1_DEBUG_INDICATOR_MASK 0xC #define RTL8367C_PORT0_DEBUG_INDICATOR_OFFSET 0 #define RTL8367C_PORT0_DEBUG_INDICATOR_MASK 0x3 #define RTL8367C_REG_PORT_DEBUG_INFO_CTRL7 0x091e #define RTL8367C_PORT10_DEBUG_INDICATOR_OFFSET 4 #define RTL8367C_PORT10_DEBUG_INDICATOR_MASK 0x30 #define RTL8367C_PORT9_DEBUG_INDICATOR_OFFSET 2 #define RTL8367C_PORT9_DEBUG_INDICATOR_MASK 0xC #define RTL8367C_PORT8_DEBUG_INDICATOR_OFFSET 0 #define RTL8367C_PORT8_DEBUG_INDICATOR_MASK 0x3 #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0 0x0930 #define RTL8367C_PORT1_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT1_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT0_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT0_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1 0x0931 #define RTL8367C_PORT3_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT3_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT2_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT2_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2 0x0932 #define RTL8367C_PORT5_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT5_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT4_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT4_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3 0x0933 #define RTL8367C_PORT7_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT7_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT6_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT6_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4 0x0934 #define RTL8367C_PORT9_QUEUE_MASK_OFFSET 8 #define RTL8367C_PORT9_QUEUE_MASK_MASK 0xFF00 #define RTL8367C_PORT8_QUEUE_MASK_OFFSET 0 #define RTL8367C_PORT8_QUEUE_MASK_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5 0x0935 #define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_OFFSET 0 #define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_MASK 0xFF #define RTL8367C_REG_FLOWCRTL_EGRESS_PORT_ENABLE 0x0938 #define RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_OFFSET 0 #define RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_MASK 0xFF #define RTL8367C_REG_EAV_CTRL 0x0939 #define RTL8367C_EAV_TRAP_CPU_OFFSET 1 #define RTL8367C_EAV_TRAP_CPU_MASK 0x2 #define RTL8367C_EAV_TRAP_8051_OFFSET 0 #define RTL8367C_EAV_TRAP_8051_MASK 0x1 #define RTL8367C_REG_UNTAG_DSCP_PRI_CFG 0x093a #define RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET 0 #define RTL8367C_UNTAG_DSCP_PRI_CFG_MASK 0x1 #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 0x093b #define RTL8367C_PORT1_VLAN_KEEP_MASK_OFFSET 8 #define RTL8367C_PORT1_VLAN_KEEP_MASK_MASK 0xFF00 #define RTL8367C_PORT0_VLAN_KEEP_MASK_OFFSET 0 #define RTL8367C_PORT0_VLAN_KEEP_MASK_MASK 0xFF #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1 0x093c #define RTL8367C_PORT3_VLAN_KEEP_MASK_OFFSET 8 #define RTL8367C_PORT3_VLAN_KEEP_MASK_MASK 0xFF00 #define RTL8367C_PORT2_VLAN_KEEP_MASK_OFFSET 0 #define RTL8367C_PORT2_VLAN_KEEP_MASK_MASK 0xFF #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2 0x093d #define RTL8367C_PORT5_VLAN_KEEP_MASK_OFFSET 8 #define RTL8367C_PORT5_VLAN_KEEP_MASK_MASK 0xFF00 #define RTL8367C_PORT4_VLAN_KEEP_MASK_OFFSET 0 #define RTL8367C_PORT4_VLAN_KEEP_MASK_MASK 0xFF #define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3 0x093e #define RTL8367C_PORT7_VLAN_KEEP_MASK_OFFSET 8 #define RTL8367C_PORT7_VLAN_KEEP_MASK_MASK 0xFF00 #define RTL8367C_PORT6_VLAN_KEEP_MASK_OFFSET 0 #define RTL8367C_PORT6_VLAN_KEEP_MASK_MASK 0xFF #define RTL8367C_REG_VLAN_TRANSPARENT_EN_CFG 0x093f #define RTL8367C_VLAN_TRANSPARENT_EN_CFG_OFFSET 0 #define RTL8367C_VLAN_TRANSPARENT_EN_CFG_MASK 0x1 #define RTL8367C_REG_IPMC_GROUP_ENTRY0_H 0x0940 #define RTL8367C_IPMC_GROUP_ENTRY0_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY0_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY0_L 0x0941 #define RTL8367C_REG_IPMC_GROUP_ENTRY1_H 0x0942 #define RTL8367C_IPMC_GROUP_ENTRY1_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY1_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY1_L 0x0943 #define RTL8367C_REG_IPMC_GROUP_ENTRY2_H 0x0944 #define RTL8367C_IPMC_GROUP_ENTRY2_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY2_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY2_L 0x0945 #define RTL8367C_REG_IPMC_GROUP_ENTRY3_H 0x0946 #define RTL8367C_IPMC_GROUP_ENTRY3_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY3_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY3_L 0x0947 #define RTL8367C_REG_IPMC_GROUP_ENTRY4_H 0x0948 #define RTL8367C_IPMC_GROUP_ENTRY4_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY4_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY4_L 0x0949 #define RTL8367C_REG_IPMC_GROUP_ENTRY5_H 0x094a #define RTL8367C_IPMC_GROUP_ENTRY5_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY5_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY5_L 0x094b #define RTL8367C_REG_IPMC_GROUP_ENTRY6_H 0x094c #define RTL8367C_IPMC_GROUP_ENTRY6_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY6_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY6_L 0x094d #define RTL8367C_REG_IPMC_GROUP_ENTRY7_H 0x094e #define RTL8367C_IPMC_GROUP_ENTRY7_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY7_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY7_L 0x094f #define RTL8367C_REG_IPMC_GROUP_ENTRY8_H 0x0950 #define RTL8367C_IPMC_GROUP_ENTRY8_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY8_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY8_L 0x0951 #define RTL8367C_REG_IPMC_GROUP_ENTRY9_H 0x0952 #define RTL8367C_IPMC_GROUP_ENTRY9_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY9_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY9_L 0x0953 #define RTL8367C_REG_IPMC_GROUP_ENTRY10_H 0x0954 #define RTL8367C_IPMC_GROUP_ENTRY10_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY10_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY10_L 0x0955 #define RTL8367C_REG_IPMC_GROUP_ENTRY11_H 0x0956 #define RTL8367C_IPMC_GROUP_ENTRY11_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY11_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY11_L 0x0957 #define RTL8367C_REG_IPMC_GROUP_ENTRY12_H 0x0958 #define RTL8367C_IPMC_GROUP_ENTRY12_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY12_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY12_L 0x0959 #define RTL8367C_REG_IPMC_GROUP_ENTRY13_H 0x095a #define RTL8367C_IPMC_GROUP_ENTRY13_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY13_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY13_L 0x095b #define RTL8367C_REG_IPMC_GROUP_ENTRY14_H 0x095c #define RTL8367C_IPMC_GROUP_ENTRY14_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY14_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY14_L 0x095d #define RTL8367C_REG_IPMC_GROUP_ENTRY15_H 0x095e #define RTL8367C_IPMC_GROUP_ENTRY15_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY15_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY15_L 0x095f #define RTL8367C_REG_IPMC_GROUP_ENTRY16_H 0x0960 #define RTL8367C_IPMC_GROUP_ENTRY16_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY16_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY16_L 0x0961 #define RTL8367C_REG_IPMC_GROUP_ENTRY17_H 0x0962 #define RTL8367C_IPMC_GROUP_ENTRY17_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY17_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY17_L 0x0963 #define RTL8367C_REG_IPMC_GROUP_ENTRY18_H 0x0964 #define RTL8367C_IPMC_GROUP_ENTRY18_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY18_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY18_L 0x0965 #define RTL8367C_REG_IPMC_GROUP_ENTRY19_H 0x0966 #define RTL8367C_IPMC_GROUP_ENTRY19_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY19_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY19_L 0x0967 #define RTL8367C_REG_IPMC_GROUP_ENTRY20_H 0x0968 #define RTL8367C_IPMC_GROUP_ENTRY20_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY20_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY20_L 0x0969 #define RTL8367C_REG_IPMC_GROUP_ENTRY21_H 0x096a #define RTL8367C_IPMC_GROUP_ENTRY21_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY21_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY21_L 0x096b #define RTL8367C_REG_IPMC_GROUP_ENTRY22_H 0x096c #define RTL8367C_IPMC_GROUP_ENTRY22_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY22_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY22_L 0x096d #define RTL8367C_REG_IPMC_GROUP_ENTRY23_H 0x096e #define RTL8367C_IPMC_GROUP_ENTRY23_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY23_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY23_L 0x096f #define RTL8367C_REG_IPMC_GROUP_ENTRY24_H 0x0970 #define RTL8367C_IPMC_GROUP_ENTRY24_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY24_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY24_L 0x0971 #define RTL8367C_REG_IPMC_GROUP_ENTRY25_H 0x0972 #define RTL8367C_IPMC_GROUP_ENTRY25_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY25_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY25_L 0x0973 #define RTL8367C_REG_IPMC_GROUP_ENTRY26_H 0x0974 #define RTL8367C_IPMC_GROUP_ENTRY26_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY26_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY26_L 0x0975 #define RTL8367C_REG_IPMC_GROUP_ENTRY27_H 0x0976 #define RTL8367C_IPMC_GROUP_ENTRY27_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY27_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY27_L 0x0977 #define RTL8367C_REG_IPMC_GROUP_ENTRY28_H 0x0978 #define RTL8367C_IPMC_GROUP_ENTRY28_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY28_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY28_L 0x0979 #define RTL8367C_REG_IPMC_GROUP_ENTRY29_H 0x097a #define RTL8367C_IPMC_GROUP_ENTRY29_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY29_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY29_L 0x097b #define RTL8367C_REG_IPMC_GROUP_ENTRY30_H 0x097c #define RTL8367C_IPMC_GROUP_ENTRY30_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY30_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY30_L 0x097d #define RTL8367C_REG_IPMC_GROUP_ENTRY31_H 0x097e #define RTL8367C_IPMC_GROUP_ENTRY31_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY31_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY31_L 0x097f #define RTL8367C_REG_IPMC_GROUP_ENTRY32_H 0x0980 #define RTL8367C_IPMC_GROUP_ENTRY32_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY32_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY32_L 0x0981 #define RTL8367C_REG_IPMC_GROUP_ENTRY33_H 0x0982 #define RTL8367C_IPMC_GROUP_ENTRY33_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY33_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY33_L 0x0983 #define RTL8367C_REG_IPMC_GROUP_ENTRY34_H 0x0984 #define RTL8367C_IPMC_GROUP_ENTRY34_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY34_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY34_L 0x0985 #define RTL8367C_REG_IPMC_GROUP_ENTRY35_H 0x0986 #define RTL8367C_IPMC_GROUP_ENTRY35_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY35_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY35_L 0x0987 #define RTL8367C_REG_IPMC_GROUP_ENTRY36_H 0x0988 #define RTL8367C_IPMC_GROUP_ENTRY36_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY36_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY36_L 0x0989 #define RTL8367C_REG_IPMC_GROUP_ENTRY37_H 0x098a #define RTL8367C_IPMC_GROUP_ENTRY37_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY37_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY37_L 0x098b #define RTL8367C_REG_IPMC_GROUP_ENTRY38_H 0x098c #define RTL8367C_IPMC_GROUP_ENTRY38_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY38_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY38_L 0x098d #define RTL8367C_REG_IPMC_GROUP_ENTRY39_H 0x098e #define RTL8367C_IPMC_GROUP_ENTRY39_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY39_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY39_L 0x098f #define RTL8367C_REG_IPMC_GROUP_ENTRY40_H 0x0990 #define RTL8367C_IPMC_GROUP_ENTRY40_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY40_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY40_L 0x0991 #define RTL8367C_REG_IPMC_GROUP_ENTRY41_H 0x0992 #define RTL8367C_IPMC_GROUP_ENTRY41_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY41_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY41_L 0x0993 #define RTL8367C_REG_IPMC_GROUP_ENTRY42_H 0x0994 #define RTL8367C_IPMC_GROUP_ENTRY42_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY42_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY42_L 0x0995 #define RTL8367C_REG_IPMC_GROUP_ENTRY43_H 0x0996 #define RTL8367C_IPMC_GROUP_ENTRY43_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY43_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY43_L 0x0997 #define RTL8367C_REG_IPMC_GROUP_ENTRY44_H 0x0998 #define RTL8367C_IPMC_GROUP_ENTRY44_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY44_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY44_L 0x0999 #define RTL8367C_REG_IPMC_GROUP_ENTRY45_H 0x099a #define RTL8367C_IPMC_GROUP_ENTRY45_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY45_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY45_L 0x099b #define RTL8367C_REG_IPMC_GROUP_ENTRY46_H 0x099c #define RTL8367C_IPMC_GROUP_ENTRY46_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY46_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY46_L 0x099d #define RTL8367C_REG_IPMC_GROUP_ENTRY47_H 0x099e #define RTL8367C_IPMC_GROUP_ENTRY47_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY47_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY47_L 0x099f #define RTL8367C_REG_IPMC_GROUP_ENTRY48_H 0x09a0 #define RTL8367C_IPMC_GROUP_ENTRY48_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY48_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY48_L 0x09a1 #define RTL8367C_REG_IPMC_GROUP_ENTRY49_H 0x09a2 #define RTL8367C_IPMC_GROUP_ENTRY49_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY49_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY49_L 0x09a3 #define RTL8367C_REG_IPMC_GROUP_ENTRY50_H 0x09a4 #define RTL8367C_IPMC_GROUP_ENTRY50_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY50_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY50_L 0x09a5 #define RTL8367C_REG_IPMC_GROUP_ENTRY51_H 0x09a6 #define RTL8367C_IPMC_GROUP_ENTRY51_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY51_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY51_L 0x09a7 #define RTL8367C_REG_IPMC_GROUP_ENTRY52_H 0x09a8 #define RTL8367C_IPMC_GROUP_ENTRY52_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY52_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY52_L 0x09a9 #define RTL8367C_REG_IPMC_GROUP_ENTRY53_H 0x09aa #define RTL8367C_IPMC_GROUP_ENTRY53_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY53_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY53_L 0x09ab #define RTL8367C_REG_IPMC_GROUP_ENTRY54_H 0x09ac #define RTL8367C_IPMC_GROUP_ENTRY54_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY54_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY54_L 0x09ad #define RTL8367C_REG_IPMC_GROUP_ENTRY55_H 0x09ae #define RTL8367C_IPMC_GROUP_ENTRY55_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY55_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY55_L 0x09af #define RTL8367C_REG_IPMC_GROUP_ENTRY56_H 0x09b0 #define RTL8367C_IPMC_GROUP_ENTRY56_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY56_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY56_L 0x09b1 #define RTL8367C_REG_IPMC_GROUP_ENTRY57_H 0x09b2 #define RTL8367C_IPMC_GROUP_ENTRY57_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY57_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY57_L 0x09b3 #define RTL8367C_REG_IPMC_GROUP_ENTRY58_H 0x09b4 #define RTL8367C_IPMC_GROUP_ENTRY58_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY58_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY58_L 0x09b5 #define RTL8367C_REG_IPMC_GROUP_ENTRY59_H 0x09b6 #define RTL8367C_IPMC_GROUP_ENTRY59_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY59_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY59_L 0x09b7 #define RTL8367C_REG_IPMC_GROUP_ENTRY60_H 0x09b8 #define RTL8367C_IPMC_GROUP_ENTRY60_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY60_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY60_L 0x09b9 #define RTL8367C_REG_IPMC_GROUP_ENTRY61_H 0x09ba #define RTL8367C_IPMC_GROUP_ENTRY61_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY61_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY61_L 0x09bb #define RTL8367C_REG_IPMC_GROUP_ENTRY62_H 0x09bc #define RTL8367C_IPMC_GROUP_ENTRY62_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY62_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY62_L 0x09bd #define RTL8367C_REG_IPMC_GROUP_ENTRY63_H 0x09be #define RTL8367C_IPMC_GROUP_ENTRY63_H_OFFSET 0 #define RTL8367C_IPMC_GROUP_ENTRY63_H_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_ENTRY63_L 0x09bf #define RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE 0x09C0 #define RTL8367C_Port7_ACTION_OFFSET 14 #define RTL8367C_Port7_ACTION_MASK 0xC000 #define RTL8367C_Port6_ACTION_OFFSET 12 #define RTL8367C_Port6_ACTION_MASK 0x3000 #define RTL8367C_Port5_ACTION_OFFSET 10 #define RTL8367C_Port5_ACTION_MASK 0xC00 #define RTL8367C_Port4_ACTION_OFFSET 8 #define RTL8367C_Port4_ACTION_MASK 0x300 #define RTL8367C_Port3_ACTION_OFFSET 6 #define RTL8367C_Port3_ACTION_MASK 0xC0 #define RTL8367C_Port2_ACTION_OFFSET 4 #define RTL8367C_Port2_ACTION_MASK 0x30 #define RTL8367C_Port1_ACTION_OFFSET 2 #define RTL8367C_Port1_ACTION_MASK 0xC #define RTL8367C_Port0_ACTION_OFFSET 0 #define RTL8367C_Port0_ACTION_MASK 0x3 #define RTL8367C_REG_MIRROR_CTRL3 0x09C1 #define RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET 2 #define RTL8367C_MIRROR_ACL_OVERRIDE_EN_MASK 0x4 #define RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET 1 #define RTL8367C_MIRROR_TX_OVERRIDE_EN_MASK 0x2 #define RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET 0 #define RTL8367C_MIRROR_RX_OVERRIDE_EN_MASK 0x1 #define RTL8367C_REG_DPM_DUMMY02 0x09C2 #define RTL8367C_REG_DPM_DUMMY03 0x09C3 #define RTL8367C_REG_DPM_DUMMY04 0x09C4 #define RTL8367C_REG_DPM_DUMMY05 0x09C5 #define RTL8367C_REG_DPM_DUMMY06 0x09C6 #define RTL8367C_REG_DPM_DUMMY07 0x09C7 #define RTL8367C_REG_DPM_DUMMY08 0x09C8 #define RTL8367C_REG_DPM_DUMMY09 0x09C9 #define RTL8367C_REG_DPM_DUMMY10 0x09CA #define RTL8367C_REG_DPM_DUMMY11 0x09CB #define RTL8367C_REG_DPM_DUMMY12 0x09CC #define RTL8367C_REG_DPM_DUMMY13 0x09CD #define RTL8367C_REG_DPM_DUMMY14 0x09CE #define RTL8367C_REG_DPM_DUMMY15 0x09CF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 0x09D0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL0_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL1 0x09D1 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL1_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL1_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL2 0x09D2 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL2_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL2_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL3 0x09D3 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL3_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL3_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL4 0x09D4 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL4_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL4_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL5 0x09D5 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL5_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL5_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL6 0x09D6 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL6_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL6_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL7 0x09D7 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL7_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL7_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL8 0x09D8 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL8_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL8_MASK 0x7FF #define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL9 0x09D9 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL9_OFFSET 0 #define RTL8367C_VLAN_EGRESS_TRANS_CTRL9_MASK 0x7FF #define RTL8367C_REG_MIRROR_CTRL2 0x09DA #define RTL8367C_MIRROR_REALKEEP_EN_OFFSET 4 #define RTL8367C_MIRROR_REALKEEP_EN_MASK 0x10 #define RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET 3 #define RTL8367C_MIRROR_RX_ISOLATION_LEAKY_MASK 0x8 #define RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET 2 #define RTL8367C_MIRROR_TX_ISOLATION_LEAKY_MASK 0x4 #define RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET 1 #define RTL8367C_MIRROR_RX_VLAN_LEAKY_MASK 0x2 #define RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET 0 #define RTL8367C_MIRROR_TX_VLAN_LEAKY_MASK 0x1 #define RTL8367C_REG_OUTPUT_DROP_CFG 0x09DB #define RTL8367C_ENABLE_PMASK_EXT_OFFSET 13 #define RTL8367C_ENABLE_PMASK_EXT_MASK 0xE000 #define RTL8367C_ENABLE_BC_OFFSET 12 #define RTL8367C_ENABLE_BC_MASK 0x1000 #define RTL8367C_ENABLE_MC_OFFSET 11 #define RTL8367C_ENABLE_MC_MASK 0x800 #define RTL8367C_ENABLE_UC_OFFSET 10 #define RTL8367C_ENABLE_UC_MASK 0x400 #define RTL8367C_ENABLE_PMASK_OFFSET 0 #define RTL8367C_ENABLE_PMASK_MASK 0xFF #define RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT 0x09DC #define RTL8367C_PORT10_ACTION_OFFSET 4 #define RTL8367C_PORT10_ACTION_MASK 0x30 #define RTL8367C_PORT9_ACTION_OFFSET 2 #define RTL8367C_PORT9_ACTION_MASK 0xC #define RTL8367C_PORT8_ACTION_OFFSET 0 #define RTL8367C_PORT8_ACTION_MASK 0x3 #define RTL8367C_REG_RMK_CFG_SEL_CTRL 0x09DF #define RTL8367C_RMK_1Q_CFG_SEL_OFFSET 2 #define RTL8367C_RMK_1Q_CFG_SEL_MASK 0x4 #define RTL8367C_RMK_DSCP_CFG_SEL_OFFSET 0 #define RTL8367C_RMK_DSCP_CFG_SEL_MASK 0x3 #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0 0x09E0 #define RTL8367C_DSCP1_DSCP_OFFSET 8 #define RTL8367C_DSCP1_DSCP_MASK 0x3F00 #define RTL8367C_DSCP0_DSCP_OFFSET 0 #define RTL8367C_DSCP0_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL1 0x09E1 #define RTL8367C_DSCP3_DSCP_OFFSET 8 #define RTL8367C_DSCP3_DSCP_MASK 0x3F00 #define RTL8367C_DSCP2_DSCP_OFFSET 0 #define RTL8367C_DSCP2_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL2 0x09E2 #define RTL8367C_DSCP5_DSCP_OFFSET 8 #define RTL8367C_DSCP5_DSCP_MASK 0x3F00 #define RTL8367C_DSCP4_DSCP_OFFSET 0 #define RTL8367C_DSCP4_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL3 0x09E3 #define RTL8367C_DSCP7_DSCP_OFFSET 8 #define RTL8367C_DSCP7_DSCP_MASK 0x3F00 #define RTL8367C_DSCP6_DSCP_OFFSET 0 #define RTL8367C_DSCP6_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL4 0x09E4 #define RTL8367C_DSCP9_DSCP_OFFSET 8 #define RTL8367C_DSCP9_DSCP_MASK 0x3F00 #define RTL8367C_DSCP8_DSCP_OFFSET 0 #define RTL8367C_DSCP8_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL5 0x09E5 #define RTL8367C_DSCP11_DSCP_OFFSET 8 #define RTL8367C_DSCP11_DSCP_MASK 0x3F00 #define RTL8367C_DSCP10_DSCP_OFFSET 0 #define RTL8367C_DSCP10_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL6 0x09E6 #define RTL8367C_DSCP13_DSCP_OFFSET 8 #define RTL8367C_DSCP13_DSCP_MASK 0x3F00 #define RTL8367C_DSCP12_DSCP_OFFSET 0 #define RTL8367C_DSCP12_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL7 0x09E7 #define RTL8367C_DSCP15_DSCP_OFFSET 8 #define RTL8367C_DSCP15_DSCP_MASK 0x3F00 #define RTL8367C_DSCP14_DSCP_OFFSET 0 #define RTL8367C_DSCP14_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL8 0x09E8 #define RTL8367C_DSCP17_DSCP_OFFSET 8 #define RTL8367C_DSCP17_DSCP_MASK 0x3F00 #define RTL8367C_DSCP16_DSCP_OFFSET 0 #define RTL8367C_DSCP16_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL9 0x09E9 #define RTL8367C_DSCP19_DSCP_OFFSET 8 #define RTL8367C_DSCP19_DSCP_MASK 0x3F00 #define RTL8367C_DSCP18_DSCP_OFFSET 0 #define RTL8367C_DSCP18_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL10 0x09EA #define RTL8367C_DSCP21_DSCP_OFFSET 8 #define RTL8367C_DSCP21_DSCP_MASK 0x3F00 #define RTL8367C_DSCP20_DSCP_OFFSET 0 #define RTL8367C_DSCP20_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL11 0x09EB #define RTL8367C_DSCP23_DSCP_OFFSET 8 #define RTL8367C_DSCP23_DSCP_MASK 0x3F00 #define RTL8367C_DSCP22_DSCP_OFFSET 0 #define RTL8367C_DSCP22_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL12 0x09EC #define RTL8367C_DSCP25_DSCP_OFFSET 8 #define RTL8367C_DSCP25_DSCP_MASK 0x3F00 #define RTL8367C_DSCP24_DSCP_OFFSET 0 #define RTL8367C_DSCP24_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL13 0x09ED #define RTL8367C_DSCP27_DSCP_OFFSET 8 #define RTL8367C_DSCP27_DSCP_MASK 0x3F00 #define RTL8367C_DSCP26_DSCP_OFFSET 0 #define RTL8367C_DSCP26_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL14 0x09EE #define RTL8367C_DSCP29_DSCP_OFFSET 8 #define RTL8367C_DSCP29_DSCP_MASK 0x3F00 #define RTL8367C_DSCP28_DSCP_OFFSET 0 #define RTL8367C_DSCP28_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL15 0x09EF #define RTL8367C_DSCP31_DSCP_OFFSET 8 #define RTL8367C_DSCP31_DSCP_MASK 0x3F00 #define RTL8367C_DSCP30_DSCP_OFFSET 0 #define RTL8367C_DSCP30_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL16 0x09F0 #define RTL8367C_DSCP33_DSCP_OFFSET 8 #define RTL8367C_DSCP33_DSCP_MASK 0x3F00 #define RTL8367C_DSCP32_DSCP_OFFSET 0 #define RTL8367C_DSCP32_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL17 0x09F1 #define RTL8367C_DSCP35_DSCP_OFFSET 8 #define RTL8367C_DSCP35_DSCP_MASK 0x3F00 #define RTL8367C_DSCP34_DSCP_OFFSET 0 #define RTL8367C_DSCP34_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL18 0x09F2 #define RTL8367C_DSCP37_DSCP_OFFSET 8 #define RTL8367C_DSCP37_DSCP_MASK 0x3F00 #define RTL8367C_DSCP36_DSCP_OFFSET 0 #define RTL8367C_DSCP36_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL19 0x09F3 #define RTL8367C_DSCP39_DSCP_OFFSET 8 #define RTL8367C_DSCP39_DSCP_MASK 0x3F00 #define RTL8367C_DSCP38_DSCP_OFFSET 0 #define RTL8367C_DSCP38_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL20 0x09F4 #define RTL8367C_DSCP41_DSCP_OFFSET 8 #define RTL8367C_DSCP41_DSCP_MASK 0x3F00 #define RTL8367C_DSCP40_DSCP_OFFSET 0 #define RTL8367C_DSCP40_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL21 0x09F5 #define RTL8367C_DSCP43_DSCP_OFFSET 8 #define RTL8367C_DSCP43_DSCP_MASK 0x3F00 #define RTL8367C_DSCP42_DSCP_OFFSET 0 #define RTL8367C_DSCP42_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL22 0x09F6 #define RTL8367C_DSCP45_DSCP_OFFSET 8 #define RTL8367C_DSCP45_DSCP_MASK 0x3F00 #define RTL8367C_DSCP44_DSCP_OFFSET 0 #define RTL8367C_DSCP44_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL23 0x09F7 #define RTL8367C_DSCP47_DSCP_OFFSET 8 #define RTL8367C_DSCP47_DSCP_MASK 0x3F00 #define RTL8367C_DSCP46_DSCP_OFFSET 0 #define RTL8367C_DSCP46_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL24 0x09F8 #define RTL8367C_DSCP49_DSCP_OFFSET 8 #define RTL8367C_DSCP49_DSCP_MASK 0x3F00 #define RTL8367C_DSCP48_DSCP_OFFSET 0 #define RTL8367C_DSCP48_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL25 0x09F9 #define RTL8367C_DSCP51_DSCP_OFFSET 8 #define RTL8367C_DSCP51_DSCP_MASK 0x3F00 #define RTL8367C_DSCP50_DSCP_OFFSET 0 #define RTL8367C_DSCP50_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL26 0x09FA #define RTL8367C_DSCP53_DSCP_OFFSET 8 #define RTL8367C_DSCP53_DSCP_MASK 0x3F00 #define RTL8367C_DSCP52_DSCP_OFFSET 0 #define RTL8367C_DSCP52_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL27 0x09FB #define RTL8367C_DSCP55_DSCP_OFFSET 8 #define RTL8367C_DSCP55_DSCP_MASK 0x3F00 #define RTL8367C_DSCP54_DSCP_OFFSET 0 #define RTL8367C_DSCP54_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL28 0x09FC #define RTL8367C_DSCP57_DSCP_OFFSET 8 #define RTL8367C_DSCP57_DSCP_MASK 0x3F00 #define RTL8367C_DSCP56_DSCP_OFFSET 0 #define RTL8367C_DSCP56_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL29 0x09FD #define RTL8367C_DSCP59_DSCP_OFFSET 8 #define RTL8367C_DSCP59_DSCP_MASK 0x3F00 #define RTL8367C_DSCP58_DSCP_OFFSET 0 #define RTL8367C_DSCP58_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL30 0x09FE #define RTL8367C_DSCP61_DSCP_OFFSET 8 #define RTL8367C_DSCP61_DSCP_MASK 0x3F00 #define RTL8367C_DSCP60_DSCP_OFFSET 0 #define RTL8367C_DSCP60_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL31 0x09FF #define RTL8367C_DSCP63_DSCP_OFFSET 8 #define RTL8367C_DSCP63_DSCP_MASK 0x3F00 #define RTL8367C_DSCP62_DSCP_OFFSET 0 #define RTL8367C_DSCP62_DSCP_MASK 0x3F /* (16'h0a00)l2_reg */ #define RTL8367C_REG_VLAN_MSTI0_CTRL0 0x0a00 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI0_CTRL1 0x0a01 #define RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI1_CTRL0 0x0a02 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI1_CTRL1 0x0a03 #define RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI2_CTRL0 0x0a04 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI2_CTRL1 0x0a05 #define RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI3_CTRL0 0x0a06 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI3_CTRL1 0x0a07 #define RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI4_CTRL0 0x0a08 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI4_CTRL1 0x0a09 #define RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI5_CTRL0 0x0a0a #define RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI5_CTRL1 0x0a0b #define RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI6_CTRL0 0x0a0c #define RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI6_CTRL1 0x0a0d #define RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI7_CTRL0 0x0a0e #define RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI7_CTRL1 0x0a0f #define RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI8_CTRL0 0x0a10 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI8_CTRL1 0x0a11 #define RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI9_CTRL0 0x0a12 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI9_CTRL1 0x0a13 #define RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI10_CTRL0 0x0a14 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI10_CTRL1 0x0a15 #define RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI11_CTRL0 0x0a16 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI11_CTRL1 0x0a17 #define RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI12_CTRL0 0x0a18 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI12_CTRL1 0x0a19 #define RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI13_CTRL0 0x0a1a #define RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI13_CTRL1 0x0a1b #define RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI14_CTRL0 0x0a1c #define RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI14_CTRL1 0x0a1d #define RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI15_CTRL0 0x0a1e #define RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_OFFSET 14 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_MASK 0xC000 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_OFFSET 12 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_MASK 0x3000 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_OFFSET 10 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_MASK 0xC00 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_OFFSET 8 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_MASK 0x300 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_OFFSET 6 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_MASK 0xC0 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_MASK 0x3 #define RTL8367C_REG_VLAN_MSTI15_CTRL1 0x0a1f #define RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_OFFSET 4 #define RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_MASK 0x30 #define RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_OFFSET 2 #define RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_MASK 0xC #define RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_OFFSET 0 #define RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_MASK 0x3 #define RTL8367C_REG_LUT_PORT0_LEARN_LIMITNO 0x0a20 #define RTL8367C_LUT_PORT0_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT0_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT1_LEARN_LIMITNO 0x0a21 #define RTL8367C_LUT_PORT1_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT1_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT2_LEARN_LIMITNO 0x0a22 #define RTL8367C_LUT_PORT2_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT2_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT3_LEARN_LIMITNO 0x0a23 #define RTL8367C_LUT_PORT3_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT3_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT4_LEARN_LIMITNO 0x0a24 #define RTL8367C_LUT_PORT4_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT4_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT5_LEARN_LIMITNO 0x0a25 #define RTL8367C_LUT_PORT5_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT5_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT6_LEARN_LIMITNO 0x0a26 #define RTL8367C_LUT_PORT6_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT6_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT7_LEARN_LIMITNO 0x0a27 #define RTL8367C_LUT_PORT7_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT7_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_SYS_LEARN_LIMITNO 0x0a28 #define RTL8367C_LUT_SYS_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_SYS_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL 0x0a29 #define RTL8367C_LUT_SYSTEM_LEARN_PMASK1_OFFSET 12 #define RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK 0x7000 #define RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_OFFSET 10 #define RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK 0xC00 #define RTL8367C_LUT_SYSTEM_LEARN_PMASK_OFFSET 0 #define RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK 0xFF #define RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO 0x0a2a #define RTL8367C_LUT_PORT8_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT8_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT9_LEARN_LIMITNO 0x0a2b #define RTL8367C_LUT_PORT9_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT9_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_PORT10_LEARN_LIMITNO 0x0a2c #define RTL8367C_LUT_PORT10_LEARN_LIMITNO_OFFSET 0 #define RTL8367C_LUT_PORT10_LEARN_LIMITNO_MASK 0x1FFF #define RTL8367C_REG_LUT_CFG 0x0a30 #define RTL8367C_AGE_SPEED_OFFSET 8 #define RTL8367C_AGE_SPEED_MASK 0x300 #define RTL8367C_BCAM_DISABLE_OFFSET 6 #define RTL8367C_BCAM_DISABLE_MASK 0x40 #define RTL8367C_LINKDOWN_AGEOUT_OFFSET 5 #define RTL8367C_LINKDOWN_AGEOUT_MASK 0x20 #define RTL8367C_LUT_IPMC_HASH_OFFSET 4 #define RTL8367C_LUT_IPMC_HASH_MASK 0x10 #define RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET 3 #define RTL8367C_LUT_IPMC_LOOKUP_OP_MASK 0x8 #define RTL8367C_AGE_TIMER_OFFSET 0 #define RTL8367C_AGE_TIMER_MASK 0x7 #define RTL8367C_REG_LUT_AGEOUT_CTRL 0x0a31 #define RTL8367C_LUT_AGEOUT_CTRL_OFFSET 0 #define RTL8367C_LUT_AGEOUT_CTRL_MASK 0x7FF #define RTL8367C_REG_PORT_EFID_CTRL0 0x0a32 #define RTL8367C_PORT3_EFID_OFFSET 12 #define RTL8367C_PORT3_EFID_MASK 0x7000 #define RTL8367C_PORT2_EFID_OFFSET 8 #define RTL8367C_PORT2_EFID_MASK 0x700 #define RTL8367C_PORT1_EFID_OFFSET 4 #define RTL8367C_PORT1_EFID_MASK 0x70 #define RTL8367C_PORT0_EFID_OFFSET 0 #define RTL8367C_PORT0_EFID_MASK 0x7 #define RTL8367C_REG_PORT_EFID_CTRL1 0x0a33 #define RTL8367C_PORT7_EFID_OFFSET 12 #define RTL8367C_PORT7_EFID_MASK 0x7000 #define RTL8367C_PORT6_EFID_OFFSET 8 #define RTL8367C_PORT6_EFID_MASK 0x700 #define RTL8367C_PORT5_EFID_OFFSET 4 #define RTL8367C_PORT5_EFID_MASK 0x70 #define RTL8367C_PORT4_EFID_OFFSET 0 #define RTL8367C_PORT4_EFID_MASK 0x7 #define RTL8367C_REG_PORT_EFID_CTRL2 0x0a34 #define RTL8367C_PORT10_EFID_OFFSET 8 #define RTL8367C_PORT10_EFID_MASK 0x700 #define RTL8367C_PORT9_EFID_OFFSET 4 #define RTL8367C_PORT9_EFID_MASK 0x70 #define RTL8367C_PORT8_EFID_OFFSET 0 #define RTL8367C_PORT8_EFID_MASK 0x7 #define RTL8367C_REG_FORCE_FLUSH1 0x0a35 #define RTL8367C_BUSY_STATUS1_OFFSET 3 #define RTL8367C_BUSY_STATUS1_MASK 0x38 #define RTL8367C_PORTMASK1_OFFSET 0 #define RTL8367C_PORTMASK1_MASK 0x7 #define RTL8367C_REG_FORCE_FLUSH 0x0a36 #define RTL8367C_BUSY_STATUS_OFFSET 8 #define RTL8367C_BUSY_STATUS_MASK 0xFF00 #define RTL8367C_FORCE_FLUSH_PORTMASK_OFFSET 0 #define RTL8367C_FORCE_FLUSH_PORTMASK_MASK 0xFF #define RTL8367C_REG_L2_FLUSH_CTRL1 0x0a37 #define RTL8367C_LUT_FLUSH_FID_OFFSET 12 #define RTL8367C_LUT_FLUSH_FID_MASK 0xF000 #define RTL8367C_LUT_FLUSH_VID_OFFSET 0 #define RTL8367C_LUT_FLUSH_VID_MASK 0xFFF #define RTL8367C_REG_L2_FLUSH_CTRL2 0x0a38 #define RTL8367C_LUT_FLUSH_TYPE_OFFSET 2 #define RTL8367C_LUT_FLUSH_TYPE_MASK 0x4 #define RTL8367C_LUT_FLUSH_MODE_OFFSET 0 #define RTL8367C_LUT_FLUSH_MODE_MASK 0x3 #define RTL8367C_REG_L2_FLUSH_CTRL3 0x0a39 #define RTL8367C_L2_FLUSH_CTRL3_OFFSET 0 #define RTL8367C_L2_FLUSH_CTRL3_MASK 0x1 #define RTL8367C_REG_LUT_CFG2 0x0a3a #define RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET 1 #define RTL8367C_LUT_IPMC_FWD_RPORT_MASK 0x2 #define RTL8367C_LUT_IPMC_VID_HASH_OFFSET 0 #define RTL8367C_LUT_IPMC_VID_HASH_MASK 0x1 #define RTL8367C_REG_FLUSH_STATUS 0x0a3f #define RTL8367C_FLUSH_STATUS_OFFSET 0 #define RTL8367C_FLUSH_STATUS_MASK 0x1 #define RTL8367C_REG_STORM_BCAST 0x0a40 #define RTL8367C_STORM_BCAST_OFFSET 0 #define RTL8367C_STORM_BCAST_MASK 0x7FF #define RTL8367C_REG_STORM_MCAST 0x0a41 #define RTL8367C_STORM_MCAST_OFFSET 0 #define RTL8367C_STORM_MCAST_MASK 0x7FF #define RTL8367C_REG_STORM_UNKOWN_UCAST 0x0a42 #define RTL8367C_STORM_UNKOWN_UCAST_OFFSET 0 #define RTL8367C_STORM_UNKOWN_UCAST_MASK 0x7FF #define RTL8367C_REG_STORM_UNKOWN_MCAST 0x0a43 #define RTL8367C_STORM_UNKOWN_MCAST_OFFSET 0 #define RTL8367C_STORM_UNKOWN_MCAST_MASK 0x7FF #define RTL8367C_REG_STORM_BCAST_METER_CTRL0 0x0a44 #define RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 #define RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_BCAST_METER_CTRL1 0x0a45 #define RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 #define RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_BCAST_METER_CTRL2 0x0a46 #define RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 #define RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_BCAST_METER_CTRL3 0x0a47 #define RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 #define RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_BCAST_METER_CTRL4 0x0a48 #define RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_OFFSET 8 #define RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_BCAST_METER_CTRL5 0x0a49 #define RTL8367C_STORM_BCAST_METER_CTRL5_OFFSET 0 #define RTL8367C_STORM_BCAST_METER_CTRL5_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL0 0x0a4c #define RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 #define RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL1 0x0a4d #define RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 #define RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL2 0x0a4e #define RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 #define RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL3 0x0a4f #define RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 #define RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL4 0x0a50 #define RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_OFFSET 8 #define RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_MCAST_METER_CTRL5 0x0a51 #define RTL8367C_STORM_MCAST_METER_CTRL5_OFFSET 0 #define RTL8367C_STORM_MCAST_METER_CTRL5_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL0 0x0a54 #define RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL1 0x0a55 #define RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL2 0x0a56 #define RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL3 0x0a57 #define RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL4 0x0a58 #define RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNDA_METER_CTRL5 0x0a59 #define RTL8367C_STORM_UNDA_METER_CTRL5_OFFSET 0 #define RTL8367C_STORM_UNDA_METER_CTRL5_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL0 0x0a5c #define RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL1 0x0a5d #define RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL2 0x0a5e #define RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL3 0x0a5f #define RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_EXT_CFG 0x0a60 #define RTL8367C_STORM_EXT_EN_PORTMASK_EXT_OFFSET 14 #define RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK 0x4000 #define RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET 13 #define RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_MASK 0x2000 #define RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET 12 #define RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_MASK 0x1000 #define RTL8367C_STORM_MCAST_EXT_EN_OFFSET 11 #define RTL8367C_STORM_MCAST_EXT_EN_MASK 0x800 #define RTL8367C_STORM_BCAST_EXT_EN_OFFSET 10 #define RTL8367C_STORM_BCAST_EXT_EN_MASK 0x400 #define RTL8367C_STORM_EXT_EN_PORTMASK_OFFSET 0 #define RTL8367C_STORM_EXT_EN_PORTMASK_MASK 0x3FF #define RTL8367C_REG_STORM_EXT_MTRIDX_CFG0 0x0a61 #define RTL8367C_MC_STORM_EXT_METERIDX_OFFSET 8 #define RTL8367C_MC_STORM_EXT_METERIDX_MASK 0x3F00 #define RTL8367C_BC_STORM_EXT_METERIDX_OFFSET 0 #define RTL8367C_BC_STORM_EXT_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_EXT_MTRIDX_CFG1 0x0a62 #define RTL8367C_UNMC_STORM_EXT_METERIDX_OFFSET 8 #define RTL8367C_UNMC_STORM_EXT_METERIDX_MASK 0x3F00 #define RTL8367C_UNUC_STORM_EXT_METERIDX_OFFSET 0 #define RTL8367C_UNUC_STORM_EXT_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL4 0x0a63 #define RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_OFFSET 8 #define RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 #define RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_MASK 0x3F #define RTL8367C_REG_STORM_UNMC_METER_CTRL5 0x0a64 #define RTL8367C_STORM_UNMC_METER_CTRL5_OFFSET 0 #define RTL8367C_STORM_UNMC_METER_CTRL5_MASK 0x3F #define RTL8367C_REG_OAM_PARSER_CTRL0 0x0a70 #define RTL8367C_PORT7_PARACT_OFFSET 14 #define RTL8367C_PORT7_PARACT_MASK 0xC000 #define RTL8367C_PORT6_PARACT_OFFSET 12 #define RTL8367C_PORT6_PARACT_MASK 0x3000 #define RTL8367C_PORT5_PARACT_OFFSET 10 #define RTL8367C_PORT5_PARACT_MASK 0xC00 #define RTL8367C_PORT4_PARACT_OFFSET 8 #define RTL8367C_PORT4_PARACT_MASK 0x300 #define RTL8367C_PORT3_PARACT_OFFSET 6 #define RTL8367C_PORT3_PARACT_MASK 0xC0 #define RTL8367C_PORT2_PARACT_OFFSET 4 #define RTL8367C_PORT2_PARACT_MASK 0x30 #define RTL8367C_PORT1_PARACT_OFFSET 2 #define RTL8367C_PORT1_PARACT_MASK 0xC #define RTL8367C_PORT0_PARACT_OFFSET 0 #define RTL8367C_PORT0_PARACT_MASK 0x3 #define RTL8367C_REG_OAM_PARSER_CTRL1 0x0a71 #define RTL8367C_PORT10_PARACT_OFFSET 4 #define RTL8367C_PORT10_PARACT_MASK 0x30 #define RTL8367C_PORT9_PARACT_OFFSET 2 #define RTL8367C_PORT9_PARACT_MASK 0xC #define RTL8367C_PORT8_PARACT_OFFSET 0 #define RTL8367C_PORT8_PARACT_MASK 0x3 #define RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 0x0a72 #define RTL8367C_PORT7_MULACT_OFFSET 14 #define RTL8367C_PORT7_MULACT_MASK 0xC000 #define RTL8367C_PORT6_MULACT_OFFSET 12 #define RTL8367C_PORT6_MULACT_MASK 0x3000 #define RTL8367C_PORT5_MULACT_OFFSET 10 #define RTL8367C_PORT5_MULACT_MASK 0xC00 #define RTL8367C_PORT4_MULACT_OFFSET 8 #define RTL8367C_PORT4_MULACT_MASK 0x300 #define RTL8367C_PORT3_MULACT_OFFSET 6 #define RTL8367C_PORT3_MULACT_MASK 0xC0 #define RTL8367C_PORT2_MULACT_OFFSET 4 #define RTL8367C_PORT2_MULACT_MASK 0x30 #define RTL8367C_PORT1_MULACT_OFFSET 2 #define RTL8367C_PORT1_MULACT_MASK 0xC #define RTL8367C_PORT0_MULACT_OFFSET 0 #define RTL8367C_PORT0_MULACT_MASK 0x3 #define RTL8367C_REG_OAM_MULTIPLEXER_CTRL1 0x0a73 #define RTL8367C_PORT10_MULACT_OFFSET 4 #define RTL8367C_PORT10_MULACT_MASK 0x30 #define RTL8367C_PORT9_MULACT_OFFSET 2 #define RTL8367C_PORT9_MULACT_MASK 0xC #define RTL8367C_PORT8_MULACT_OFFSET 0 #define RTL8367C_PORT8_MULACT_MASK 0x3 #define RTL8367C_REG_OAM_CTRL 0x0a74 #define RTL8367C_OAM_CTRL_OFFSET 0 #define RTL8367C_OAM_CTRL_MASK 0x1 #define RTL8367C_REG_DOT1X_PORT_ENABLE 0x0a80 #define RTL8367C_DOT1X_PORT_ENABLE_OFFSET 0 #define RTL8367C_DOT1X_PORT_ENABLE_MASK 0x7FF #define RTL8367C_REG_DOT1X_MAC_ENABLE 0x0a81 #define RTL8367C_DOT1X_MAC_ENABLE_OFFSET 0 #define RTL8367C_DOT1X_MAC_ENABLE_MASK 0x7FF #define RTL8367C_REG_DOT1X_PORT_AUTH 0x0a82 #define RTL8367C_DOT1X_PORT_AUTH_OFFSET 0 #define RTL8367C_DOT1X_PORT_AUTH_MASK 0x7FF #define RTL8367C_REG_DOT1X_PORT_OPDIR 0x0a83 #define RTL8367C_DOT1X_PORT_OPDIR_OFFSET 0 #define RTL8367C_DOT1X_PORT_OPDIR_MASK 0x7FF #define RTL8367C_REG_DOT1X_UNAUTH_ACT_W0 0x0a84 #define RTL8367C_DOT1X_PORT7_UNAUTHBH_OFFSET 14 #define RTL8367C_DOT1X_PORT7_UNAUTHBH_MASK 0xC000 #define RTL8367C_DOT1X_PORT6_UNAUTHBH_OFFSET 12 #define RTL8367C_DOT1X_PORT6_UNAUTHBH_MASK 0x3000 #define RTL8367C_DOT1X_PORT5_UNAUTHBH_OFFSET 10 #define RTL8367C_DOT1X_PORT5_UNAUTHBH_MASK 0xC00 #define RTL8367C_DOT1X_PORT4_UNAUTHBH_OFFSET 8 #define RTL8367C_DOT1X_PORT4_UNAUTHBH_MASK 0x300 #define RTL8367C_DOT1X_PORT3_UNAUTHBH_OFFSET 6 #define RTL8367C_DOT1X_PORT3_UNAUTHBH_MASK 0xC0 #define RTL8367C_DOT1X_PORT2_UNAUTHBH_OFFSET 4 #define RTL8367C_DOT1X_PORT2_UNAUTHBH_MASK 0x30 #define RTL8367C_DOT1X_PORT1_UNAUTHBH_OFFSET 2 #define RTL8367C_DOT1X_PORT1_UNAUTHBH_MASK 0xC #define RTL8367C_DOT1X_PORT0_UNAUTHBH_OFFSET 0 #define RTL8367C_DOT1X_PORT0_UNAUTHBH_MASK 0x3 #define RTL8367C_REG_DOT1X_UNAUTH_ACT_W1 0x0a85 #define RTL8367C_DOT1X_PORT10_UNAUTHBH_OFFSET 4 #define RTL8367C_DOT1X_PORT10_UNAUTHBH_MASK 0x30 #define RTL8367C_DOT1X_PORT9_UNAUTHBH_OFFSET 2 #define RTL8367C_DOT1X_PORT9_UNAUTHBH_MASK 0xC #define RTL8367C_DOT1X_PORT8_UNAUTHBH_OFFSET 0 #define RTL8367C_DOT1X_PORT8_UNAUTHBH_MASK 0x3 #define RTL8367C_REG_DOT1X_CFG 0x0a86 #define RTL8367C_DOT1X_GVOPDIR_OFFSET 6 #define RTL8367C_DOT1X_GVOPDIR_MASK 0x40 #define RTL8367C_DOT1X_MAC_OPDIR_OFFSET 5 #define RTL8367C_DOT1X_MAC_OPDIR_MASK 0x20 #define RTL8367C_DOT1X_GVIDX_OFFSET 0 #define RTL8367C_DOT1X_GVIDX_MASK 0x1F #define RTL8367C_REG_L2_LRN_CNT_CTRL0 0x0a87 #define RTL8367C_L2_LRN_CNT_CTRL0_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL0_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL1 0x0a88 #define RTL8367C_L2_LRN_CNT_CTRL1_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL1_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL2 0x0a89 #define RTL8367C_L2_LRN_CNT_CTRL2_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL2_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL3 0x0a8a #define RTL8367C_L2_LRN_CNT_CTRL3_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL3_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL4 0x0a8b #define RTL8367C_L2_LRN_CNT_CTRL4_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL4_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL5 0x0a8c #define RTL8367C_L2_LRN_CNT_CTRL5_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL5_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL6 0x0a8d #define RTL8367C_L2_LRN_CNT_CTRL6_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL6_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL7 0x0a8e #define RTL8367C_L2_LRN_CNT_CTRL7_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL7_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL8 0x0a8f #define RTL8367C_L2_LRN_CNT_CTRL8_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL8_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL9 0x0a90 #define RTL8367C_L2_LRN_CNT_CTRL9_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL9_MASK 0x1FFF #define RTL8367C_REG_L2_LRN_CNT_CTRL10 0x0a92 #define RTL8367C_L2_LRN_CNT_CTRL10_OFFSET 0 #define RTL8367C_L2_LRN_CNT_CTRL10_MASK 0x1FFF #define RTL8367C_REG_LUT_LRN_UNDER_STATUS 0x0a91 #define RTL8367C_LUT_LRN_UNDER_STATUS_OFFSET 0 #define RTL8367C_LUT_LRN_UNDER_STATUS_MASK 0x7FF #define RTL8367C_REG_L2_SA_MOVING_FORBID 0x0aa0 #define RTL8367C_L2_SA_MOVING_FORBID_OFFSET 0 #define RTL8367C_L2_SA_MOVING_FORBID_MASK 0x7FF #define RTL8367C_REG_DRPORT_LEARN_CTRL 0x0aa1 #define RTL8367C_FORBID1_OFFSET 1 #define RTL8367C_FORBID1_MASK 0x2 #define RTL8367C_FORBID0_OFFSET 0 #define RTL8367C_FORBID0_MASK 0x1 #define RTL8367C_REG_L2_DUMMY02 0x0aa2 #define RTL8367C_REG_L2_DUMMY03 0x0aa3 #define RTL8367C_REG_L2_DUMMY04 0x0aa4 #define RTL8367C_REG_L2_DUMMY05 0x0aa5 #define RTL8367C_REG_L2_DUMMY06 0x0aa6 #define RTL8367C_REG_L2_DUMMY07 0x0aa7 #define RTL8367C_REG_IPMC_GROUP_PMSK_00 0x0AC0 #define RTL8367C_IPMC_GROUP_PMSK_00_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_00_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_01 0x0AC1 #define RTL8367C_IPMC_GROUP_PMSK_01_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_01_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_02 0x0AC2 #define RTL8367C_IPMC_GROUP_PMSK_02_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_02_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_03 0x0AC3 #define RTL8367C_IPMC_GROUP_PMSK_03_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_03_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_04 0x0AC4 #define RTL8367C_IPMC_GROUP_PMSK_04_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_04_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_05 0x0AC5 #define RTL8367C_IPMC_GROUP_PMSK_05_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_05_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_06 0x0AC6 #define RTL8367C_IPMC_GROUP_PMSK_06_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_06_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_07 0x0AC7 #define RTL8367C_IPMC_GROUP_PMSK_07_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_07_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_08 0x0AC8 #define RTL8367C_IPMC_GROUP_PMSK_08_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_08_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_09 0x0AC9 #define RTL8367C_IPMC_GROUP_PMSK_09_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_09_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_10 0x0ACA #define RTL8367C_IPMC_GROUP_PMSK_10_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_10_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_11 0x0ACB #define RTL8367C_IPMC_GROUP_PMSK_11_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_11_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_12 0x0ACC #define RTL8367C_IPMC_GROUP_PMSK_12_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_12_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_13 0x0ACD #define RTL8367C_IPMC_GROUP_PMSK_13_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_13_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_14 0x0ACE #define RTL8367C_IPMC_GROUP_PMSK_14_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_14_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_15 0x0ACF #define RTL8367C_IPMC_GROUP_PMSK_15_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_15_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_16 0x0AD0 #define RTL8367C_IPMC_GROUP_PMSK_16_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_16_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_17 0x0AD1 #define RTL8367C_IPMC_GROUP_PMSK_17_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_17_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_18 0x0AD2 #define RTL8367C_IPMC_GROUP_PMSK_18_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_18_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_19 0x0AD3 #define RTL8367C_IPMC_GROUP_PMSK_19_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_19_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_20 0x0AD4 #define RTL8367C_IPMC_GROUP_PMSK_20_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_20_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_21 0x0AD5 #define RTL8367C_IPMC_GROUP_PMSK_21_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_21_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_22 0x0AD6 #define RTL8367C_IPMC_GROUP_PMSK_22_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_22_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_23 0x0AD7 #define RTL8367C_IPMC_GROUP_PMSK_23_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_23_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_24 0x0AD8 #define RTL8367C_IPMC_GROUP_PMSK_24_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_24_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_25 0x0AD9 #define RTL8367C_IPMC_GROUP_PMSK_25_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_25_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_26 0x0ADA #define RTL8367C_IPMC_GROUP_PMSK_26_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_26_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_27 0x0ADB #define RTL8367C_IPMC_GROUP_PMSK_27_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_27_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_28 0x0ADC #define RTL8367C_IPMC_GROUP_PMSK_28_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_28_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_29 0x0ADD #define RTL8367C_IPMC_GROUP_PMSK_29_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_29_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_30 0x0ADE #define RTL8367C_IPMC_GROUP_PMSK_30_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_30_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_31 0x0ADF #define RTL8367C_IPMC_GROUP_PMSK_31_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_31_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_32 0x0AE0 #define RTL8367C_IPMC_GROUP_PMSK_32_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_32_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_33 0x0AE1 #define RTL8367C_IPMC_GROUP_PMSK_33_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_33_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_34 0x0AE2 #define RTL8367C_IPMC_GROUP_PMSK_34_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_34_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_35 0x0AE3 #define RTL8367C_IPMC_GROUP_PMSK_35_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_35_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_36 0x0AE4 #define RTL8367C_IPMC_GROUP_PMSK_36_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_36_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_37 0x0AE5 #define RTL8367C_IPMC_GROUP_PMSK_37_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_37_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_38 0x0AE6 #define RTL8367C_IPMC_GROUP_PMSK_38_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_38_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_39 0x0AE7 #define RTL8367C_IPMC_GROUP_PMSK_39_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_39_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_40 0x0AE8 #define RTL8367C_IPMC_GROUP_PMSK_40_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_40_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_41 0x0AE9 #define RTL8367C_IPMC_GROUP_PMSK_41_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_41_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_42 0x0AEA #define RTL8367C_IPMC_GROUP_PMSK_42_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_42_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_43 0x0AEB #define RTL8367C_IPMC_GROUP_PMSK_43_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_43_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_44 0x0AEC #define RTL8367C_IPMC_GROUP_PMSK_44_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_44_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_45 0x0AED #define RTL8367C_IPMC_GROUP_PMSK_45_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_45_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_46 0x0AEE #define RTL8367C_IPMC_GROUP_PMSK_46_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_46_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_47 0x0AEF #define RTL8367C_IPMC_GROUP_PMSK_47_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_47_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_48 0x0AF0 #define RTL8367C_IPMC_GROUP_PMSK_48_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_48_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_49 0x0AF1 #define RTL8367C_IPMC_GROUP_PMSK_49_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_49_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_50 0x0AF2 #define RTL8367C_IPMC_GROUP_PMSK_50_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_50_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_51 0x0AF3 #define RTL8367C_IPMC_GROUP_PMSK_51_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_51_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_52 0x0AF4 #define RTL8367C_IPMC_GROUP_PMSK_52_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_52_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_53 0x0AF5 #define RTL8367C_IPMC_GROUP_PMSK_53_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_53_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_54 0x0AF6 #define RTL8367C_IPMC_GROUP_PMSK_54_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_54_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_55 0x0AF7 #define RTL8367C_IPMC_GROUP_PMSK_55_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_55_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_56 0x0AF8 #define RTL8367C_IPMC_GROUP_PMSK_56_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_56_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_57 0x0AF9 #define RTL8367C_IPMC_GROUP_PMSK_57_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_57_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_58 0x0AFA #define RTL8367C_IPMC_GROUP_PMSK_58_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_58_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_59 0x0AFB #define RTL8367C_IPMC_GROUP_PMSK_59_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_59_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_60 0x0AFC #define RTL8367C_IPMC_GROUP_PMSK_60_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_60_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_61 0x0AFD #define RTL8367C_IPMC_GROUP_PMSK_61_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_61_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_62 0x0AFE #define RTL8367C_IPMC_GROUP_PMSK_62_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_62_MASK 0x7FF #define RTL8367C_REG_IPMC_GROUP_PMSK_63 0x0AFF #define RTL8367C_IPMC_GROUP_PMSK_63_OFFSET 0 #define RTL8367C_IPMC_GROUP_PMSK_63_MASK 0x7FF /* (16'h0b00)mltvlan_reg */ #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL0 0x0b00 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL1 0x0b01 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL2 0x0b02 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL3 0x0b03 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL4 0x0b04 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL0 0x0b05 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL1 0x0b06 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL2 0x0b07 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL3 0x0b08 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL4 0x0b09 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL0 0x0b0a #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL1 0x0b0b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL2 0x0b0c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL3 0x0b0d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL4 0x0b0e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL0 0x0b0f #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL1 0x0b10 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL2 0x0b11 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL3 0x0b12 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL4 0x0b13 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL0 0x0b14 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL1 0x0b15 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL2 0x0b16 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL3 0x0b17 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL4 0x0b18 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL0 0x0b19 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL1 0x0b1a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL2 0x0b1b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL3 0x0b1c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL4 0x0b1d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL0 0x0b1e #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL1 0x0b1f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL2 0x0b20 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL3 0x0b21 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL4 0x0b22 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL0 0x0b23 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL1 0x0b24 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL2 0x0b25 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL3 0x0b26 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL4 0x0b27 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL0 0x0b28 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL1 0x0b29 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL2 0x0b2a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL3 0x0b2b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL4 0x0b2c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL0 0x0b2d #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL1 0x0b2e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL2 0x0b2f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL3 0x0b30 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL4 0x0b31 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL0 0x0b32 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL1 0x0b33 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL2 0x0b34 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL3 0x0b35 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL4 0x0b36 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL0 0x0b37 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL1 0x0b38 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL2 0x0b39 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL3 0x0b3a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL4 0x0b3b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL0 0x0b3c #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL1 0x0b3d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL2 0x0b3e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL3 0x0b3f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL4 0x0b40 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL0 0x0b41 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL1 0x0b42 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL2 0x0b43 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL3 0x0b44 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL4 0x0b45 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL0 0x0b46 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL1 0x0b47 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL2 0x0b48 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL3 0x0b49 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL4 0x0b4a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL0 0x0b4b #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL1 0x0b4c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL2 0x0b4d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL3 0x0b4e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL4 0x0b4f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL0 0x0b50 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL1 0x0b51 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL2 0x0b52 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL3 0x0b53 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL4 0x0b54 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL0 0x0b55 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL1 0x0b56 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL2 0x0b57 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL3 0x0b58 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL4 0x0b59 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL0 0x0b5a #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL1 0x0b5b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL2 0x0b5c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL3 0x0b5d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL4 0x0b5e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL0 0x0b5f #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL1 0x0b60 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL2 0x0b61 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL3 0x0b62 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL4 0x0b63 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL0 0x0b64 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL1 0x0b65 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL2 0x0b66 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL3 0x0b67 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL4 0x0b68 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL0 0x0b69 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL1 0x0b6a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL2 0x0b6b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL3 0x0b6c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL4 0x0b6d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL0 0x0b6e #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL1 0x0b6f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL2 0x0b70 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL3 0x0b71 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL4 0x0b72 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL0 0x0b73 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL1 0x0b74 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL2 0x0b75 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL3 0x0b76 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL4 0x0b77 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL0 0x0b78 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL1 0x0b79 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL2 0x0b7a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL3 0x0b7b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL4 0x0b7c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL0 0x0b7d #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL1 0x0b7e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL2 0x0b7f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL3 0x0b80 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL4 0x0b81 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL0 0x0b82 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL1 0x0b83 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL2 0x0b84 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL3 0x0b85 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL4 0x0b86 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL0 0x0b87 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL1 0x0b88 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL2 0x0b89 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL3 0x0b8a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL4 0x0b8b #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL0 0x0b8c #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL1 0x0b8d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL2 0x0b8e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL3 0x0b8f #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL4 0x0b90 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL0 0x0b91 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL1 0x0b92 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL2 0x0b93 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL3 0x0b94 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL4 0x0b95 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL0 0x0b96 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL1 0x0b97 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL2 0x0b98 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL3 0x0b99 #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL4 0x0b9a #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL0 0x0b9b #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_OFFSET 7 #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_MASK 0x80 #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_OFFSET 6 #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_MASK 0x40 #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_OFFSET 0 #define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL1 0x0b9c #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL2 0x0b9d #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL3 0x0b9e #define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL4 0x0b9f #define RTL8367C_REG_MLTVLAN_DUMMY_0 0x0ba0 #define RTL8367C_REG_MLTVLAN_DUMMY_1 0x0ba1 #define RTL8367C_REG_MLTVLAN_DUMMY_2 0x0ba2 #define RTL8367C_REG_MLTVLAN_DUMMY_3 0x0ba3 #define RTL8367C_REG_MLTVLAN_DUMMY_4 0x0ba4 #define RTL8367C_REG_MLTVLAN_DUMMY_5 0x0ba5 #define RTL8367C_REG_MLTVLAN_DUMMY_6 0x0ba6 #define RTL8367C_REG_MLTVLAN_DUMMY_7 0x0ba7 /* (16'h0c00)svlan_reg */ #define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL1 0x0c01 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL2 0x0c02 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL3 0x0c03 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL1 0x0c04 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL2 0x0c05 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL3 0x0c06 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL1 0x0c07 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL2 0x0c08 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL3 0x0c09 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL1 0x0c0a #define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL2 0x0c0b #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL3 0x0c0c #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL1 0x0c0d #define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL2 0x0c0e #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL3 0x0c0f #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL1 0x0c10 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL2 0x0c11 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL3 0x0c12 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL1 0x0c13 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL2 0x0c14 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL3 0x0c15 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL1 0x0c16 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL2 0x0c17 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL3 0x0c18 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL1 0x0c19 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL2 0x0c1a #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL3 0x0c1b #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL1 0x0c1c #define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL2 0x0c1d #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL3 0x0c1e #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL1 0x0c1f #define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL2 0x0c20 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL3 0x0c21 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL1 0x0c22 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL2 0x0c23 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL3 0x0c24 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL1 0x0c25 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL2 0x0c26 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL3 0x0c27 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL1 0x0c28 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL2 0x0c29 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL3 0x0c2a #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL1 0x0c2b #define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL2 0x0c2c #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL3 0x0c2d #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL1 0x0c2e #define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL2 0x0c2f #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL3 0x0c30 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL1 0x0c31 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL2 0x0c32 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL3 0x0c33 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL1 0x0c34 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL2 0x0c35 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL3 0x0c36 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL1 0x0c37 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL2 0x0c38 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL3 0x0c39 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL1 0x0c3a #define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL2 0x0c3b #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL3 0x0c3c #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL1 0x0c3d #define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL2 0x0c3e #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL3 0x0c3f #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL1 0x0c40 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL2 0x0c41 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL3 0x0c42 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL1 0x0c43 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL2 0x0c44 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL3 0x0c45 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL1 0x0c46 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL2 0x0c47 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL3 0x0c48 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL1 0x0c49 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL2 0x0c4a #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL3 0x0c4b #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL1 0x0c4c #define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL2 0x0c4d #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL3 0x0c4e #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL1 0x0c4f #define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL2 0x0c50 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL3 0x0c51 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL1 0x0c52 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL2 0x0c53 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL3 0x0c54 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL1 0x0c55 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL2 0x0c56 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL3 0x0c57 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL1 0x0c58 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL2 0x0c59 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL3 0x0c5a #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL1 0x0c5b #define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL2 0x0c5c #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL3 0x0c5d #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL1 0x0c5e #define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL2 0x0c5f #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL3 0x0c60 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL1 0x0c61 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL2 0x0c62 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL3 0x0c63 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL1 0x0c64 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL2 0x0c65 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL3 0x0c66 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL1 0x0c67 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL2 0x0c68 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL3 0x0c69 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL1 0x0c6a #define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL2 0x0c6b #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL3 0x0c6c #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL1 0x0c6d #define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL2 0x0c6e #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL3 0x0c6f #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL1 0x0c70 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL2 0x0c71 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL3 0x0c72 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL1 0x0c73 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL2 0x0c74 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL3 0x0c75 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL1 0x0c76 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL2 0x0c77 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL3 0x0c78 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL1 0x0c79 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL2 0x0c7a #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL3 0x0c7b #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL1 0x0c7c #define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL2 0x0c7d #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL3 0x0c7e #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL1 0x0c7f #define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL2 0x0c80 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL3 0x0c81 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL1 0x0c82 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL2 0x0c83 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL3 0x0c84 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL1 0x0c85 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL2 0x0c86 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL3 0x0c87 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL1 0x0c88 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL2 0x0c89 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL3 0x0c8a #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL1 0x0c8b #define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL2 0x0c8c #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL3 0x0c8d #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL1 0x0c8e #define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL2 0x0c8f #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL3 0x0c90 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL1 0x0c91 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL2 0x0c92 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL3 0x0c93 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL1 0x0c94 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL2 0x0c95 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL3 0x0c96 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL1 0x0c97 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL2 0x0c98 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL3 0x0c99 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL1 0x0c9a #define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL2 0x0c9b #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL3 0x0c9c #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL1 0x0c9d #define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL2 0x0c9e #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL3 0x0c9f #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL1 0x0ca0 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL2 0x0ca1 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL3 0x0ca2 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL1 0x0ca3 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL2 0x0ca4 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL3 0x0ca5 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL1 0x0ca6 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL2 0x0ca7 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL3 0x0ca8 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL1 0x0ca9 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL2 0x0caa #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL3 0x0cab #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL1 0x0cac #define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL2 0x0cad #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL3 0x0cae #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL1 0x0caf #define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL2 0x0cb0 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL3 0x0cb1 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL1 0x0cb2 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL2 0x0cb3 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL3 0x0cb4 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL1 0x0cb5 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL2 0x0cb6 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL3 0x0cb7 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL1 0x0cb8 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL2 0x0cb9 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL3 0x0cba #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL1 0x0cbb #define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL2 0x0cbc #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL3 0x0cbd #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL1 0x0cbe #define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_MASK 0xFF00 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_MASK 0xFF #define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL2 0x0cbf #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_OFFSET 7 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_MASK 0x80 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_OFFSET 4 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_MASK 0x70 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_MASK 0xF #define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL3 0x0cc0 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_OFFSET 13 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_MASK 0xE000 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_OFFSET 12 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_MASK 0x1000 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_MASK 0xFFF #define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4 0x0cc1 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL4 0x0cc2 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL4 0x0cc3 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL4 0x0cc4 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL4 0x0cc5 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL4 0x0cc6 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL4 0x0cc7 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL4 0x0cc8 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL4 0x0cc9 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL4 0x0cca #define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL4 0x0ccb #define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL4 0x0ccc #define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL4 0x0ccd #define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL4 0x0cce #define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL4 0x0ccf #define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL4 0x0cd0 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL4 0x0cd1 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL4 0x0cd2 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL4 0x0cd3 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL4 0x0cd4 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL4 0x0cd5 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL4 0x0cd6 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL4 0x0cd7 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL4 0x0cd8 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL4 0x0cd9 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL4 0x0cda #define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL4 0x0cdb #define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL4 0x0cdc #define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL4 0x0cdd #define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL4 0x0cde #define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL4 0x0cdf #define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL4 0x0ce0 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL4 0x0ce1 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL4 0x0ce2 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL4 0x0ce3 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL4 0x0ce4 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL4 0x0ce5 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL4 0x0ce6 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL4 0x0ce7 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL4 0x0ce8 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL4 0x0ce9 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL4 0x0cea #define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL4 0x0ceb #define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL4 0x0cec #define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL4 0x0ced #define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL4 0x0cee #define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL4 0x0cef #define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL4 0x0cf0 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL4 0x0cf1 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL4 0x0cf2 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL4 0x0cf3 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL4 0x0cf4 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL4 0x0cf5 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL4 0x0cf6 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL4 0x0cf7 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL4 0x0cf8 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL4 0x0cf9 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL4 0x0cfa #define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL4 0x0cfb #define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL4 0x0cfc #define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL4 0x0cfd #define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL4 0x0cfe #define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL4 0x0cff #define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_C2SCFG0_CTRL0 0x0d00 #define RTL8367C_SVLAN_C2SCFG0_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG0_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG0_CTRL1 0x0d01 #define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG0_CTRL2 0x0d02 #define RTL8367C_SVLAN_C2SCFG0_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG0_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG1_CTRL0 0x0d03 #define RTL8367C_SVLAN_C2SCFG1_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG1_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG1_CTRL1 0x0d04 #define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG1_CTRL2 0x0d05 #define RTL8367C_SVLAN_C2SCFG1_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG1_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG2_CTRL0 0x0d06 #define RTL8367C_SVLAN_C2SCFG2_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG2_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG2_CTRL1 0x0d07 #define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG2_CTRL2 0x0d08 #define RTL8367C_SVLAN_C2SCFG2_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG2_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG3_CTRL0 0x0d09 #define RTL8367C_SVLAN_C2SCFG3_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG3_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG3_CTRL1 0x0d0a #define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG3_CTRL2 0x0d0b #define RTL8367C_SVLAN_C2SCFG3_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG3_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG4_CTRL0 0x0d0c #define RTL8367C_SVLAN_C2SCFG4_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG4_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG4_CTRL1 0x0d0d #define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG4_CTRL2 0x0d0e #define RTL8367C_SVLAN_C2SCFG4_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG4_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG5_CTRL0 0x0d0f #define RTL8367C_SVLAN_C2SCFG5_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG5_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG5_CTRL1 0x0d10 #define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG5_CTRL2 0x0d11 #define RTL8367C_SVLAN_C2SCFG5_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG5_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG6_CTRL0 0x0d12 #define RTL8367C_SVLAN_C2SCFG6_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG6_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG6_CTRL1 0x0d13 #define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG6_CTRL2 0x0d14 #define RTL8367C_SVLAN_C2SCFG6_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG6_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG7_CTRL0 0x0d15 #define RTL8367C_SVLAN_C2SCFG7_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG7_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG7_CTRL1 0x0d16 #define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG7_CTRL2 0x0d17 #define RTL8367C_SVLAN_C2SCFG7_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG7_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG8_CTRL0 0x0d18 #define RTL8367C_SVLAN_C2SCFG8_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG8_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG8_CTRL1 0x0d19 #define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG8_CTRL2 0x0d1a #define RTL8367C_SVLAN_C2SCFG8_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG8_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG9_CTRL0 0x0d1b #define RTL8367C_SVLAN_C2SCFG9_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG9_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG9_CTRL1 0x0d1c #define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG9_CTRL2 0x0d1d #define RTL8367C_SVLAN_C2SCFG9_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG9_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG10_CTRL0 0x0d1e #define RTL8367C_SVLAN_C2SCFG10_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG10_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG10_CTRL1 0x0d1f #define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG10_CTRL2 0x0d20 #define RTL8367C_SVLAN_C2SCFG10_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG10_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG11_CTRL0 0x0d21 #define RTL8367C_SVLAN_C2SCFG11_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG11_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG11_CTRL1 0x0d22 #define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG11_CTRL2 0x0d23 #define RTL8367C_SVLAN_C2SCFG11_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG11_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG12_CTRL0 0x0d24 #define RTL8367C_SVLAN_C2SCFG12_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG12_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG12_CTRL1 0x0d25 #define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG12_CTRL2 0x0d26 #define RTL8367C_SVLAN_C2SCFG12_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG12_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG13_CTRL0 0x0d27 #define RTL8367C_SVLAN_C2SCFG13_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG13_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG13_CTRL1 0x0d28 #define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG13_CTRL2 0x0d29 #define RTL8367C_SVLAN_C2SCFG13_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG13_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG14_CTRL0 0x0d2a #define RTL8367C_SVLAN_C2SCFG14_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG14_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG14_CTRL1 0x0d2b #define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG14_CTRL2 0x0d2c #define RTL8367C_SVLAN_C2SCFG14_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG14_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG15_CTRL0 0x0d2d #define RTL8367C_SVLAN_C2SCFG15_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG15_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG15_CTRL1 0x0d2e #define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG15_CTRL2 0x0d2f #define RTL8367C_SVLAN_C2SCFG15_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG15_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG16_CTRL0 0x0d30 #define RTL8367C_SVLAN_C2SCFG16_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG16_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG16_CTRL1 0x0d31 #define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG16_CTRL2 0x0d32 #define RTL8367C_SVLAN_C2SCFG16_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG16_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG17_CTRL0 0x0d33 #define RTL8367C_SVLAN_C2SCFG17_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG17_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG17_CTRL1 0x0d34 #define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG17_CTRL2 0x0d35 #define RTL8367C_SVLAN_C2SCFG17_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG17_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG18_CTRL0 0x0d36 #define RTL8367C_SVLAN_C2SCFG18_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG18_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG18_CTRL1 0x0d37 #define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG18_CTRL2 0x0d38 #define RTL8367C_SVLAN_C2SCFG18_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG18_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG19_CTRL0 0x0d39 #define RTL8367C_SVLAN_C2SCFG19_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG19_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG19_CTRL1 0x0d3a #define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG19_CTRL2 0x0d3b #define RTL8367C_SVLAN_C2SCFG19_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG19_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG20_CTRL0 0x0d3c #define RTL8367C_SVLAN_C2SCFG20_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG20_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG20_CTRL1 0x0d3d #define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG20_CTRL2 0x0d3e #define RTL8367C_SVLAN_C2SCFG20_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG20_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG21_CTRL0 0x0d3f #define RTL8367C_SVLAN_C2SCFG21_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG21_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG21_CTRL1 0x0d40 #define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG21_CTRL2 0x0d41 #define RTL8367C_SVLAN_C2SCFG21_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG21_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG22_CTRL0 0x0d42 #define RTL8367C_SVLAN_C2SCFG22_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG22_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG22_CTRL1 0x0d43 #define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG22_CTRL2 0x0d44 #define RTL8367C_SVLAN_C2SCFG22_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG22_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG23_CTRL0 0x0d45 #define RTL8367C_SVLAN_C2SCFG23_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG23_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG23_CTRL1 0x0d46 #define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG23_CTRL2 0x0d47 #define RTL8367C_SVLAN_C2SCFG23_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG23_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG24_CTRL0 0x0d48 #define RTL8367C_SVLAN_C2SCFG24_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG24_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG24_CTRL1 0x0d49 #define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG24_CTRL2 0x0d4a #define RTL8367C_SVLAN_C2SCFG24_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG24_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG25_CTRL0 0x0d4b #define RTL8367C_SVLAN_C2SCFG25_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG25_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG25_CTRL1 0x0d4c #define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG25_CTRL2 0x0d4d #define RTL8367C_SVLAN_C2SCFG25_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG25_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG26_CTRL0 0x0d4e #define RTL8367C_SVLAN_C2SCFG26_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG26_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG26_CTRL1 0x0d4f #define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG26_CTRL2 0x0d50 #define RTL8367C_SVLAN_C2SCFG26_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG26_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG27_CTRL0 0x0d51 #define RTL8367C_SVLAN_C2SCFG27_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG27_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG27_CTRL1 0x0d52 #define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG27_CTRL2 0x0d53 #define RTL8367C_SVLAN_C2SCFG27_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG27_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG28_CTRL0 0x0d54 #define RTL8367C_SVLAN_C2SCFG28_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG28_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG28_CTRL1 0x0d55 #define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG28_CTRL2 0x0d56 #define RTL8367C_SVLAN_C2SCFG28_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG28_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG29_CTRL0 0x0d57 #define RTL8367C_SVLAN_C2SCFG29_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG29_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG29_CTRL1 0x0d58 #define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG29_CTRL2 0x0d59 #define RTL8367C_SVLAN_C2SCFG29_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG29_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG30_CTRL0 0x0d5a #define RTL8367C_SVLAN_C2SCFG30_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG30_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG30_CTRL1 0x0d5b #define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG30_CTRL2 0x0d5c #define RTL8367C_SVLAN_C2SCFG30_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG30_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG31_CTRL0 0x0d5d #define RTL8367C_SVLAN_C2SCFG31_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG31_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG31_CTRL1 0x0d5e #define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG31_CTRL2 0x0d5f #define RTL8367C_SVLAN_C2SCFG31_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG31_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG32_CTRL0 0x0d60 #define RTL8367C_SVLAN_C2SCFG32_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG32_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG32_CTRL1 0x0d61 #define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG32_CTRL2 0x0d62 #define RTL8367C_SVLAN_C2SCFG32_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG32_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG33_CTRL0 0x0d63 #define RTL8367C_SVLAN_C2SCFG33_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG33_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG33_CTRL1 0x0d64 #define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG33_CTRL2 0x0d65 #define RTL8367C_SVLAN_C2SCFG33_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG33_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG34_CTRL0 0x0d66 #define RTL8367C_SVLAN_C2SCFG34_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG34_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG34_CTRL1 0x0d67 #define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG34_CTRL2 0x0d68 #define RTL8367C_SVLAN_C2SCFG34_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG34_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG35_CTRL0 0x0d69 #define RTL8367C_SVLAN_C2SCFG35_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG35_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG35_CTRL1 0x0d6a #define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG35_CTRL2 0x0d6b #define RTL8367C_SVLAN_C2SCFG35_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG35_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG36_CTRL0 0x0d6c #define RTL8367C_SVLAN_C2SCFG36_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG36_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG36_CTRL1 0x0d6d #define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG36_CTRL2 0x0d6e #define RTL8367C_SVLAN_C2SCFG36_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG36_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG37_CTRL0 0x0d6f #define RTL8367C_SVLAN_C2SCFG37_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG37_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG37_CTRL1 0x0d70 #define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG37_CTRL2 0x0d71 #define RTL8367C_SVLAN_C2SCFG37_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG37_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG38_CTRL0 0x0d72 #define RTL8367C_SVLAN_C2SCFG38_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG38_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG38_CTRL1 0x0d73 #define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG38_CTRL2 0x0d74 #define RTL8367C_SVLAN_C2SCFG38_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG38_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG39_CTRL0 0x0d75 #define RTL8367C_SVLAN_C2SCFG39_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG39_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG39_CTRL1 0x0d76 #define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG39_CTRL2 0x0d77 #define RTL8367C_SVLAN_C2SCFG39_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG39_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG40_CTRL0 0x0d78 #define RTL8367C_SVLAN_C2SCFG40_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG40_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG40_CTRL1 0x0d79 #define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG40_CTRL2 0x0d7a #define RTL8367C_SVLAN_C2SCFG40_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG40_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG41_CTRL0 0x0d7b #define RTL8367C_SVLAN_C2SCFG41_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG41_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG41_CTRL1 0x0d7c #define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG41_CTRL2 0x0d7d #define RTL8367C_SVLAN_C2SCFG41_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG41_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG42_CTRL0 0x0d7e #define RTL8367C_SVLAN_C2SCFG42_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG42_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG42_CTRL1 0x0d7f #define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG42_CTRL2 0x0d80 #define RTL8367C_SVLAN_C2SCFG42_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG42_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG43_CTRL0 0x0d81 #define RTL8367C_SVLAN_C2SCFG43_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG43_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG43_CTRL1 0x0d82 #define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG43_CTRL2 0x0d83 #define RTL8367C_SVLAN_C2SCFG43_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG43_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG44_CTRL0 0x0d84 #define RTL8367C_SVLAN_C2SCFG44_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG44_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG44_CTRL1 0x0d85 #define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG44_CTRL2 0x0d86 #define RTL8367C_SVLAN_C2SCFG44_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG44_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG45_CTRL0 0x0d87 #define RTL8367C_SVLAN_C2SCFG45_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG45_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG45_CTRL1 0x0d88 #define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG45_CTRL2 0x0d89 #define RTL8367C_SVLAN_C2SCFG45_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG45_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG46_CTRL0 0x0d8a #define RTL8367C_SVLAN_C2SCFG46_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG46_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG46_CTRL1 0x0d8b #define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG46_CTRL2 0x0d8c #define RTL8367C_SVLAN_C2SCFG46_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG46_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG47_CTRL0 0x0d8d #define RTL8367C_SVLAN_C2SCFG47_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG47_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG47_CTRL1 0x0d8e #define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG47_CTRL2 0x0d8f #define RTL8367C_SVLAN_C2SCFG47_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG47_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG48_CTRL0 0x0d90 #define RTL8367C_SVLAN_C2SCFG48_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG48_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG48_CTRL1 0x0d91 #define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG48_CTRL2 0x0d92 #define RTL8367C_SVLAN_C2SCFG48_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG48_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG49_CTRL0 0x0d93 #define RTL8367C_SVLAN_C2SCFG49_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG49_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG49_CTRL1 0x0d94 #define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG49_CTRL2 0x0d95 #define RTL8367C_SVLAN_C2SCFG49_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG49_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG50_CTRL0 0x0d96 #define RTL8367C_SVLAN_C2SCFG50_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG50_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG50_CTRL1 0x0d97 #define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG50_CTRL2 0x0d98 #define RTL8367C_SVLAN_C2SCFG50_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG50_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG51_CTRL0 0x0d99 #define RTL8367C_SVLAN_C2SCFG51_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG51_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG51_CTRL1 0x0d9a #define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG51_CTRL2 0x0d9b #define RTL8367C_SVLAN_C2SCFG51_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG51_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG52_CTRL0 0x0d9c #define RTL8367C_SVLAN_C2SCFG52_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG52_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG52_CTRL1 0x0d9d #define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG52_CTRL2 0x0d9e #define RTL8367C_SVLAN_C2SCFG52_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG52_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG53_CTRL0 0x0d9f #define RTL8367C_SVLAN_C2SCFG53_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG53_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG53_CTRL1 0x0da0 #define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG53_CTRL2 0x0da1 #define RTL8367C_SVLAN_C2SCFG53_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG53_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG54_CTRL0 0x0da2 #define RTL8367C_SVLAN_C2SCFG54_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG54_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG54_CTRL1 0x0da3 #define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG54_CTRL2 0x0da4 #define RTL8367C_SVLAN_C2SCFG54_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG54_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG55_CTRL0 0x0da5 #define RTL8367C_SVLAN_C2SCFG55_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG55_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG55_CTRL1 0x0da6 #define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG55_CTRL2 0x0da7 #define RTL8367C_SVLAN_C2SCFG55_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG55_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG56_CTRL0 0x0da8 #define RTL8367C_SVLAN_C2SCFG56_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG56_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG56_CTRL1 0x0da9 #define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG56_CTRL2 0x0daa #define RTL8367C_SVLAN_C2SCFG56_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG56_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG57_CTRL0 0x0dab #define RTL8367C_SVLAN_C2SCFG57_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG57_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG57_CTRL1 0x0dac #define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG57_CTRL2 0x0dad #define RTL8367C_SVLAN_C2SCFG57_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG57_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG58_CTRL0 0x0dae #define RTL8367C_SVLAN_C2SCFG58_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG58_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG58_CTRL1 0x0daf #define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG58_CTRL2 0x0db0 #define RTL8367C_SVLAN_C2SCFG58_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG58_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG59_CTRL0 0x0db1 #define RTL8367C_SVLAN_C2SCFG59_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG59_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG59_CTRL1 0x0db2 #define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG59_CTRL2 0x0db3 #define RTL8367C_SVLAN_C2SCFG59_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG59_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG60_CTRL0 0x0db4 #define RTL8367C_SVLAN_C2SCFG60_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG60_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG60_CTRL1 0x0db5 #define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG60_CTRL2 0x0db6 #define RTL8367C_SVLAN_C2SCFG60_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG60_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG61_CTRL0 0x0db7 #define RTL8367C_SVLAN_C2SCFG61_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG61_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG61_CTRL1 0x0db8 #define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG61_CTRL2 0x0db9 #define RTL8367C_SVLAN_C2SCFG61_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG61_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG62_CTRL0 0x0dba #define RTL8367C_SVLAN_C2SCFG62_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG62_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG62_CTRL1 0x0dbb #define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG62_CTRL2 0x0dbc #define RTL8367C_SVLAN_C2SCFG62_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG62_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG63_CTRL0 0x0dbd #define RTL8367C_SVLAN_C2SCFG63_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG63_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG63_CTRL1 0x0dbe #define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG63_CTRL2 0x0dbf #define RTL8367C_SVLAN_C2SCFG63_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG63_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG64_CTRL0 0x0dc0 #define RTL8367C_SVLAN_C2SCFG64_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG64_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG64_CTRL1 0x0dc1 #define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG64_CTRL2 0x0dc2 #define RTL8367C_SVLAN_C2SCFG64_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG64_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG65_CTRL0 0x0dc3 #define RTL8367C_SVLAN_C2SCFG65_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG65_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG65_CTRL1 0x0dc4 #define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG65_CTRL2 0x0dc5 #define RTL8367C_SVLAN_C2SCFG65_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG65_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG66_CTRL0 0x0dc6 #define RTL8367C_SVLAN_C2SCFG66_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG66_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG66_CTRL1 0x0dc7 #define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG66_CTRL2 0x0dc8 #define RTL8367C_SVLAN_C2SCFG66_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG66_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG67_CTRL0 0x0dc9 #define RTL8367C_SVLAN_C2SCFG67_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG67_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG67_CTRL1 0x0dca #define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG67_CTRL2 0x0dcb #define RTL8367C_SVLAN_C2SCFG67_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG67_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG68_CTRL0 0x0dcc #define RTL8367C_SVLAN_C2SCFG68_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG68_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG68_CTRL1 0x0dcd #define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG68_CTRL2 0x0dce #define RTL8367C_SVLAN_C2SCFG68_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG68_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG69_CTRL0 0x0dcf #define RTL8367C_SVLAN_C2SCFG69_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG69_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG69_CTRL1 0x0dd0 #define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG69_CTRL2 0x0dd1 #define RTL8367C_SVLAN_C2SCFG69_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG69_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG70_CTRL0 0x0dd2 #define RTL8367C_SVLAN_C2SCFG70_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG70_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG70_CTRL1 0x0dd3 #define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG70_CTRL2 0x0dd4 #define RTL8367C_SVLAN_C2SCFG70_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG70_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG71_CTRL0 0x0dd5 #define RTL8367C_SVLAN_C2SCFG71_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG71_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG71_CTRL1 0x0dd6 #define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG71_CTRL2 0x0dd7 #define RTL8367C_SVLAN_C2SCFG71_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG71_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG72_CTRL0 0x0dd8 #define RTL8367C_SVLAN_C2SCFG72_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG72_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG72_CTRL1 0x0dd9 #define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG72_CTRL2 0x0dda #define RTL8367C_SVLAN_C2SCFG72_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG72_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG73_CTRL0 0x0ddb #define RTL8367C_SVLAN_C2SCFG73_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG73_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG73_CTRL1 0x0ddc #define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG73_CTRL2 0x0ddd #define RTL8367C_SVLAN_C2SCFG73_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG73_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG74_CTRL0 0x0dde #define RTL8367C_SVLAN_C2SCFG74_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG74_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG74_CTRL1 0x0ddf #define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG74_CTRL2 0x0de0 #define RTL8367C_SVLAN_C2SCFG74_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG74_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG75_CTRL0 0x0de1 #define RTL8367C_SVLAN_C2SCFG75_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG75_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG75_CTRL1 0x0de2 #define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG75_CTRL2 0x0de3 #define RTL8367C_SVLAN_C2SCFG75_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG75_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG76_CTRL0 0x0de4 #define RTL8367C_SVLAN_C2SCFG76_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG76_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG76_CTRL1 0x0de5 #define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG76_CTRL2 0x0de6 #define RTL8367C_SVLAN_C2SCFG76_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG76_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG77_CTRL0 0x0de7 #define RTL8367C_SVLAN_C2SCFG77_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG77_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG77_CTRL1 0x0de8 #define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG77_CTRL2 0x0de9 #define RTL8367C_SVLAN_C2SCFG77_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG77_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG78_CTRL0 0x0dea #define RTL8367C_SVLAN_C2SCFG78_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG78_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG78_CTRL1 0x0deb #define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG78_CTRL2 0x0dec #define RTL8367C_SVLAN_C2SCFG78_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG78_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG79_CTRL0 0x0ded #define RTL8367C_SVLAN_C2SCFG79_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG79_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG79_CTRL1 0x0dee #define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG79_CTRL2 0x0def #define RTL8367C_SVLAN_C2SCFG79_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG79_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG80_CTRL0 0x0df0 #define RTL8367C_SVLAN_C2SCFG80_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG80_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG80_CTRL1 0x0df1 #define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG80_CTRL2 0x0df2 #define RTL8367C_SVLAN_C2SCFG80_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG80_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG81_CTRL0 0x0df3 #define RTL8367C_SVLAN_C2SCFG81_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG81_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG81_CTRL1 0x0df4 #define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG81_CTRL2 0x0df5 #define RTL8367C_SVLAN_C2SCFG81_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG81_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG82_CTRL0 0x0df6 #define RTL8367C_SVLAN_C2SCFG82_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG82_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG82_CTRL1 0x0df7 #define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG82_CTRL2 0x0df8 #define RTL8367C_SVLAN_C2SCFG82_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG82_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG83_CTRL0 0x0df9 #define RTL8367C_SVLAN_C2SCFG83_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG83_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG83_CTRL1 0x0dfa #define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG83_CTRL2 0x0dfb #define RTL8367C_SVLAN_C2SCFG83_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG83_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG84_CTRL0 0x0dfc #define RTL8367C_SVLAN_C2SCFG84_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG84_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG84_CTRL1 0x0dfd #define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG84_CTRL2 0x0dfe #define RTL8367C_SVLAN_C2SCFG84_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG84_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG85_CTRL0 0x0dff #define RTL8367C_SVLAN_C2SCFG85_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG85_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG85_CTRL1 0x0e00 #define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG85_CTRL2 0x0e01 #define RTL8367C_SVLAN_C2SCFG85_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG85_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG86_CTRL0 0x0e02 #define RTL8367C_SVLAN_C2SCFG86_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG86_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG86_CTRL1 0x0e03 #define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG86_CTRL2 0x0e04 #define RTL8367C_SVLAN_C2SCFG86_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG86_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG87_CTRL0 0x0e05 #define RTL8367C_SVLAN_C2SCFG87_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG87_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG87_CTRL1 0x0e06 #define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG87_CTRL2 0x0e07 #define RTL8367C_SVLAN_C2SCFG87_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG87_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG88_CTRL0 0x0e08 #define RTL8367C_SVLAN_C2SCFG88_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG88_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG88_CTRL1 0x0e09 #define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG88_CTRL2 0x0e0a #define RTL8367C_SVLAN_C2SCFG88_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG88_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG89_CTRL0 0x0e0b #define RTL8367C_SVLAN_C2SCFG89_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG89_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG89_CTRL1 0x0e0c #define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG89_CTRL2 0x0e0d #define RTL8367C_SVLAN_C2SCFG89_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG89_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG90_CTRL0 0x0e0e #define RTL8367C_SVLAN_C2SCFG90_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG90_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG90_CTRL1 0x0e0f #define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG90_CTRL2 0x0e10 #define RTL8367C_SVLAN_C2SCFG90_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG90_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG91_CTRL0 0x0e11 #define RTL8367C_SVLAN_C2SCFG91_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG91_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG91_CTRL1 0x0e12 #define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG91_CTRL2 0x0e13 #define RTL8367C_SVLAN_C2SCFG91_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG91_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG92_CTRL0 0x0e14 #define RTL8367C_SVLAN_C2SCFG92_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG92_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG92_CTRL1 0x0e15 #define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG92_CTRL2 0x0e16 #define RTL8367C_SVLAN_C2SCFG92_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG92_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG93_CTRL0 0x0e17 #define RTL8367C_SVLAN_C2SCFG93_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG93_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG93_CTRL1 0x0e18 #define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG93_CTRL2 0x0e19 #define RTL8367C_SVLAN_C2SCFG93_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG93_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG94_CTRL0 0x0e1a #define RTL8367C_SVLAN_C2SCFG94_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG94_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG94_CTRL1 0x0e1b #define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG94_CTRL2 0x0e1c #define RTL8367C_SVLAN_C2SCFG94_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG94_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG95_CTRL0 0x0e1d #define RTL8367C_SVLAN_C2SCFG95_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG95_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG95_CTRL1 0x0e1e #define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG95_CTRL2 0x0e1f #define RTL8367C_SVLAN_C2SCFG95_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG95_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG96_CTRL0 0x0e20 #define RTL8367C_SVLAN_C2SCFG96_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG96_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG96_CTRL1 0x0e21 #define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG96_CTRL2 0x0e22 #define RTL8367C_SVLAN_C2SCFG96_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG96_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG97_CTRL0 0x0e23 #define RTL8367C_SVLAN_C2SCFG97_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG97_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG97_CTRL1 0x0e24 #define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG97_CTRL2 0x0e25 #define RTL8367C_SVLAN_C2SCFG97_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG97_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG98_CTRL0 0x0e26 #define RTL8367C_SVLAN_C2SCFG98_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG98_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG98_CTRL1 0x0e27 #define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG98_CTRL2 0x0e28 #define RTL8367C_SVLAN_C2SCFG98_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG98_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG99_CTRL0 0x0e29 #define RTL8367C_SVLAN_C2SCFG99_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG99_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG99_CTRL1 0x0e2a #define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG99_CTRL2 0x0e2b #define RTL8367C_SVLAN_C2SCFG99_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG99_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG100_CTRL0 0x0e2c #define RTL8367C_SVLAN_C2SCFG100_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG100_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG100_CTRL1 0x0e2d #define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG100_CTRL2 0x0e2e #define RTL8367C_SVLAN_C2SCFG100_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG100_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG101_CTRL0 0x0e2f #define RTL8367C_SVLAN_C2SCFG101_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG101_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG101_CTRL1 0x0e30 #define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG101_CTRL2 0x0e31 #define RTL8367C_SVLAN_C2SCFG101_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG101_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG102_CTRL0 0x0e32 #define RTL8367C_SVLAN_C2SCFG102_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG102_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG102_CTRL1 0x0e33 #define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG102_CTRL2 0x0e34 #define RTL8367C_SVLAN_C2SCFG102_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG102_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG103_CTRL0 0x0e35 #define RTL8367C_SVLAN_C2SCFG103_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG103_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG103_CTRL1 0x0e36 #define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG103_CTRL2 0x0e37 #define RTL8367C_SVLAN_C2SCFG103_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG103_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG104_CTRL0 0x0e38 #define RTL8367C_SVLAN_C2SCFG104_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG104_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG104_CTRL1 0x0e39 #define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG104_CTRL2 0x0e3a #define RTL8367C_SVLAN_C2SCFG104_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG104_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG105_CTRL0 0x0e3b #define RTL8367C_SVLAN_C2SCFG105_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG105_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG105_CTRL1 0x0e3c #define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG105_CTRL2 0x0e3d #define RTL8367C_SVLAN_C2SCFG105_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG105_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG106_CTRL0 0x0e3e #define RTL8367C_SVLAN_C2SCFG106_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG106_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG106_CTRL1 0x0e3f #define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG106_CTRL2 0x0e40 #define RTL8367C_SVLAN_C2SCFG106_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG106_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG107_CTRL0 0x0e41 #define RTL8367C_SVLAN_C2SCFG107_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG107_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG107_CTRL1 0x0e42 #define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG107_CTRL2 0x0e43 #define RTL8367C_SVLAN_C2SCFG107_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG107_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG108_CTRL0 0x0e44 #define RTL8367C_SVLAN_C2SCFG108_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG108_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG108_CTRL1 0x0e45 #define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG108_CTRL2 0x0e46 #define RTL8367C_SVLAN_C2SCFG108_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG108_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG109_CTRL0 0x0e47 #define RTL8367C_SVLAN_C2SCFG109_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG109_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG109_CTRL1 0x0e48 #define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG109_CTRL2 0x0e49 #define RTL8367C_SVLAN_C2SCFG109_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG109_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG110_CTRL0 0x0e4a #define RTL8367C_SVLAN_C2SCFG110_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG110_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG110_CTRL1 0x0e4b #define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG110_CTRL2 0x0e4c #define RTL8367C_SVLAN_C2SCFG110_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG110_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG111_CTRL0 0x0e4d #define RTL8367C_SVLAN_C2SCFG111_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG111_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG111_CTRL1 0x0e4e #define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG111_CTRL2 0x0e4f #define RTL8367C_SVLAN_C2SCFG111_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG111_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG112_CTRL0 0x0e50 #define RTL8367C_SVLAN_C2SCFG112_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG112_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG112_CTRL1 0x0e51 #define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG112_CTRL2 0x0e52 #define RTL8367C_SVLAN_C2SCFG112_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG112_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG113_CTRL0 0x0e53 #define RTL8367C_SVLAN_C2SCFG113_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG113_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG113_CTRL1 0x0e54 #define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG113_CTRL2 0x0e55 #define RTL8367C_SVLAN_C2SCFG113_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG113_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG114_CTRL0 0x0e56 #define RTL8367C_SVLAN_C2SCFG114_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG114_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG114_CTRL1 0x0e57 #define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG114_CTRL2 0x0e58 #define RTL8367C_SVLAN_C2SCFG114_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG114_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG115_CTRL0 0x0e59 #define RTL8367C_SVLAN_C2SCFG115_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG115_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG115_CTRL1 0x0e5a #define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG115_CTRL2 0x0e5b #define RTL8367C_SVLAN_C2SCFG115_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG115_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG116_CTRL0 0x0e5c #define RTL8367C_SVLAN_C2SCFG116_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG116_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG116_CTRL1 0x0e5d #define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG116_CTRL2 0x0e5e #define RTL8367C_SVLAN_C2SCFG116_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG116_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG117_CTRL0 0x0e5f #define RTL8367C_SVLAN_C2SCFG117_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG117_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG117_CTRL1 0x0e60 #define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG117_CTRL2 0x0e61 #define RTL8367C_SVLAN_C2SCFG117_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG117_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG118_CTRL0 0x0e62 #define RTL8367C_SVLAN_C2SCFG118_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG118_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG118_CTRL1 0x0e63 #define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG118_CTRL2 0x0e64 #define RTL8367C_SVLAN_C2SCFG118_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG118_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG119_CTRL0 0x0e65 #define RTL8367C_SVLAN_C2SCFG119_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG119_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG119_CTRL1 0x0e66 #define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG119_CTRL2 0x0e67 #define RTL8367C_SVLAN_C2SCFG119_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG119_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG120_CTRL0 0x0e68 #define RTL8367C_SVLAN_C2SCFG120_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG120_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG120_CTRL1 0x0e69 #define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG120_CTRL2 0x0e6a #define RTL8367C_SVLAN_C2SCFG120_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG120_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG121_CTRL0 0x0e6b #define RTL8367C_SVLAN_C2SCFG121_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG121_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG121_CTRL1 0x0e6c #define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG121_CTRL2 0x0e6d #define RTL8367C_SVLAN_C2SCFG121_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG121_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG122_CTRL0 0x0e6e #define RTL8367C_SVLAN_C2SCFG122_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG122_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG122_CTRL1 0x0e6f #define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG122_CTRL2 0x0e70 #define RTL8367C_SVLAN_C2SCFG122_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG122_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG123_CTRL0 0x0e71 #define RTL8367C_SVLAN_C2SCFG123_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG123_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG123_CTRL1 0x0e72 #define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG123_CTRL2 0x0e73 #define RTL8367C_SVLAN_C2SCFG123_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG123_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG124_CTRL0 0x0e74 #define RTL8367C_SVLAN_C2SCFG124_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG124_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG124_CTRL1 0x0e75 #define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG124_CTRL2 0x0e76 #define RTL8367C_SVLAN_C2SCFG124_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG124_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG125_CTRL0 0x0e77 #define RTL8367C_SVLAN_C2SCFG125_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG125_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG125_CTRL1 0x0e78 #define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG125_CTRL2 0x0e79 #define RTL8367C_SVLAN_C2SCFG125_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG125_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG126_CTRL0 0x0e7a #define RTL8367C_SVLAN_C2SCFG126_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG126_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG126_CTRL1 0x0e7b #define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG126_CTRL2 0x0e7c #define RTL8367C_SVLAN_C2SCFG126_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG126_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_C2SCFG127_CTRL0 0x0e7d #define RTL8367C_SVLAN_C2SCFG127_CTRL0_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG127_CTRL0_MASK 0x3F #define RTL8367C_REG_SVLAN_C2SCFG127_CTRL1 0x0e7e #define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_OFFSET 8 #define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_MASK 0x700 #define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_MASK 0xFF #define RTL8367C_REG_SVLAN_C2SCFG127_CTRL2 0x0e7f #define RTL8367C_SVLAN_C2SCFG127_CTRL2_OFFSET 0 #define RTL8367C_SVLAN_C2SCFG127_CTRL2_MASK 0x1FFF #define RTL8367C_REG_SVLAN_CFG 0x0e80 #define RTL8367C_VS_PORT7_DMACVIDSEL_OFFSET 14 #define RTL8367C_VS_PORT7_DMACVIDSEL_MASK 0x4000 #define RTL8367C_VS_PORT6_DMACVIDSEL_OFFSET 13 #define RTL8367C_VS_PORT6_DMACVIDSEL_MASK 0x2000 #define RTL8367C_VS_PORT5_DMACVIDSEL_OFFSET 12 #define RTL8367C_VS_PORT5_DMACVIDSEL_MASK 0x1000 #define RTL8367C_VS_PORT4_DMACVIDSEL_OFFSET 11 #define RTL8367C_VS_PORT4_DMACVIDSEL_MASK 0x800 #define RTL8367C_VS_PORT3_DMACVIDSEL_OFFSET 10 #define RTL8367C_VS_PORT3_DMACVIDSEL_MASK 0x400 #define RTL8367C_VS_PORT2_DMACVIDSEL_OFFSET 9 #define RTL8367C_VS_PORT2_DMACVIDSEL_MASK 0x200 #define RTL8367C_VS_PORT1_DMACVIDSEL_OFFSET 8 #define RTL8367C_VS_PORT1_DMACVIDSEL_MASK 0x100 #define RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET 7 #define RTL8367C_VS_PORT0_DMACVIDSEL_MASK 0x80 #define RTL8367C_VS_UIFSEG_OFFSET 6 #define RTL8367C_VS_UIFSEG_MASK 0x40 #define RTL8367C_VS_UNMAT_OFFSET 4 #define RTL8367C_VS_UNMAT_MASK 0x30 #define RTL8367C_VS_UNTAG_OFFSET 2 #define RTL8367C_VS_UNTAG_MASK 0xC #define RTL8367C_VS_SPRISEL_OFFSET 0 #define RTL8367C_VS_SPRISEL_MASK 0x3 #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 0x0e81 #define RTL8367C_VS_PORT1_SVIDX_OFFSET 8 #define RTL8367C_VS_PORT1_SVIDX_MASK 0x3F00 #define RTL8367C_VS_PORT0_SVIDX_OFFSET 0 #define RTL8367C_VS_PORT0_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL1 0x0e82 #define RTL8367C_VS_PORT3_SVIDX_OFFSET 8 #define RTL8367C_VS_PORT3_SVIDX_MASK 0x3F00 #define RTL8367C_VS_PORT2_SVIDX_OFFSET 0 #define RTL8367C_VS_PORT2_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL2 0x0e83 #define RTL8367C_VS_PORT5_SVIDX_OFFSET 8 #define RTL8367C_VS_PORT5_SVIDX_MASK 0x3F00 #define RTL8367C_VS_PORT4_SVIDX_OFFSET 0 #define RTL8367C_VS_PORT4_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL3 0x0e84 #define RTL8367C_VS_PORT7_SVIDX_OFFSET 8 #define RTL8367C_VS_PORT7_SVIDX_MASK 0x3F00 #define RTL8367C_VS_PORT6_SVIDX_OFFSET 0 #define RTL8367C_VS_PORT6_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG 0x0e85 #define RTL8367C_VS_UNTAG_SVIDX_OFFSET 8 #define RTL8367C_VS_UNTAG_SVIDX_MASK 0x3F00 #define RTL8367C_VS_UNMAT_SVIDX_OFFSET 0 #define RTL8367C_VS_UNMAT_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_LOOKUP_TYPE 0x0e86 #define RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET 0 #define RTL8367C_SVLAN_LOOKUP_TYPE_MASK 0x1 #define RTL8367C_REG_IPMC_GROUP_VALID_15_0 0x0e87 #define RTL8367C_REG_IPMC_GROUP_VALID_31_16 0x0e88 #define RTL8367C_REG_IPMC_GROUP_VALID_47_32 0x0e89 #define RTL8367C_REG_IPMC_GROUP_VALID_63_48 0x0e8a #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4 0x0e8b #define RTL8367C_VS_PORT9_SVIDX_OFFSET 8 #define RTL8367C_VS_PORT9_SVIDX_MASK 0x3F00 #define RTL8367C_VS_PORT8_SVIDX_OFFSET 0 #define RTL8367C_VS_PORT8_SVIDX_MASK 0x3F #define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5 0x0e8c #define RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_OFFSET 0 #define RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK 0x3F #define RTL8367C_REG_SVLAN_CFG_EXT 0x0e8d #define RTL8367C_VS_PORT10_DMACVIDSEL_OFFSET 2 #define RTL8367C_VS_PORT10_DMACVIDSEL_MASK 0x4 #define RTL8367C_VS_PORT9_DMACVIDSEL_OFFSET 1 #define RTL8367C_VS_PORT9_DMACVIDSEL_MASK 0x2 #define RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET 0 #define RTL8367C_VS_PORT8_DMACVIDSEL_MASK 0x1 #define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4 0x0e8e #define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_OFFSET 0 #define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_MASK 0x7 #define RTL8367C_REG_SVLAN_DUMMY_0 0x0e90 #define RTL8367C_REG_SVLAN_DUMMY_1 0x0e91 #define RTL8367C_REG_SVLAN_DUMMY_2 0x0e92 #define RTL8367C_REG_SVLAN_DUMMY_3 0x0e93 #define RTL8367C_REG_SVLAN_DUMMY_4 0x0e94 #define RTL8367C_REG_SVLAN_DUMMY_5 0x0e95 #define RTL8367C_REG_SVLAN_DUMMY_6 0x0e96 #define RTL8367C_REG_SVLAN_DUMMY_7 0x0e97 #define RTL8367C_REG_SVLAN_DUMMY_8 0x0e98 #define RTL8367C_REG_SVLAN_DUMMY_9 0x0e99 #define RTL8367C_REG_SVLAN_DUMMY_10 0x0e9a #define RTL8367C_REG_SVLAN_DUMMY_11 0x0e9b #define RTL8367C_REG_SVLAN_DUMMY_12 0x0e9c #define RTL8367C_REG_SVLAN_DUMMY_13 0x0e9d #define RTL8367C_REG_SVLAN_DUMMY_14 0x0e9e #define RTL8367C_REG_SVLAN_DUMMY_15 0x0e9f #define RTL8367C_REG_SVLAN_DUMMY_16 0x0ea0 #define RTL8367C_REG_SVLAN_DUMMY_17 0x0ea1 #define RTL8367C_REG_SVLAN_DUMMY_18 0x0ea2 #define RTL8367C_REG_SVLAN_DUMMY_19 0x0ea3 #define RTL8367C_REG_SVLAN_DUMMY_20 0x0ea4 #define RTL8367C_REG_SVLAN_DUMMY_21 0x0ea5 #define RTL8367C_REG_SVLAN_DUMMY_22 0x0ea6 #define RTL8367C_REG_SVLAN_DUMMY_23 0x0ea7 #define RTL8367C_REG_SVLAN_DUMMY_24 0x0ea8 #define RTL8367C_REG_SVLAN_DUMMY_25 0x0ea9 #define RTL8367C_REG_SVLAN_DUMMY_26 0x0eaa #define RTL8367C_REG_SVLAN_DUMMY_27 0x0eab #define RTL8367C_REG_SVLAN_DUMMY_28 0x0eac #define RTL8367C_REG_SVLAN_DUMMY_29 0x0ead #define RTL8367C_REG_SVLAN_DUMMY_30 0x0eae #define RTL8367C_REG_SVLAN_DUMMY_31 0x0eaf #define RTL8367C_REG_IPMC_GROUP_VID_00 0x0eb0 #define RTL8367C_IPMC_GROUP_VID_00_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_00_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_01 0x0eb1 #define RTL8367C_IPMC_GROUP_VID_01_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_01_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_02 0x0eb2 #define RTL8367C_IPMC_GROUP_VID_02_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_02_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_03 0x0eb3 #define RTL8367C_IPMC_GROUP_VID_03_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_03_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_04 0x0eb4 #define RTL8367C_IPMC_GROUP_VID_04_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_04_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_05 0x0eb5 #define RTL8367C_IPMC_GROUP_VID_05_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_05_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_06 0x0eb6 #define RTL8367C_IPMC_GROUP_VID_06_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_06_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_07 0x0eb7 #define RTL8367C_IPMC_GROUP_VID_07_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_07_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_08 0x0eb8 #define RTL8367C_IPMC_GROUP_VID_08_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_08_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_09 0x0eb9 #define RTL8367C_IPMC_GROUP_VID_09_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_09_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_10 0x0eba #define RTL8367C_IPMC_GROUP_VID_10_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_10_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_11 0x0ebb #define RTL8367C_IPMC_GROUP_VID_11_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_11_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_12 0x0ebc #define RTL8367C_IPMC_GROUP_VID_12_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_12_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_13 0x0ebd #define RTL8367C_IPMC_GROUP_VID_13_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_13_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_14 0x0ebe #define RTL8367C_IPMC_GROUP_VID_14_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_14_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_15 0x0ebf #define RTL8367C_IPMC_GROUP_VID_15_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_15_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_16 0x0ec0 #define RTL8367C_IPMC_GROUP_VID_16_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_16_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_17 0x0ec1 #define RTL8367C_IPMC_GROUP_VID_17_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_17_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_18 0x0ec2 #define RTL8367C_IPMC_GROUP_VID_18_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_18_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_19 0x0ec3 #define RTL8367C_IPMC_GROUP_VID_19_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_19_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_20 0x0ec4 #define RTL8367C_IPMC_GROUP_VID_20_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_20_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_21 0x0ec5 #define RTL8367C_IPMC_GROUP_VID_21_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_21_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_22 0x0ec6 #define RTL8367C_IPMC_GROUP_VID_22_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_22_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_23 0x0ec7 #define RTL8367C_IPMC_GROUP_VID_23_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_23_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_24 0x0ec8 #define RTL8367C_IPMC_GROUP_VID_24_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_24_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_25 0x0ec9 #define RTL8367C_IPMC_GROUP_VID_25_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_25_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_26 0x0eca #define RTL8367C_IPMC_GROUP_VID_26_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_26_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_27 0x0ecb #define RTL8367C_IPMC_GROUP_VID_27_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_27_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_28 0x0ecc #define RTL8367C_IPMC_GROUP_VID_28_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_28_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_29 0x0ecd #define RTL8367C_IPMC_GROUP_VID_29_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_29_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_30 0x0ece #define RTL8367C_IPMC_GROUP_VID_30_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_30_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_31 0x0ecf #define RTL8367C_IPMC_GROUP_VID_31_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_31_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_32 0x0ed0 #define RTL8367C_IPMC_GROUP_VID_32_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_32_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_33 0x0ed1 #define RTL8367C_IPMC_GROUP_VID_33_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_33_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_34 0x0ed2 #define RTL8367C_IPMC_GROUP_VID_34_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_34_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_35 0x0ed3 #define RTL8367C_IPMC_GROUP_VID_35_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_35_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_36 0x0ed4 #define RTL8367C_IPMC_GROUP_VID_36_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_36_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_37 0x0ed5 #define RTL8367C_IPMC_GROUP_VID_37_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_37_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_38 0x0ed6 #define RTL8367C_IPMC_GROUP_VID_38_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_38_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_39 0x0ed7 #define RTL8367C_IPMC_GROUP_VID_39_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_39_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_40 0x0ed8 #define RTL8367C_IPMC_GROUP_VID_40_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_40_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_41 0x0ed9 #define RTL8367C_IPMC_GROUP_VID_41_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_41_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_42 0x0eda #define RTL8367C_IPMC_GROUP_VID_42_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_42_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_43 0x0edb #define RTL8367C_IPMC_GROUP_VID_43_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_43_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_44 0x0edc #define RTL8367C_IPMC_GROUP_VID_44_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_44_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_45 0x0edd #define RTL8367C_IPMC_GROUP_VID_45_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_45_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_46 0x0ede #define RTL8367C_IPMC_GROUP_VID_46_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_46_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_47 0x0edf #define RTL8367C_IPMC_GROUP_VID_47_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_47_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_48 0x0ef0 #define RTL8367C_IPMC_GROUP_VID_48_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_48_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_49 0x0ef1 #define RTL8367C_IPMC_GROUP_VID_49_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_49_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_50 0x0ef2 #define RTL8367C_IPMC_GROUP_VID_50_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_50_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_51 0x0ef3 #define RTL8367C_IPMC_GROUP_VID_51_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_51_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_52 0x0ef4 #define RTL8367C_IPMC_GROUP_VID_52_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_52_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_53 0x0ef5 #define RTL8367C_IPMC_GROUP_VID_53_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_53_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_54 0x0ef6 #define RTL8367C_IPMC_GROUP_VID_54_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_54_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_55 0x0ef7 #define RTL8367C_IPMC_GROUP_VID_55_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_55_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_56 0x0ef8 #define RTL8367C_IPMC_GROUP_VID_56_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_56_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_57 0x0ef9 #define RTL8367C_IPMC_GROUP_VID_57_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_57_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_58 0x0efa #define RTL8367C_IPMC_GROUP_VID_58_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_58_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_59 0x0efb #define RTL8367C_IPMC_GROUP_VID_59_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_59_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_60 0x0efc #define RTL8367C_IPMC_GROUP_VID_60_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_60_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_61 0x0efd #define RTL8367C_IPMC_GROUP_VID_61_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_61_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_62 0x0efe #define RTL8367C_IPMC_GROUP_VID_62_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_62_MASK 0xFFF #define RTL8367C_REG_IPMC_GROUP_VID_63 0x0eff #define RTL8367C_IPMC_GROUP_VID_63_OFFSET 0 #define RTL8367C_IPMC_GROUP_VID_63_MASK 0xFFF /* (16'h0f00)hsactrl_reg */ #define RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL0 0x0f00 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL1 0x0f01 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL0 0x0f02 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL1 0x0f03 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL0 0x0f04 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL1 0x0f05 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL0 0x0f06 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL1 0x0f07 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL0 0x0f08 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL1 0x0f09 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL0 0x0f0a #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL1 0x0f0b #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL0 0x0f0c #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL1 0x0f0d #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL0 0x0f0e #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL1 0x0f0f #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL0 0x0f10 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL1 0x0f11 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL0 0x0f12 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL1 0x0f13 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL0 0x0f14 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL1 0x0f15 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL0 0x0f16 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL1 0x0f17 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL0 0x0f18 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL1 0x0f19 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL0 0x0f1a #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL1 0x0f1b #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL0 0x0f1c #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL1 0x0f1d #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL0 0x0f1e #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL1 0x0f1f #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL0 0x0f20 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL1 0x0f21 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL0 0x0f22 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL1 0x0f23 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL0 0x0f24 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL1 0x0f25 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL0 0x0f26 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL1 0x0f27 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL0 0x0f28 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL1 0x0f29 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL0 0x0f2a #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL1 0x0f2b #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL0 0x0f2c #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL1 0x0f2d #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL0 0x0f2e #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL1 0x0f2f #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL0 0x0f30 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL1 0x0f31 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL0 0x0f32 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL1 0x0f33 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL0 0x0f34 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL1 0x0f35 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL0 0x0f36 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL1 0x0f37 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL0 0x0f38 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL1 0x0f39 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL0 0x0f3a #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL1 0x0f3b #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL0 0x0f3c #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL1 0x0f3d #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL0 0x0f3e #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL1 0x0f3f #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL0 0x0f40 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL1 0x0f41 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL0 0x0f42 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL1 0x0f43 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL0 0x0f44 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL1 0x0f45 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL0 0x0f46 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL1 0x0f47 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL0 0x0f48 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL1 0x0f49 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL0 0x0f4a #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL1 0x0f4b #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL0 0x0f4c #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL1 0x0f4d #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL0 0x0f4e #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL1 0x0f4f #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL0 0x0f50 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL1 0x0f51 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL0 0x0f52 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL1 0x0f53 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL0 0x0f54 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL1 0x0f55 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL0 0x0f56 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL1 0x0f57 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL0 0x0f58 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL1 0x0f59 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL0 0x0f5a #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL1 0x0f5b #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL0 0x0f5c #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL1 0x0f5d #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL0 0x0f5e #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL1 0x0f5f #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL0 0x0f60 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL1 0x0f61 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL0 0x0f62 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL1 0x0f63 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL0 0x0f64 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL1 0x0f65 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL0 0x0f66 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL1 0x0f67 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL0 0x0f68 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL1 0x0f69 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL0 0x0f6a #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL1 0x0f6b #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL0 0x0f6c #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL1 0x0f6d #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL0 0x0f6e #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL1 0x0f6f #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL0 0x0f70 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL1 0x0f71 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL0 0x0f72 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL1 0x0f73 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL0 0x0f74 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL1 0x0f75 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL0 0x0f76 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL1 0x0f77 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL0 0x0f78 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL1 0x0f79 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL0 0x0f7a #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL1 0x0f7b #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL0 0x0f7c #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL1 0x0f7d #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL0 0x0f7e #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL1 0x0f7f #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL0 0x0f80 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL1 0x0f81 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL0 0x0f82 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL1 0x0f83 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL0 0x0f84 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL1 0x0f85 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL0 0x0f86 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL1 0x0f87 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL0 0x0f88 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL1 0x0f89 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL0 0x0f8a #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL1 0x0f8b #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL0 0x0f8c #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL1 0x0f8d #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL0 0x0f8e #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL1 0x0f8f #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL0 0x0f90 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL1 0x0f91 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL0 0x0f92 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL1 0x0f93 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL0 0x0f94 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL1 0x0f95 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL0 0x0f96 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL1 0x0f97 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL0 0x0f98 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL1 0x0f99 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL0 0x0f9a #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL1 0x0f9b #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL0 0x0f9c #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL1 0x0f9d #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL0 0x0f9e #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL1 0x0f9f #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL0 0x0fa0 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL1 0x0fa1 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL0 0x0fa2 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL1 0x0fa3 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL0 0x0fa4 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL1 0x0fa5 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL0 0x0fa6 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL1 0x0fa7 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL0 0x0fa8 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL1 0x0fa9 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL0 0x0faa #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL1 0x0fab #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL0 0x0fac #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL1 0x0fad #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL0 0x0fae #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL1 0x0faf #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL0 0x0fb0 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL1 0x0fb1 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL0 0x0fb2 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL1 0x0fb3 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL0 0x0fb4 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL1 0x0fb5 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL0 0x0fb6 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL1 0x0fb7 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL0 0x0fb8 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL1 0x0fb9 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL0 0x0fba #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL1 0x0fbb #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL0 0x0fbc #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL1 0x0fbd #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL0 0x0fbe #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL1 0x0fbf #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL0 0x0fc0 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL1 0x0fc1 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL0 0x0fc2 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL1 0x0fc3 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL0 0x0fc4 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL1 0x0fc5 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL0 0x0fc6 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL1 0x0fc7 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL0 0x0fc8 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL1 0x0fc9 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL0 0x0fca #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL1 0x0fcb #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL0 0x0fcc #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL1 0x0fcd #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL0 0x0fce #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL1 0x0fcf #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL0 0x0fd0 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL1 0x0fd1 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL0 0x0fd2 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL1 0x0fd3 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL0 0x0fd4 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL1 0x0fd5 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL0 0x0fd6 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL1 0x0fd7 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL0 0x0fd8 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL1 0x0fd9 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL0 0x0fda #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL1 0x0fdb #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL0 0x0fdc #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL1 0x0fdd #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL0 0x0fde #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL1 0x0fdf #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL0 0x0fe0 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL1 0x0fe1 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL0 0x0fe2 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL1 0x0fe3 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL0 0x0fe4 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL1 0x0fe5 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL0 0x0fe6 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL1 0x0fe7 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL0 0x0fe8 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL1 0x0fe9 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL0 0x0fea #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL1 0x0feb #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL0 0x0fec #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL1 0x0fed #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL0 0x0fee #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL1 0x0fef #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL0 0x0ff0 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL1 0x0ff1 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL0 0x0ff2 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL1 0x0ff3 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL0 0x0ff4 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL1 0x0ff5 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL0 0x0ff6 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL1 0x0ff7 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL0 0x0ff8 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL1 0x0ff9 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL0 0x0ffa #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL1 0x0ffb #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL0 0x0ffc #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL1 0x0ffd #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_MASK 0xFFF #define RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL0 0x0ffe #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_OFFSET 9 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_MASK 0x200 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_OFFSET 3 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_MASK 0x1F8 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_MASK 0x7 #define RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL1 0x0fff #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_OFFSET 12 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_MASK 0x1000 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_OFFSET 0 #define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_MASK 0xFFF /* (16'h1000)mib_reg */ #define RTL8367C_REG_MIB_COUNTER0 0x1000 #define RTL8367C_REG_MIB_COUNTER1 0x1001 #define RTL8367C_REG_MIB_COUNTER2 0x1002 #define RTL8367C_REG_MIB_COUNTER3 0x1003 #define RTL8367C_REG_MIB_ADDRESS 0x1004 #define RTL8367C_MIB_ADDRESS_OFFSET 0 #define RTL8367C_MIB_ADDRESS_MASK 0x1FF #define RTL8367C_REG_MIB_CTRL0 0x1005 #define RTL8367C_PORT10_RESET_OFFSET 15 #define RTL8367C_PORT10_RESET_MASK 0x8000 #define RTL8367C_PORT9_RESET_OFFSET 14 #define RTL8367C_PORT9_RESET_MASK 0x4000 #define RTL8367C_PORT8_RESET_OFFSET 13 #define RTL8367C_PORT8_RESET_MASK 0x2000 #define RTL8367C_RESET_VALUE_OFFSET 12 #define RTL8367C_RESET_VALUE_MASK 0x1000 #define RTL8367C_GLOBAL_RESET_OFFSET 11 #define RTL8367C_GLOBAL_RESET_MASK 0x800 #define RTL8367C_QM_RESET_OFFSET 10 #define RTL8367C_QM_RESET_MASK 0x400 #define RTL8367C_PORT7_RESET_OFFSET 9 #define RTL8367C_PORT7_RESET_MASK 0x200 #define RTL8367C_PORT6_RESET_OFFSET 8 #define RTL8367C_PORT6_RESET_MASK 0x100 #define RTL8367C_PORT5_RESET_OFFSET 7 #define RTL8367C_PORT5_RESET_MASK 0x80 #define RTL8367C_PORT4_RESET_OFFSET 6 #define RTL8367C_PORT4_RESET_MASK 0x40 #define RTL8367C_PORT3_RESET_OFFSET 5 #define RTL8367C_PORT3_RESET_MASK 0x20 #define RTL8367C_PORT2_RESET_OFFSET 4 #define RTL8367C_PORT2_RESET_MASK 0x10 #define RTL8367C_PORT1_RESET_OFFSET 3 #define RTL8367C_PORT1_RESET_MASK 0x8 #define RTL8367C_PORT0_RESET_OFFSET 2 #define RTL8367C_PORT0_RESET_MASK 0x4 #define RTL8367C_RESET_FLAG_OFFSET 1 #define RTL8367C_RESET_FLAG_MASK 0x2 #define RTL8367C_MIB_CTRL0_BUSY_FLAG_OFFSET 0 #define RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK 0x1 #define RTL8367C_REG_MIB_CTRL1 0x1007 #define RTL8367C_COUNTER15_RESET_OFFSET 15 #define RTL8367C_COUNTER15_RESET_MASK 0x8000 #define RTL8367C_COUNTER14_RESET_OFFSET 14 #define RTL8367C_COUNTER14_RESET_MASK 0x4000 #define RTL8367C_COUNTER13_RESET_OFFSET 13 #define RTL8367C_COUNTER13_RESET_MASK 0x2000 #define RTL8367C_COUNTER12_RESET_OFFSET 12 #define RTL8367C_COUNTER12_RESET_MASK 0x1000 #define RTL8367C_COUNTER11_RESET_OFFSET 11 #define RTL8367C_COUNTER11_RESET_MASK 0x800 #define RTL8367C_COUNTER10_RESET_OFFSET 10 #define RTL8367C_COUNTER10_RESET_MASK 0x400 #define RTL8367C_COUNTER9_RESET_OFFSET 9 #define RTL8367C_COUNTER9_RESET_MASK 0x200 #define RTL8367C_COUNTER8_RESET_OFFSET 8 #define RTL8367C_COUNTER8_RESET_MASK 0x100 #define RTL8367C_COUNTER7_RESET_OFFSET 7 #define RTL8367C_COUNTER7_RESET_MASK 0x80 #define RTL8367C_COUNTER6_RESET_OFFSET 6 #define RTL8367C_COUNTER6_RESET_MASK 0x40 #define RTL8367C_COUNTER5_RESET_OFFSET 5 #define RTL8367C_COUNTER5_RESET_MASK 0x20 #define RTL8367C_COUNTER4_RESET_OFFSET 4 #define RTL8367C_COUNTER4_RESET_MASK 0x10 #define RTL8367C_COUNTER3_RESET_OFFSET 3 #define RTL8367C_COUNTER3_RESET_MASK 0x8 #define RTL8367C_COUNTER2_RESET_OFFSET 2 #define RTL8367C_COUNTER2_RESET_MASK 0x4 #define RTL8367C_COUNTER1_RESET_OFFSET 1 #define RTL8367C_COUNTER1_RESET_MASK 0x2 #define RTL8367C_COUNTER0_RESET_OFFSET 0 #define RTL8367C_COUNTER0_RESET_MASK 0x1 #define RTL8367C_REG_MIB_CTRL2 0x1008 #define RTL8367C_COUNTER31_RESET_OFFSET 15 #define RTL8367C_COUNTER31_RESET_MASK 0x8000 #define RTL8367C_COUNTER30_RESET_OFFSET 14 #define RTL8367C_COUNTER30_RESET_MASK 0x4000 #define RTL8367C_COUNTER29_RESET_OFFSET 13 #define RTL8367C_COUNTER29_RESET_MASK 0x2000 #define RTL8367C_COUNTER28_RESET_OFFSET 12 #define RTL8367C_COUNTER28_RESET_MASK 0x1000 #define RTL8367C_COUNTER27_RESET_OFFSET 11 #define RTL8367C_COUNTER27_RESET_MASK 0x800 #define RTL8367C_COUNTER26_RESET_OFFSET 10 #define RTL8367C_COUNTER26_RESET_MASK 0x400 #define RTL8367C_COUNTER25_RESET_OFFSET 9 #define RTL8367C_COUNTER25_RESET_MASK 0x200 #define RTL8367C_COUNTER24_RESET_OFFSET 8 #define RTL8367C_COUNTER24_RESET_MASK 0x100 #define RTL8367C_COUNTER23_RESET_OFFSET 7 #define RTL8367C_COUNTER23_RESET_MASK 0x80 #define RTL8367C_COUNTER22_RESET_OFFSET 6 #define RTL8367C_COUNTER22_RESET_MASK 0x40 #define RTL8367C_COUNTER21_RESET_OFFSET 5 #define RTL8367C_COUNTER21_RESET_MASK 0x20 #define RTL8367C_COUNTER20_RESET_OFFSET 4 #define RTL8367C_COUNTER20_RESET_MASK 0x10 #define RTL8367C_COUNTER19_RESET_OFFSET 3 #define RTL8367C_COUNTER19_RESET_MASK 0x8 #define RTL8367C_COUNTER18_RESET_OFFSET 2 #define RTL8367C_COUNTER18_RESET_MASK 0x4 #define RTL8367C_COUNTER17_RESET_OFFSET 1 #define RTL8367C_COUNTER17_RESET_MASK 0x2 #define RTL8367C_COUNTER16_RESET_OFFSET 0 #define RTL8367C_COUNTER16_RESET_MASK 0x1 #define RTL8367C_REG_MIB_CTRL3 0x1009 #define RTL8367C_COUNTER15_MODE_OFFSET 15 #define RTL8367C_COUNTER15_MODE_MASK 0x8000 #define RTL8367C_COUNTER14_MODE_OFFSET 14 #define RTL8367C_COUNTER14_MODE_MASK 0x4000 #define RTL8367C_COUNTER13_MODE_OFFSET 13 #define RTL8367C_COUNTER13_MODE_MASK 0x2000 #define RTL8367C_COUNTER12_MODE_OFFSET 12 #define RTL8367C_COUNTER12_MODE_MASK 0x1000 #define RTL8367C_COUNTER11_MODE_OFFSET 11 #define RTL8367C_COUNTER11_MODE_MASK 0x800 #define RTL8367C_COUNTER10_MODE_OFFSET 10 #define RTL8367C_COUNTER10_MODE_MASK 0x400 #define RTL8367C_COUNTER9_MODE_OFFSET 9 #define RTL8367C_COUNTER9_MODE_MASK 0x200 #define RTL8367C_COUNTER8_MODE_OFFSET 8 #define RTL8367C_COUNTER8_MODE_MASK 0x100 #define RTL8367C_COUNTER7_MODE_OFFSET 7 #define RTL8367C_COUNTER7_MODE_MASK 0x80 #define RTL8367C_COUNTER6_MODE_OFFSET 6 #define RTL8367C_COUNTER6_MODE_MASK 0x40 #define RTL8367C_COUNTER5_MODE_OFFSET 5 #define RTL8367C_COUNTER5_MODE_MASK 0x20 #define RTL8367C_COUNTER4_MODE_OFFSET 4 #define RTL8367C_COUNTER4_MODE_MASK 0x10 #define RTL8367C_COUNTER3_MODE_OFFSET 3 #define RTL8367C_COUNTER3_MODE_MASK 0x8 #define RTL8367C_COUNTER2_MODE_OFFSET 2 #define RTL8367C_COUNTER2_MODE_MASK 0x4 #define RTL8367C_COUNTER1_MODE_OFFSET 1 #define RTL8367C_COUNTER1_MODE_MASK 0x2 #define RTL8367C_COUNTER0_MODE_OFFSET 0 #define RTL8367C_COUNTER0_MODE_MASK 0x1 #define RTL8367C_REG_MIB_CTRL4 0x100a #define RTL8367C_MIB_USAGE_MODE_OFFSET 8 #define RTL8367C_MIB_USAGE_MODE_MASK 0x100 #define RTL8367C_MIB_TIMER_OFFSET 0 #define RTL8367C_MIB_TIMER_MASK 0xFF #define RTL8367C_REG_MIB_CTRL5 0x100b #define RTL8367C_MIB_CTRL5_COUNTER15_TYPE_OFFSET 15 #define RTL8367C_MIB_CTRL5_COUNTER15_TYPE_MASK 0x8000 #define RTL8367C_MIB_CTRL5_COUNTER14_TYPE_OFFSET 14 #define RTL8367C_MIB_CTRL5_COUNTER14_TYPE_MASK 0x4000 #define RTL8367C_MIB_CTRL5_COUNTER13_TYPE_OFFSET 13 #define RTL8367C_MIB_CTRL5_COUNTER13_TYPE_MASK 0x2000 #define RTL8367C_MIB_CTRL5_COUNTER12_TYPE_OFFSET 12 #define RTL8367C_MIB_CTRL5_COUNTER12_TYPE_MASK 0x1000 #define RTL8367C_MIB_CTRL5_COUNTER11_TYPE_OFFSET 11 #define RTL8367C_MIB_CTRL5_COUNTER11_TYPE_MASK 0x800 #define RTL8367C_MIB_CTRL5_COUNTER10_TYPE_OFFSET 10 #define RTL8367C_MIB_CTRL5_COUNTER10_TYPE_MASK 0x400 #define RTL8367C_MIB_CTRL5_COUNTER9_TYPE_OFFSET 9 #define RTL8367C_MIB_CTRL5_COUNTER9_TYPE_MASK 0x200 #define RTL8367C_MIB_CTRL5_COUNTER8_TYPE_OFFSET 8 #define RTL8367C_MIB_CTRL5_COUNTER8_TYPE_MASK 0x100 #define RTL8367C_MIB_CTRL5_COUNTER7_TYPE_OFFSET 7 #define RTL8367C_MIB_CTRL5_COUNTER7_TYPE_MASK 0x80 #define RTL8367C_MIB_CTRL5_COUNTER6_TYPE_OFFSET 6 #define RTL8367C_MIB_CTRL5_COUNTER6_TYPE_MASK 0x40 #define RTL8367C_MIB_CTRL5_COUNTER5_TYPE_OFFSET 5 #define RTL8367C_MIB_CTRL5_COUNTER5_TYPE_MASK 0x20 #define RTL8367C_MIB_CTRL5_COUNTER4_TYPE_OFFSET 4 #define RTL8367C_MIB_CTRL5_COUNTER4_TYPE_MASK 0x10 #define RTL8367C_MIB_CTRL5_COUNTER3_TYPE_OFFSET 3 #define RTL8367C_MIB_CTRL5_COUNTER3_TYPE_MASK 0x8 #define RTL8367C_MIB_CTRL5_COUNTER2_TYPE_OFFSET 2 #define RTL8367C_MIB_CTRL5_COUNTER2_TYPE_MASK 0x4 #define RTL8367C_MIB_CTRL5_COUNTER1_TYPE_OFFSET 1 #define RTL8367C_MIB_CTRL5_COUNTER1_TYPE_MASK 0x2 #define RTL8367C_MIB_CTRL5_COUNTER0_TYPE_OFFSET 0 #define RTL8367C_MIB_CTRL5_COUNTER0_TYPE_MASK 0x1 /* (16'h1100)intrpt_reg */ #define RTL8367C_REG_INTR_CTRL 0x1100 #define RTL8367C_INTR_CTRL_OFFSET 0 #define RTL8367C_INTR_CTRL_MASK 0x1 #define RTL8367C_REG_INTR_IMR 0x1101 #define RTL8367C_INTR_IMR_SLIENT_START_2_OFFSET 12 #define RTL8367C_INTR_IMR_SLIENT_START_2_MASK 0x1000 #define RTL8367C_INTR_IMR_SLIENT_START_OFFSET 11 #define RTL8367C_INTR_IMR_SLIENT_START_MASK 0x800 #define RTL8367C_INTR_IMR_ACL_ACTION_OFFSET 9 #define RTL8367C_INTR_IMR_ACL_ACTION_MASK 0x200 #define RTL8367C_INTR_IMR_CABLE_DIAG_FIN_OFFSET 8 #define RTL8367C_INTR_IMR_CABLE_DIAG_FIN_MASK 0x100 #define RTL8367C_INTR_IMR_INTERRUPT_8051_OFFSET 7 #define RTL8367C_INTR_IMR_INTERRUPT_8051_MASK 0x80 #define RTL8367C_INTR_IMR_LOOP_DETECTION_OFFSET 6 #define RTL8367C_INTR_IMR_LOOP_DETECTION_MASK 0x40 #define RTL8367C_INTR_IMR_GREEN_TIMER_OFFSET 5 #define RTL8367C_INTR_IMR_GREEN_TIMER_MASK 0x20 #define RTL8367C_INTR_IMR_SPECIAL_CONGEST_OFFSET 4 #define RTL8367C_INTR_IMR_SPECIAL_CONGEST_MASK 0x10 #define RTL8367C_INTR_IMR_SPEED_CHANGE_OFFSET 3 #define RTL8367C_INTR_IMR_SPEED_CHANGE_MASK 0x8 #define RTL8367C_INTR_IMR_LEARN_OVER_OFFSET 2 #define RTL8367C_INTR_IMR_LEARN_OVER_MASK 0x4 #define RTL8367C_INTR_IMR_METER_EXCEEDED_OFFSET 1 #define RTL8367C_INTR_IMR_METER_EXCEEDED_MASK 0x2 #define RTL8367C_INTR_IMR_LINK_CHANGE_OFFSET 0 #define RTL8367C_INTR_IMR_LINK_CHANGE_MASK 0x1 #define RTL8367C_REG_INTR_IMS 0x1102 #define RTL8367C_INTR_IMS_SLIENT_START_2_OFFSET 12 #define RTL8367C_INTR_IMS_SLIENT_START_2_MASK 0x1000 #define RTL8367C_INTR_IMS_SLIENT_START_OFFSET 11 #define RTL8367C_INTR_IMS_SLIENT_START_MASK 0x800 #define RTL8367C_INTR_IMS_ACL_ACTION_OFFSET 9 #define RTL8367C_INTR_IMS_ACL_ACTION_MASK 0x200 #define RTL8367C_INTR_IMS_CABLE_DIAG_FIN_OFFSET 8 #define RTL8367C_INTR_IMS_CABLE_DIAG_FIN_MASK 0x100 #define RTL8367C_INTR_IMS_INTERRUPT_8051_OFFSET 7 #define RTL8367C_INTR_IMS_INTERRUPT_8051_MASK 0x80 #define RTL8367C_INTR_IMS_LOOP_DETECTION_OFFSET 6 #define RTL8367C_INTR_IMS_LOOP_DETECTION_MASK 0x40 #define RTL8367C_INTR_IMS_GREEN_TIMER_OFFSET 5 #define RTL8367C_INTR_IMS_GREEN_TIMER_MASK 0x20 #define RTL8367C_INTR_IMS_SPECIAL_CONGEST_OFFSET 4 #define RTL8367C_INTR_IMS_SPECIAL_CONGEST_MASK 0x10 #define RTL8367C_INTR_IMS_SPEED_CHANGE_OFFSET 3 #define RTL8367C_INTR_IMS_SPEED_CHANGE_MASK 0x8 #define RTL8367C_INTR_IMS_LEARN_OVER_OFFSET 2 #define RTL8367C_INTR_IMS_LEARN_OVER_MASK 0x4 #define RTL8367C_INTR_IMS_METER_EXCEEDED_OFFSET 1 #define RTL8367C_INTR_IMS_METER_EXCEEDED_MASK 0x2 #define RTL8367C_INTR_IMS_LINK_CHANGE_OFFSET 0 #define RTL8367C_INTR_IMS_LINK_CHANGE_MASK 0x1 #define RTL8367C_REG_LEARN_OVER_INDICATOR 0x1103 #define RTL8367C_LEARN_OVER_INDICATOR_OFFSET 0 #define RTL8367C_LEARN_OVER_INDICATOR_MASK 0x7FF #define RTL8367C_REG_SPEED_CHANGE_INDICATOR 0x1104 #define RTL8367C_SPEED_CHANGE_INDICATOR_OFFSET 0 #define RTL8367C_SPEED_CHANGE_INDICATOR_MASK 0x7FF #define RTL8367C_REG_SPECIAL_CONGEST_INDICATOR 0x1105 #define RTL8367C_SPECIAL_CONGEST_INDICATOR_OFFSET 0 #define RTL8367C_SPECIAL_CONGEST_INDICATOR_MASK 0x7FF #define RTL8367C_REG_PORT_LINKDOWN_INDICATOR 0x1106 #define RTL8367C_PORT_LINKDOWN_INDICATOR_OFFSET 0 #define RTL8367C_PORT_LINKDOWN_INDICATOR_MASK 0x7FF #define RTL8367C_REG_PORT_LINKUP_INDICATOR 0x1107 #define RTL8367C_PORT_LINKUP_INDICATOR_OFFSET 0 #define RTL8367C_PORT_LINKUP_INDICATOR_MASK 0x7FF #define RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR 0x1108 #define RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_OFFSET 0 #define RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_MASK 0x1 #define RTL8367C_REG_INTR_IMR_8051 0x1118 #define RTL8367C_INTR_IMR_8051_SLIENT_START_2_OFFSET 13 #define RTL8367C_INTR_IMR_8051_SLIENT_START_2_MASK 0x2000 #define RTL8367C_INTR_IMR_8051_SLIENT_START_OFFSET 12 #define RTL8367C_INTR_IMR_8051_SLIENT_START_MASK 0x1000 #define RTL8367C_INTR_IMR_8051_ACL_ACTION_OFFSET 10 #define RTL8367C_INTR_IMR_8051_ACL_ACTION_MASK 0x400 #define RTL8367C_INTR_IMR_8051_SAMOVING_8051_OFFSET 9 #define RTL8367C_INTR_IMR_8051_SAMOVING_8051_MASK 0x200 #define RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_OFFSET 8 #define RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_MASK 0x100 #define RTL8367C_INTR_IMR_8051_EEELLDP_8051_OFFSET 7 #define RTL8367C_INTR_IMR_8051_EEELLDP_8051_MASK 0x80 #define RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_OFFSET 6 #define RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_MASK 0x40 #define RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_OFFSET 5 #define RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_MASK 0x20 #define RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_OFFSET 4 #define RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_MASK 0x10 #define RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_OFFSET 3 #define RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_MASK 0x8 #define RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_OFFSET 2 #define RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_MASK 0x4 #define RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_OFFSET 1 #define RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_MASK 0x2 #define RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_OFFSET 0 #define RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_MASK 0x1 #define RTL8367C_REG_INTR_IMS_8051 0x1119 #define RTL8367C_INTR_IMS_8051_SLIENT_START_2_OFFSET 13 #define RTL8367C_INTR_IMS_8051_SLIENT_START_2_MASK 0x2000 #define RTL8367C_INTR_IMS_8051_SLIENT_START_OFFSET 12 #define RTL8367C_INTR_IMS_8051_SLIENT_START_MASK 0x1000 #define RTL8367C_INTR_IMS_8051_ACL_ACTION_OFFSET 10 #define RTL8367C_INTR_IMS_8051_ACL_ACTION_MASK 0x400 #define RTL8367C_INTR_IMS_8051_SAMOVING_8051_OFFSET 9 #define RTL8367C_INTR_IMS_8051_SAMOVING_8051_MASK 0x200 #define RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_OFFSET 8 #define RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_MASK 0x100 #define RTL8367C_INTR_IMS_8051_EEELLDP_8051_OFFSET 7 #define RTL8367C_INTR_IMS_8051_EEELLDP_8051_MASK 0x80 #define RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_OFFSET 6 #define RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_MASK 0x40 #define RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_OFFSET 5 #define RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_MASK 0x20 #define RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_OFFSET 4 #define RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_MASK 0x10 #define RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_OFFSET 3 #define RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_MASK 0x8 #define RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_OFFSET 2 #define RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_MASK 0x4 #define RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_OFFSET 1 #define RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_MASK 0x2 #define RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_OFFSET 0 #define RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_MASK 0x1 #define RTL8367C_REG_DW8051_INT_CPU 0x111a #define RTL8367C_DW8051_INT_CPU_OFFSET 0 #define RTL8367C_DW8051_INT_CPU_MASK 0x1 #define RTL8367C_REG_LEARN_OVER_INDICATOR_8051 0x1120 #define RTL8367C_LEARN_OVER_INDICATOR_8051_OFFSET 0 #define RTL8367C_LEARN_OVER_INDICATOR_8051_MASK 0x7FF #define RTL8367C_REG_SPEED_CHANGE_INDICATOR_8051 0x1121 #define RTL8367C_SPEED_CHANGE_INDICATOR_8051_OFFSET 0 #define RTL8367C_SPEED_CHANGE_INDICATOR_8051_MASK 0x7FF #define RTL8367C_REG_SPECIAL_CONGEST_INDICATOR_8051 0x1122 #define RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_OFFSET 0 #define RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_MASK 0x7FF #define RTL8367C_REG_PORT_LINKDOWN_INDICATOR_8051 0x1123 #define RTL8367C_PORT_LINKDOWN_INDICATOR_8051_OFFSET 0 #define RTL8367C_PORT_LINKDOWN_INDICATOR_8051_MASK 0x7FF #define RTL8367C_REG_PORT_LINKUP_INDICATOR_8051 0x1124 #define RTL8367C_PORT_LINKUP_INDICATOR_8051_OFFSET 0 #define RTL8367C_PORT_LINKUP_INDICATOR_8051_MASK 0x7FF #define RTL8367C_REG_DUMMY_1125 0x1125 #define RTL8367C_REG_DUMMY_1126 0x1126 #define RTL8367C_REG_DUMMY_1127 0x1127 #define RTL8367C_REG_DUMMY_1128 0x1128 #define RTL8367C_REG_DUMMY_1129 0x1129 #define RTL8367C_REG_INTR_IMS_BUFFER_RESET 0x112a #define RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 #define RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 #define RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_OFFSET 0 #define RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_MASK 0x1 #define RTL8367C_REG_INTR_IMS_8051_BUFFER_RESET 0x112b #define RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 #define RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 #define RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_OFFSET 0 #define RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_MASK 0x1 #define RTL8367C_REG_GPHY_INTRPT_8051 0x112c #define RTL8367C_IMS_GPHY_8051_H_OFFSET 13 #define RTL8367C_IMS_GPHY_8051_H_MASK 0xE000 #define RTL8367C_IMR_GPHY_8051_H_OFFSET 10 #define RTL8367C_IMR_GPHY_8051_H_MASK 0x1C00 #define RTL8367C_IMS_GPHY_8051_OFFSET 5 #define RTL8367C_IMS_GPHY_8051_MASK 0x3E0 #define RTL8367C_IMR_GPHY_8051_OFFSET 0 #define RTL8367C_IMR_GPHY_8051_MASK 0x1F #define RTL8367C_REG_GPHY_INTRPT 0x112d #define RTL8367C_IMS_GPHY_H_OFFSET 13 #define RTL8367C_IMS_GPHY_H_MASK 0xE000 #define RTL8367C_IMR_GPHY_H_OFFSET 10 #define RTL8367C_IMR_GPHY_H_MASK 0x1C00 #define RTL8367C_IMS_GPHY_OFFSET 5 #define RTL8367C_IMS_GPHY_MASK 0x3E0 #define RTL8367C_IMR_GPHY_OFFSET 0 #define RTL8367C_IMR_GPHY_MASK 0x1F #define RTL8367C_REG_THERMAL_INTRPT 0x112e #define RTL8367C_IMS_TM_HIGH_OFFSET 3 #define RTL8367C_IMS_TM_HIGH_MASK 0x8 #define RTL8367C_IMR_TM_HIGH_OFFSET 2 #define RTL8367C_IMR_TM_HIGH_MASK 0x4 #define RTL8367C_IMS_TM_LOW_OFFSET 1 #define RTL8367C_IMS_TM_LOW_MASK 0x2 #define RTL8367C_IMR_TM_LOW_OFFSET 0 #define RTL8367C_IMR_TM_LOW_MASK 0x1 #define RTL8367C_REG_THERMAL_INTRPT_8051 0x112f #define RTL8367C_IMS_TM_HIGH_8051_OFFSET 3 #define RTL8367C_IMS_TM_HIGH_8051_MASK 0x8 #define RTL8367C_IMR_TM_HIGH_8051_OFFSET 2 #define RTL8367C_IMR_TM_HIGH_8051_MASK 0x4 #define RTL8367C_IMS_TM_LOW_8051_OFFSET 1 #define RTL8367C_IMS_TM_LOW_8051_MASK 0x2 #define RTL8367C_IMR_TM_LOW_8051_OFFSET 0 #define RTL8367C_IMR_TM_LOW_8051_MASK 0x1 #define RTL8367C_REG_SDS_LINK_CHG_INT 0x1130 #define RTL8367C_IMS_SDS_LINK_STS_C7_OFFSET 15 #define RTL8367C_IMS_SDS_LINK_STS_C7_MASK 0x8000 #define RTL8367C_IMS_SDS_LINK_STS_C6_OFFSET 14 #define RTL8367C_IMS_SDS_LINK_STS_C6_MASK 0x4000 #define RTL8367C_IMS_SDS_LINK_STS_C5_OFFSET 13 #define RTL8367C_IMS_SDS_LINK_STS_C5_MASK 0x2000 #define RTL8367C_IMS_SDS_LINK_STS_C4_OFFSET 12 #define RTL8367C_IMS_SDS_LINK_STS_C4_MASK 0x1000 #define RTL8367C_IMS_SDS_LINK_STS_C3_OFFSET 11 #define RTL8367C_IMS_SDS_LINK_STS_C3_MASK 0x800 #define RTL8367C_IMS_SDS_LINK_STS_C2_OFFSET 10 #define RTL8367C_IMS_SDS_LINK_STS_C2_MASK 0x400 #define RTL8367C_IMS_SDS_LINK_STS_C1_OFFSET 9 #define RTL8367C_IMS_SDS_LINK_STS_C1_MASK 0x200 #define RTL8367C_IMS_SDS_LINK_STS_C0_OFFSET 8 #define RTL8367C_IMS_SDS_LINK_STS_C0_MASK 0x100 #define RTL8367C_IMR_SDS_LINK_STS_C7_OFFSET 7 #define RTL8367C_IMR_SDS_LINK_STS_C7_MASK 0x80 #define RTL8367C_IMR_SDS_LINK_STS_C6_OFFSET 6 #define RTL8367C_IMR_SDS_LINK_STS_C6_MASK 0x40 #define RTL8367C_IMR_SDS_LINK_STS_C5_OFFSET 5 #define RTL8367C_IMR_SDS_LINK_STS_C5_MASK 0x20 #define RTL8367C_IMR_SDS_LINK_STS_C4_OFFSET 4 #define RTL8367C_IMR_SDS_LINK_STS_C4_MASK 0x10 #define RTL8367C_IMR_SDS_LINK_STS_C3_OFFSET 3 #define RTL8367C_IMR_SDS_LINK_STS_C3_MASK 0x8 #define RTL8367C_IMR_SDS_LINK_STS_C2_OFFSET 2 #define RTL8367C_IMR_SDS_LINK_STS_C2_MASK 0x4 #define RTL8367C_IMR_SDS_LINK_STS_C1_OFFSET 1 #define RTL8367C_IMR_SDS_LINK_STS_C1_MASK 0x2 #define RTL8367C_IMR_SDS_LINK_STS_C0_OFFSET 0 #define RTL8367C_IMR_SDS_LINK_STS_C0_MASK 0x1 #define RTL8367C_REG_SDS_LINK_CHG_INT_8051 0x1131 #define RTL8367C_IMS_SDS_LINK_STS_C7_8051_OFFSET 15 #define RTL8367C_IMS_SDS_LINK_STS_C7_8051_MASK 0x8000 #define RTL8367C_IMS_SDS_LINK_STS_C6_8051_OFFSET 14 #define RTL8367C_IMS_SDS_LINK_STS_C6_8051_MASK 0x4000 #define RTL8367C_IMS_SDS_LINK_STS_C5_8051_OFFSET 13 #define RTL8367C_IMS_SDS_LINK_STS_C5_8051_MASK 0x2000 #define RTL8367C_IMS_SDS_LINK_STS_C4_8051_OFFSET 12 #define RTL8367C_IMS_SDS_LINK_STS_C4_8051_MASK 0x1000 #define RTL8367C_IMS_SDS_LINK_STS_C3_8051_OFFSET 11 #define RTL8367C_IMS_SDS_LINK_STS_C3_8051_MASK 0x800 #define RTL8367C_IMS_SDS_LINK_STS_C2_8051_OFFSET 10 #define RTL8367C_IMS_SDS_LINK_STS_C2_8051_MASK 0x400 #define RTL8367C_IMS_SDS_LINK_STS_C1_8051_OFFSET 9 #define RTL8367C_IMS_SDS_LINK_STS_C1_8051_MASK 0x200 #define RTL8367C_IMS_SDS_LINK_STS_C0_8051_OFFSET 8 #define RTL8367C_IMS_SDS_LINK_STS_C0_8051_MASK 0x100 #define RTL8367C_IMR_SDS_LINK_STS_C7_8051_OFFSET 7 #define RTL8367C_IMR_SDS_LINK_STS_C7_8051_MASK 0x80 #define RTL8367C_IMR_SDS_LINK_STS_C6_8051_OFFSET 6 #define RTL8367C_IMR_SDS_LINK_STS_C6_8051_MASK 0x40 #define RTL8367C_IMR_SDS_LINK_STS_C5_8051_OFFSET 5 #define RTL8367C_IMR_SDS_LINK_STS_C5_8051_MASK 0x20 #define RTL8367C_IMR_SDS_LINK_STS_C4_8051_OFFSET 4 #define RTL8367C_IMR_SDS_LINK_STS_C4_8051_MASK 0x10 #define RTL8367C_IMR_SDS_LINK_STS_C3_8051_OFFSET 3 #define RTL8367C_IMR_SDS_LINK_STS_C3_8051_MASK 0x8 #define RTL8367C_IMR_SDS_LINK_STS_C2_8051_OFFSET 2 #define RTL8367C_IMR_SDS_LINK_STS_C2_8051_MASK 0x4 #define RTL8367C_IMR_SDS_LINK_STS_C1_8051_OFFSET 1 #define RTL8367C_IMR_SDS_LINK_STS_C1_8051_MASK 0x2 #define RTL8367C_IMR_SDS_LINK_STS_C0_8051_OFFSET 0 #define RTL8367C_IMR_SDS_LINK_STS_C0_8051_MASK 0x1 /* (16'h1200)swcore_reg */ #define RTL8367C_REG_MAX_LENGTH_LIMINT_IPG 0x1200 #define RTL8367C_MAX_LENTH_CTRL_OFFSET 13 #define RTL8367C_MAX_LENTH_CTRL_MASK 0x6000 #define RTL8367C_PAGES_BEFORE_FCDROP_OFFSET 6 #define RTL8367C_PAGES_BEFORE_FCDROP_MASK 0x1FC0 #define RTL8367C_CHECK_MIN_IPG_RXDV_OFFSET 5 #define RTL8367C_CHECK_MIN_IPG_RXDV_MASK 0x20 #define RTL8367C_LIMIT_IPG_CFG_OFFSET 0 #define RTL8367C_LIMIT_IPG_CFG_MASK 0x1F #define RTL8367C_REG_IOL_RXDROP_CFG 0x1201 #define RTL8367C_RX_IOL_MAX_LENGTH_CFG_OFFSET 13 #define RTL8367C_RX_IOL_MAX_LENGTH_CFG_MASK 0x2000 #define RTL8367C_RX_IOL_ERROR_LENGTH_CFG_OFFSET 12 #define RTL8367C_RX_IOL_ERROR_LENGTH_CFG_MASK 0x1000 #define RTL8367C_RX_NODROP_PAUSE_CFG_OFFSET 8 #define RTL8367C_RX_NODROP_PAUSE_CFG_MASK 0x100 #define RTL8367C_RX_DV_CNT_CFG_OFFSET 0 #define RTL8367C_RX_DV_CNT_CFG_MASK 0x3F #define RTL8367C_REG_VS_TPID 0x1202 #define RTL8367C_REG_INBW_BOUND 0x1203 #define RTL8367C_LBOUND_OFFSET 4 #define RTL8367C_LBOUND_MASK 0xF0 #define RTL8367C_HBOUND_OFFSET 0 #define RTL8367C_HBOUND_MASK 0xF #define RTL8367C_REG_CFG_TX_ITFSP_OP 0x1204 #define RTL8367C_MASK_OFFSET 1 #define RTL8367C_MASK_MASK 0x2 #define RTL8367C_OP_OFFSET 0 #define RTL8367C_OP_MASK 0x1 #define RTL8367C_REG_INBW_BOUND2 0x1205 #define RTL8367C_LBOUND2_H_OFFSET 9 #define RTL8367C_LBOUND2_H_MASK 0x200 #define RTL8367C_HBOUND2_H_OFFSET 8 #define RTL8367C_HBOUND2_H_MASK 0x100 #define RTL8367C_LBOUND2_OFFSET 4 #define RTL8367C_LBOUND2_MASK 0xF0 #define RTL8367C_HBOUND2_OFFSET 0 #define RTL8367C_HBOUND2_MASK 0xF #define RTL8367C_REG_CFG_48PASS1_DROP 0x1206 #define RTL8367C_CFG_48PASS1_DROP_OFFSET 0 #define RTL8367C_CFG_48PASS1_DROP_MASK 0x1 #define RTL8367C_REG_CFG_BACKPRESSURE 0x1207 #define RTL8367C_LONGTXE_OFFSET 12 #define RTL8367C_LONGTXE_MASK 0x1000 #define RTL8367C_EN_BYPASS_ERROR_OFFSET 8 #define RTL8367C_EN_BYPASS_ERROR_MASK 0x100 #define RTL8367C_EN_BACKPRESSURE_OFFSET 4 #define RTL8367C_EN_BACKPRESSURE_MASK 0x10 #define RTL8367C_EN_48_PASS_1_OFFSET 0 #define RTL8367C_EN_48_PASS_1_MASK 0x1 #define RTL8367C_REG_CFG_UNHIOL 0x1208 #define RTL8367C_IOL_BACKOFF_OFFSET 12 #define RTL8367C_IOL_BACKOFF_MASK 0x1000 #define RTL8367C_BACKOFF_RANDOM_TIME_OFFSET 8 #define RTL8367C_BACKOFF_RANDOM_TIME_MASK 0x100 #define RTL8367C_DISABLE_BACK_OFF_OFFSET 4 #define RTL8367C_DISABLE_BACK_OFF_MASK 0x10 #define RTL8367C_IPG_COMPENSATION_OFFSET 0 #define RTL8367C_IPG_COMPENSATION_MASK 0x1 #define RTL8367C_REG_SWITCH_MAC0 0x1209 #define RTL8367C_REG_SWITCH_MAC1 0x120a #define RTL8367C_REG_SWITCH_MAC2 0x120b #define RTL8367C_REG_SWITCH_CTRL0 0x120c #define RTL8367C_REMARKING_DSCP_ENABLE_OFFSET 8 #define RTL8367C_REMARKING_DSCP_ENABLE_MASK 0x100 #define RTL8367C_SHORT_IPG_OFFSET 4 #define RTL8367C_SHORT_IPG_MASK 0x10 #define RTL8367C_PAUSE_MAX128_OFFSET 0 #define RTL8367C_PAUSE_MAX128_MASK 0x1 #define RTL8367C_REG_QOS_DSCP_REMARK_CTRL0 0x120d #define RTL8367C_INTPRI1_DSCP_OFFSET 8 #define RTL8367C_INTPRI1_DSCP_MASK 0x3F00 #define RTL8367C_INTPRI0_DSCP_OFFSET 0 #define RTL8367C_INTPRI0_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_CTRL1 0x120e #define RTL8367C_INTPRI3_DSCP_OFFSET 8 #define RTL8367C_INTPRI3_DSCP_MASK 0x3F00 #define RTL8367C_INTPRI2_DSCP_OFFSET 0 #define RTL8367C_INTPRI2_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_CTRL2 0x120f #define RTL8367C_INTPRI5_DSCP_OFFSET 8 #define RTL8367C_INTPRI5_DSCP_MASK 0x3F00 #define RTL8367C_INTPRI4_DSCP_OFFSET 0 #define RTL8367C_INTPRI4_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_DSCP_REMARK_CTRL3 0x1210 #define RTL8367C_INTPRI7_DSCP_OFFSET 8 #define RTL8367C_INTPRI7_DSCP_MASK 0x3F00 #define RTL8367C_INTPRI6_DSCP_OFFSET 0 #define RTL8367C_INTPRI6_DSCP_MASK 0x3F #define RTL8367C_REG_QOS_1Q_REMARK_CTRL0 0x1211 #define RTL8367C_INTPRI3_PRI_OFFSET 12 #define RTL8367C_INTPRI3_PRI_MASK 0x7000 #define RTL8367C_INTPRI2_PRI_OFFSET 8 #define RTL8367C_INTPRI2_PRI_MASK 0x700 #define RTL8367C_INTPRI1_PRI_OFFSET 4 #define RTL8367C_INTPRI1_PRI_MASK 0x70 #define RTL8367C_INTPRI0_PRI_OFFSET 0 #define RTL8367C_INTPRI0_PRI_MASK 0x7 #define RTL8367C_REG_QOS_1Q_REMARK_CTRL1 0x1212 #define RTL8367C_INTPRI7_PRI_OFFSET 12 #define RTL8367C_INTPRI7_PRI_MASK 0x7000 #define RTL8367C_INTPRI6_PRI_OFFSET 8 #define RTL8367C_INTPRI6_PRI_MASK 0x700 #define RTL8367C_INTPRI5_PRI_OFFSET 4 #define RTL8367C_INTPRI5_PRI_MASK 0x70 #define RTL8367C_INTPRI4_PRI_OFFSET 0 #define RTL8367C_INTPRI4_PRI_MASK 0x7 #define RTL8367C_REG_PKTGEN_COMMAND 0x1213 #define RTL8367C_PKTGEN_STOP_OFFSET 8 #define RTL8367C_PKTGEN_STOP_MASK 0x100 #define RTL8367C_PKTGEN_START_OFFSET 4 #define RTL8367C_PKTGEN_START_MASK 0x10 #define RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_OFFSET 0 #define RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_MASK 0x1 #define RTL8367C_REG_SW_DUMMY0 0x1214 #define RTL8367C_SW_DUMMY0_DUMMY_OFFSET 4 #define RTL8367C_SW_DUMMY0_DUMMY_MASK 0xFFF0 #define RTL8367C_EEE_DEFER_TXLPI_OFFSET 3 #define RTL8367C_EEE_DEFER_TXLPI_MASK 0x8 #define RTL8367C_INGRESSBW_BYPASS_EN_OFFSET 2 #define RTL8367C_INGRESSBW_BYPASS_EN_MASK 0x4 #define RTL8367C_CFG_RX_MIN_OFFSET 0 #define RTL8367C_CFG_RX_MIN_MASK 0x3 #define RTL8367C_REG_SW_DUMMY1 0x1215 #define RTL8367C_REG_PKTGEN_PAUSE_TIME 0x1216 #define RTL8367C_REG_SVLAN_UPLINK_PORTMASK 0x1218 #define RTL8367C_SVLAN_UPLINK_PORTMASK_OFFSET 0 #define RTL8367C_SVLAN_UPLINK_PORTMASK_MASK 0x7FF #define RTL8367C_REG_CPU_PORT_MASK 0x1219 #define RTL8367C_CPU_PORT_MASK_OFFSET 0 #define RTL8367C_CPU_PORT_MASK_MASK 0x7FF #define RTL8367C_REG_CPU_CTRL 0x121a #define RTL8367C_CPU_TRAP_PORT_EXT_OFFSET 10 #define RTL8367C_CPU_TRAP_PORT_EXT_MASK 0x400 #define RTL8367C_CPU_TAG_FORMAT_OFFSET 9 #define RTL8367C_CPU_TAG_FORMAT_MASK 0x200 #define RTL8367C_IOL_16DROP_OFFSET 8 #define RTL8367C_IOL_16DROP_MASK 0x100 #define RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET 7 #define RTL8367C_CPU_TAG_RXBYTECOUNT_MASK 0x80 #define RTL8367C_CPU_TAG_POSITION_OFFSET 6 #define RTL8367C_CPU_TAG_POSITION_MASK 0x40 #define RTL8367C_CPU_TRAP_PORT_OFFSET 3 #define RTL8367C_CPU_TRAP_PORT_MASK 0x38 #define RTL8367C_CPU_INSERTMODE_OFFSET 1 #define RTL8367C_CPU_INSERTMODE_MASK 0x6 #define RTL8367C_CPU_EN_OFFSET 0 #define RTL8367C_CPU_EN_MASK 0x1 #define RTL8367C_REG_MIRROR_CTRL 0x121c #define RTL8367C_MIRROR_CTRL_DUMMY_OFFSET 12 #define RTL8367C_MIRROR_CTRL_DUMMY_MASK 0xF000 #define RTL8367C_MIRROR_ISO_OFFSET 11 #define RTL8367C_MIRROR_ISO_MASK 0x800 #define RTL8367C_MIRROR_TX_OFFSET 10 #define RTL8367C_MIRROR_TX_MASK 0x400 #define RTL8367C_MIRROR_RX_OFFSET 9 #define RTL8367C_MIRROR_RX_MASK 0x200 #define RTL8367C_MIRROR_MONITOR_PORT_OFFSET 4 #define RTL8367C_MIRROR_MONITOR_PORT_MASK 0xF0 #define RTL8367C_MIRROR_SOURCE_PORT_OFFSET 0 #define RTL8367C_MIRROR_SOURCE_PORT_MASK 0xF #define RTL8367C_REG_FLOWCTRL_CTRL0 0x121d #define RTL8367C_FLOWCTRL_TYPE_OFFSET 15 #define RTL8367C_FLOWCTRL_TYPE_MASK 0x8000 #define RTL8367C_DROP_ALL_THRESHOLD_OFFSET 5 #define RTL8367C_DROP_ALL_THRESHOLD_MASK 0x7FE0 #define RTL8367C_DROP_ALL_THRESHOLD_MSB_OFFSET 4 #define RTL8367C_DROP_ALL_THRESHOLD_MSB_MASK 0x10 #define RTL8367C_ITFSP_REG_OFFSET 0 #define RTL8367C_ITFSP_REG_MASK 0x7 #define RTL8367C_REG_FLOWCTRL_ALL_ON 0x121e #define RTL8367C_CFG_RLDPACT_OFFSET 12 #define RTL8367C_CFG_RLDPACT_MASK 0x1000 #define RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET 0 #define RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_SYS_ON 0x121f #define RTL8367C_FLOWCTRL_SYS_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_SYS_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_SYS_OFF 0x1220 #define RTL8367C_FLOWCTRL_SYS_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_SYS_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_SHARE_ON 0x1221 #define RTL8367C_FLOWCTRL_SHARE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_SHARE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_SHARE_OFF 0x1222 #define RTL8367C_FLOWCTRL_SHARE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_SHARE_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON 0x1223 #define RTL8367C_FLOWCTRL_FCOFF_SYS_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF 0x1224 #define RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON 0x1225 #define RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF 0x1226 #define RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_ON 0x1227 #define RTL8367C_FLOWCTRL_PORT_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_OFF 0x1228 #define RTL8367C_FLOWCTRL_PORT_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON 0x1229 #define RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF 0x122a #define RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK 0x7FF #define RTL8367C_REG_RRCP_CTRL0 0x122b #define RTL8367C_COL_SEL_OFFSET 14 #define RTL8367C_COL_SEL_MASK 0x4000 #define RTL8367C_CRS_SEL_OFFSET 13 #define RTL8367C_CRS_SEL_MASK 0x2000 #define RTL8367C_RRCP_PBVLAN_EN_OFFSET 11 #define RTL8367C_RRCP_PBVLAN_EN_MASK 0x800 #define RTL8367C_RRCPV3_SECURITY_CRC_OFFSET 10 #define RTL8367C_RRCPV3_SECURITY_CRC_MASK 0x400 #define RTL8367C_RRCPV3_HANDLE_OFFSET 8 #define RTL8367C_RRCPV3_HANDLE_MASK 0x300 #define RTL8367C_RRCPV1_MALFORMED_ACT_OFFSET 5 #define RTL8367C_RRCPV1_MALFORMED_ACT_MASK 0x60 #define RTL8367C_RRCP_VLANLEAKY_OFFSET 4 #define RTL8367C_RRCP_VLANLEAKY_MASK 0x10 #define RTL8367C_RRCPV1_SECURITY_CRC_GET_OFFSET 3 #define RTL8367C_RRCPV1_SECURITY_CRC_GET_MASK 0x8 #define RTL8367C_RRCPV1_SECURITY_CRC_SET_OFFSET 2 #define RTL8367C_RRCPV1_SECURITY_CRC_SET_MASK 0x4 #define RTL8367C_RRCPV1_HANDLE_OFFSET 1 #define RTL8367C_RRCPV1_HANDLE_MASK 0x2 #define RTL8367C_RRCP_ENABLE_OFFSET 0 #define RTL8367C_RRCP_ENABLE_MASK 0x1 #define RTL8367C_REG_RRCP_CTRL1 0x122c #define RTL8367C_RRCP_ADMIN_PMSK_OFFSET 8 #define RTL8367C_RRCP_ADMIN_PMSK_MASK 0xFF00 #define RTL8367C_RRCP_AUTH_PMSK_OFFSET 0 #define RTL8367C_RRCP_AUTH_PMSK_MASK 0xFF #define RTL8367C_REG_RRCP_CTRL2 0x122d #define RTL8367C_RRCPV1_HELLOFWD_TAG_OFFSET 9 #define RTL8367C_RRCPV1_HELLOFWD_TAG_MASK 0x600 #define RTL8367C_RRCP_FWD_TAG_OFFSET 7 #define RTL8367C_RRCP_FWD_TAG_MASK 0x180 #define RTL8367C_RRCPV1_REPLY_TAG_OFFSET 6 #define RTL8367C_RRCPV1_REPLY_TAG_MASK 0x40 #define RTL8367C_RRCPV1_HELLO_COUNT_OFFSET 3 #define RTL8367C_RRCPV1_HELLO_COUNT_MASK 0x38 #define RTL8367C_RRCPV1_HELLO_PEDIOD_OFFSET 0 #define RTL8367C_RRCPV1_HELLO_PEDIOD_MASK 0x3 #define RTL8367C_REG_RRCP_CTRL3 0x122e #define RTL8367C_RRCP_TAG_PRIORITY_OFFSET 13 #define RTL8367C_RRCP_TAG_PRIORITY_MASK 0xE000 #define RTL8367C_RRCP_TAG_VID_OFFSET 0 #define RTL8367C_RRCP_TAG_VID_MASK 0xFFF #define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON 0x122f #define RTL8367C_FLOWCTRL_FCOFF_PORT_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF 0x1230 #define RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON 0x1231 #define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF 0x1232 #define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON 0x1233 #define RTL8367C_FLOWCTRL_JUMBO_SYS_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF 0x1234 #define RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON 0x1235 #define RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF 0x1236 #define RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON 0x1237 #define RTL8367C_FLOWCTRL_JUMBO_PORT_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF 0x1238 #define RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON 0x1239 #define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF 0x123a #define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_OFFSET 0 #define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_JUMBO_SIZE 0x123b #define RTL8367C_JUMBO_MODE_OFFSET 2 #define RTL8367C_JUMBO_MODE_MASK 0x4 #define RTL8367C_JUMBO_SIZE_OFFSET 0 #define RTL8367C_JUMBO_SIZE_MASK 0x3 #define RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_COUNTER 0x124c #define RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER 0x124d #define RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_MAX 0x124e #define RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_MAX 0x124f #define RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT0_PAGE_COUNTER 0x1250 #define RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT1_PAGE_COUNTER 0x1251 #define RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT2_PAGE_COUNTER 0x1252 #define RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT3_PAGE_COUNTER 0x1253 #define RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT4_PAGE_COUNTER 0x1254 #define RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT5_PAGE_COUNTER 0x1255 #define RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT6_PAGE_COUNTER 0x1256 #define RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT7_PAGE_COUNTER 0x1257 #define RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER 0x1258 #define RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER 0x1259 #define RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER 0x125a #define RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER 0x125b #define RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX 0x1260 #define RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT1_PAGE_MAX 0x1261 #define RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT2_PAGE_MAX 0x1262 #define RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT3_PAGE_MAX 0x1263 #define RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT4_PAGE_MAX 0x1264 #define RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT5_PAGE_MAX 0x1265 #define RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT6_PAGE_MAX 0x1266 #define RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT7_PAGE_MAX 0x1267 #define RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PAGE_COUNT_CLEAR 0x1268 #define RTL8367C_DIS_SKIP_FP_OFFSET 1 #define RTL8367C_DIS_SKIP_FP_MASK 0x2 #define RTL8367C_PAGE_COUNT_CLEAR_OFFSET 0 #define RTL8367C_PAGE_COUNT_CLEAR_MASK 0x1 #define RTL8367C_REG_FLOWCTRL_PORT8_PAGE_MAX 0x1269 #define RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT9_PAGE_MAX 0x126a #define RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT10_PAGE_MAX 0x126b #define RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT8_PAGE_COUNTER 0x126c #define RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT9_PAGE_COUNTER 0x126d #define RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_FLOWCTRL_PORT10_PAGE_COUNTER 0x126e #define RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_OFFSET 0 #define RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_MASK 0x7FF #define RTL8367C_REG_RRCP_CTRL1_H 0x126f #define RTL8367C_RRCP_ADMIN_PMSK_P10_8_OFFSET 3 #define RTL8367C_RRCP_ADMIN_PMSK_P10_8_MASK 0x38 #define RTL8367C_RRCP_AUTH_PMSK_P10_8_OFFSET 0 #define RTL8367C_RRCP_AUTH_PMSK_P10_8_MASK 0x7 #define RTL8367C_REG_EMA_CTRL0 0x1270 #define RTL8367C_CFG_DVSE_VIAROM_OFFSET 13 #define RTL8367C_CFG_DVSE_VIAROM_MASK 0x2000 #define RTL8367C_CFG_DVSE_MIBRAM_OFFSET 12 #define RTL8367C_CFG_DVSE_MIBRAM_MASK 0x1000 #define RTL8367C_CFG_DVSE_IROM_OFFSET 11 #define RTL8367C_CFG_DVSE_IROM_MASK 0x800 #define RTL8367C_CFG_DVSE_ERAM_OFFSET 10 #define RTL8367C_CFG_DVSE_ERAM_MASK 0x400 #define RTL8367C_CFG_DVSE_IRAM_OFFSET 9 #define RTL8367C_CFG_DVSE_IRAM_MASK 0x200 #define RTL8367C_CFG_DVSE_NICRAM_OFFSET 8 #define RTL8367C_CFG_DVSE_NICRAM_MASK 0x100 #define RTL8367C_CFG_DVSE_CVLANRAM_OFFSET 7 #define RTL8367C_CFG_DVSE_CVLANRAM_MASK 0x80 #define RTL8367C_CFG_DVSE_ACTRAM_OFFSET 6 #define RTL8367C_CFG_DVSE_ACTRAM_MASK 0x40 #define RTL8367C_CFG_DVSE_INQRAM_OFFSET 5 #define RTL8367C_CFG_DVSE_INQRAM_MASK 0x20 #define RTL8367C_CFG_DVSE_HSARAM_OFFSET 4 #define RTL8367C_CFG_DVSE_HSARAM_MASK 0x10 #define RTL8367C_CFG_DVSE_OUTQRAM_OFFSET 3 #define RTL8367C_CFG_DVSE_OUTQRAM_MASK 0x8 #define RTL8367C_CFG_DVSE_HTRAM_OFFSET 2 #define RTL8367C_CFG_DVSE_HTRAM_MASK 0x4 #define RTL8367C_CFG_DVSE_PBRAM_OFFSET 1 #define RTL8367C_CFG_DVSE_PBRAM_MASK 0x2 #define RTL8367C_CFG_DVSE_L2RAM_OFFSET 0 #define RTL8367C_CFG_DVSE_L2RAM_MASK 0x1 #define RTL8367C_REG_EMA_CTRL1 0x1271 #define RTL8367C_CFG_DVS_OUTQRAM_OFFSET 12 #define RTL8367C_CFG_DVS_OUTQRAM_MASK 0xF000 #define RTL8367C_CFG_DVS_HTRAM_OFFSET 8 #define RTL8367C_CFG_DVS_HTRAM_MASK 0x700 #define RTL8367C_CFG_DVS_PBRAM_OFFSET 4 #define RTL8367C_CFG_DVS_PBRAM_MASK 0xF0 #define RTL8367C_CFG_DVS_L2RAM_OFFSET 0 #define RTL8367C_CFG_DVS_L2RAM_MASK 0xF #define RTL8367C_REG_EMA_CTRL2 0x1272 #define RTL8367C_CFG_DVS_CVLANRAM_OFFSET 12 #define RTL8367C_CFG_DVS_CVLANRAM_MASK 0xF000 #define RTL8367C_CFG_DVS_ACTRAM_OFFSET 8 #define RTL8367C_CFG_DVS_ACTRAM_MASK 0xF00 #define RTL8367C_CFG_DVS_INQRAM_OFFSET 4 #define RTL8367C_CFG_DVS_INQRAM_MASK 0xF0 #define RTL8367C_CFG_DVS_HSARAM_OFFSET 0 #define RTL8367C_CFG_DVS_HSARAM_MASK 0xF #define RTL8367C_REG_EMA_CTRL3 0x1273 #define RTL8367C_CFG_DVS_IROM_OFFSET 12 #define RTL8367C_CFG_DVS_IROM_MASK 0xF000 #define RTL8367C_CFG_DVS_ERAM_OFFSET 8 #define RTL8367C_CFG_DVS_ERAM_MASK 0xF00 #define RTL8367C_CFG_DVS_IRAM_OFFSET 4 #define RTL8367C_CFG_DVS_IRAM_MASK 0xF0 #define RTL8367C_CFG_DVS_NICRAM_OFFSET 0 #define RTL8367C_CFG_DVS_NICRAM_MASK 0xF #define RTL8367C_REG_EMA_CTRL4 0x1274 #define RTL8367C_CFG_DVS_VIAROM_OFFSET 4 #define RTL8367C_CFG_DVS_VIAROM_MASK 0xF0 #define RTL8367C_CFG_DVS_MIBRAM_OFFSET 0 #define RTL8367C_CFG_DVS_MIBRAM_MASK 0xF #define RTL8367C_REG_DIAG_MODE 0x1275 #define RTL8367C_DIAG_MODE_OFFSET 0 #define RTL8367C_DIAG_MODE_MASK 0x1F #define RTL8367C_REG_BIST_MODE 0x1276 #define RTL8367C_REG_STS_BIST_DONE 0x1277 #define RTL8367C_REG_STS_BIST_RLT0 0x1278 #define RTL8367C_STS_BIST_RLT0_OFFSET 0 #define RTL8367C_STS_BIST_RLT0_MASK 0x1 #define RTL8367C_REG_STS_BIST_RLT1 0x1279 #define RTL8367C_REG_STS_BIST_RLT2 0x127a #define RTL8367C_REG_STS_BIST_RLT3 0x127b #define RTL8367C_STS_BIST_RLT3_OFFSET 0 #define RTL8367C_STS_BIST_RLT3_MASK 0x3FF #define RTL8367C_REG_STS_BIST_RLT4 0x127c #define RTL8367C_STS_BIST_RLT4_OFFSET 0 #define RTL8367C_STS_BIST_RLT4_MASK 0x7 #define RTL8367C_REG_VIAROM_MISR 0x127d #define RTL8367C_REG_DRF_BIST_MODE 0x1280 #define RTL8367C_DRF_TCAMDEL_OFFSET 15 #define RTL8367C_DRF_TCAMDEL_MASK 0x8000 #define RTL8367C_CFG_DRF_BIST_MODE_OFFSET 0 #define RTL8367C_CFG_DRF_BIST_MODE_MASK 0x7FFF #define RTL8367C_REG_STS_DRF_BIST 0x1281 #define RTL8367C_STS_DRF_BIST_OFFSET 0 #define RTL8367C_STS_DRF_BIST_MASK 0x7FFF #define RTL8367C_REG_STS_DRF_BIST_RLT0 0x1282 #define RTL8367C_STS_DRF_BIST_RLT0_OFFSET 0 #define RTL8367C_STS_DRF_BIST_RLT0_MASK 0x1 #define RTL8367C_REG_STS_DRF_BIST_RLT1 0x1283 #define RTL8367C_REG_STS_DRF_BIST_RLT2 0x1284 #define RTL8367C_REG_STS_DRF_BIST_RLT3 0x1285 #define RTL8367C_STS_DRF_BIST_RLT3_OFFSET 0 #define RTL8367C_STS_DRF_BIST_RLT3_MASK 0x3FF #define RTL8367C_REG_STS_DRF_BIST_RLT4 0x1286 #define RTL8367C_STS_DRF_BIST_RLT4_OFFSET 0 #define RTL8367C_STS_DRF_BIST_RLT4_MASK 0x7FFF #define RTL8367C_REG_RAM_DRF_CTRL 0x1289 #define RTL8367C_RAM_DRF_CTRL_OFFSET 0 #define RTL8367C_RAM_DRF_CTRL_MASK 0x1 #define RTL8367C_REG_MIB_RMON_LEN_CTRL 0x128a #define RTL8367C_RX_LENGTH_CTRL_OFFSET 1 #define RTL8367C_RX_LENGTH_CTRL_MASK 0x2 #define RTL8367C_TX_LENGTH_CTRL_OFFSET 0 #define RTL8367C_TX_LENGTH_CTRL_MASK 0x1 #define RTL8367C_REG_COND0_BISR_OUT0 0x1290 #define RTL8367C_REG_COND0_BISR_OUT1 0x1291 #define RTL8367C_REG_COND0_BISR_OUT2 0x1292 #define RTL8367C_REG_COND0_BISR_OUT3 0x1293 #define RTL8367C_REG_COND0_BISR_OUT4 0x1294 #define RTL8367C_COND0_BISR_OUT4_OFFSET 0 #define RTL8367C_COND0_BISR_OUT4_MASK 0x3F #define RTL8367C_REG_COND0_BISR_OUT5 0x1295 #define RTL8367C_COND0_BISR_OUT5_OFFSET 0 #define RTL8367C_COND0_BISR_OUT5_MASK 0x7 #define RTL8367C_REG_CHG_DUPLEX_CFG 0x1296 #define RTL8367C_CHG_COL_CNT_PORT_OFFSET 13 #define RTL8367C_CHG_COL_CNT_PORT_MASK 0xE000 #define RTL8367C_CHG_COL_CNT_OFFSET 8 #define RTL8367C_CHG_COL_CNT_MASK 0x1F00 #define RTL8367C_CFG_CHG_DUP_EN_OFFSET 7 #define RTL8367C_CFG_CHG_DUP_EN_MASK 0x80 #define RTL8367C_CFG_CHG_DUP_THR_OFFSET 2 #define RTL8367C_CFG_CHG_DUP_THR_MASK 0x7C #define RTL8367C_CFG_CHG_DUP_CONGEST_OFFSET 1 #define RTL8367C_CFG_CHG_DUP_CONGEST_MASK 0x2 #define RTL8367C_CFG_CHG_DUP_REF_OFFSET 0 #define RTL8367C_CFG_CHG_DUP_REF_MASK 0x1 #define RTL8367C_REG_COND0_BIST_PASS 0x1297 #define RTL8367C_COND0_DRF_BIST_NOFAIL_OFFSET 1 #define RTL8367C_COND0_DRF_BIST_NOFAIL_MASK 0x2 #define RTL8367C_COND0_BIST_NOFAIL_OFFSET 0 #define RTL8367C_COND0_BIST_NOFAIL_MASK 0x1 #define RTL8367C_REG_COND1_BISR_OUT0 0x1298 #define RTL8367C_REG_COND1_BISR_OUT1 0x1299 #define RTL8367C_REG_COND1_BISR_OUT2 0x129a #define RTL8367C_REG_COND1_BISR_OUT3 0x129b #define RTL8367C_REG_COND1_BISR_OUT4 0x129c #define RTL8367C_COND1_BISR_OUT4_OFFSET 0 #define RTL8367C_COND1_BISR_OUT4_MASK 0x3F #define RTL8367C_REG_COND1_BISR_OUT5 0x129d #define RTL8367C_COND1_BISR_OUT5_OFFSET 0 #define RTL8367C_COND1_BISR_OUT5_MASK 0x7 #define RTL8367C_REG_COND1_BIST_PASS 0x129f #define RTL8367C_COND1_DRF_BIST_NOFAIL_OFFSET 1 #define RTL8367C_COND1_DRF_BIST_NOFAIL_MASK 0x2 #define RTL8367C_COND1_BIST_NOFAIL_OFFSET 0 #define RTL8367C_COND1_BIST_NOFAIL_MASK 0x1 #define RTL8367C_REG_EEE_TX_THR_Giga_500M 0x12a0 #define RTL8367C_REG_EEE_TX_THR_FE 0x12a1 #define RTL8367C_REG_EEE_MISC 0x12a3 #define RTL8367C_EEE_REQ_SET1_OFFSET 13 #define RTL8367C_EEE_REQ_SET1_MASK 0x2000 #define RTL8367C_EEE_REQ_SET0_OFFSET 12 #define RTL8367C_EEE_REQ_SET0_MASK 0x1000 #define RTL8367C_EEE_WAKE_SET1_OFFSET 9 #define RTL8367C_EEE_WAKE_SET1_MASK 0x200 #define RTL8367C_EEE_Wake_SET0_OFFSET 8 #define RTL8367C_EEE_Wake_SET0_MASK 0x100 #define RTL8367C_EEE_TU_GIGA_500M_OFFSET 4 #define RTL8367C_EEE_TU_GIGA_500M_MASK 0x30 #define RTL8367C_EEE_TU_100M_OFFSET 2 #define RTL8367C_EEE_TU_100M_MASK 0xC #define RTL8367C_REG_EEE_GIGA_CTRL0 0x12a4 #define RTL8367C_EEE_TW_GIGA_OFFSET 8 #define RTL8367C_EEE_TW_GIGA_MASK 0xFF00 #define RTL8367C_EEE_TR_GIGA_500M_OFFSET 0 #define RTL8367C_EEE_TR_GIGA_500M_MASK 0xFF #define RTL8367C_REG_EEE_GIGA_CTRL1 0x12a5 #define RTL8367C_EEE_TD_GIGA_500M_OFFSET 8 #define RTL8367C_EEE_TD_GIGA_500M_MASK 0xFF00 #define RTL8367C_EEE_TP_GIGA_OFFSET 0 #define RTL8367C_EEE_TP_GIGA_MASK 0xFF #define RTL8367C_REG_EEE_100M_CTRL0 0x12a6 #define RTL8367C_EEE_TW_100M_OFFSET 8 #define RTL8367C_EEE_TW_100M_MASK 0xFF00 #define RTL8367C_EEE_TR_100M_OFFSET 0 #define RTL8367C_EEE_TR_100M_MASK 0xFF #define RTL8367C_REG_EEE_100M_CTRL1 0x12a7 #define RTL8367C_EEE_TD_100M_OFFSET 8 #define RTL8367C_EEE_TD_100M_MASK 0xFF00 #define RTL8367C_EEE_TP_100M_OFFSET 0 #define RTL8367C_EEE_TP_100M_MASK 0xFF #define RTL8367C_REG_RX_FC_REG 0x12aa #define RTL8367C_EN_EEE_HALF_DUP_OFFSET 8 #define RTL8367C_EN_EEE_HALF_DUP_MASK 0x100 #define RTL8367C_RX_PGCNT_OFFSET 0 #define RTL8367C_RX_PGCNT_MASK 0xFF #define RTL8367C_REG_MAX_FIFO_SIZE 0x12af #define RTL8367C_MAX_FIFO_SIZE_OFFSET 0 #define RTL8367C_MAX_FIFO_SIZE_MASK 0xF #define RTL8367C_REG_EEEP_RX_RATE_GIGA 0x12b0 #define RTL8367C_REG_EEEP_RX_RATE_100M 0x12b1 #define RTL8367C_REG_DUMMY_REG_12_2 0x12b2 #define RTL8367C_REG_EEEP_TX_RATE_GIGA 0x12b3 #define RTL8367C_REG_EEEP_TX_RATE_100M 0x12b4 #define RTL8367C_REG_DUMMY_REG_12_3 0x12b5 #define RTL8367C_REG_EEEP_GIGA_CTRL0 0x12b6 #define RTL8367C_EEEP_TR_GIGA_OFFSET 8 #define RTL8367C_EEEP_TR_GIGA_MASK 0xFF00 #define RTL8367C_EEEP_RW_GIGA_MST_OFFSET 0 #define RTL8367C_EEEP_RW_GIGA_MST_MASK 0xFF #define RTL8367C_REG_EEEP_GIGA_CTRL1 0x12b7 #define RTL8367C_EEEP_TW_GIGA_OFFSET 8 #define RTL8367C_EEEP_TW_GIGA_MASK 0xFF00 #define RTL8367C_EEEP_TP_GIGA_OFFSET 0 #define RTL8367C_EEEP_TP_GIGA_MASK 0xFF #define RTL8367C_REG_EEEP_GIGA_CTRL2 0x12b8 #define RTL8367C_EEEP_TXEN_GIGA_OFFSET 12 #define RTL8367C_EEEP_TXEN_GIGA_MASK 0x1000 #define RTL8367C_EEEP_TU_GIGA_OFFSET 8 #define RTL8367C_EEEP_TU_GIGA_MASK 0x300 #define RTL8367C_EEEP_TS_GIGA_OFFSET 0 #define RTL8367C_EEEP_TS_GIGA_MASK 0xFF #define RTL8367C_REG_EEEP_100M_CTRL0 0x12b9 #define RTL8367C_EEEP_TR_100M_OFFSET 8 #define RTL8367C_EEEP_TR_100M_MASK 0xFF00 #define RTL8367C_EEEP_RW_100M_OFFSET 0 #define RTL8367C_EEEP_RW_100M_MASK 0xFF #define RTL8367C_REG_EEEP_100M_CTRL1 0x12ba #define RTL8367C_EEEP_TW_100M_OFFSET 8 #define RTL8367C_EEEP_TW_100M_MASK 0xFF00 #define RTL8367C_EEEP_TP_100M_OFFSET 0 #define RTL8367C_EEEP_TP_100M_MASK 0xFF #define RTL8367C_REG_EEEP_100M_CTRL2 0x12bb #define RTL8367C_EEEP_TXEN_100M_OFFSET 12 #define RTL8367C_EEEP_TXEN_100M_MASK 0x1000 #define RTL8367C_EEEP_TU_100M_OFFSET 8 #define RTL8367C_EEEP_TU_100M_MASK 0x300 #define RTL8367C_EEEP_TS_100M_OFFSET 0 #define RTL8367C_EEEP_TS_100M_MASK 0xFF #define RTL8367C_REG_EEEP_CTRL0 0x12bc #define RTL8367C_EEEP_CTRL0_DUMMY_OFFSET 8 #define RTL8367C_EEEP_CTRL0_DUMMY_MASK 0xFF00 #define RTL8367C_EEEP_SLEEP_STEP_OFFSET 0 #define RTL8367C_EEEP_SLEEP_STEP_MASK 0xFF #define RTL8367C_REG_EEEP_CTRL1 0x12bd #define RTL8367C_EEEP_TXR_GIGA_OFFSET 8 #define RTL8367C_EEEP_TXR_GIGA_MASK 0xFF00 #define RTL8367C_EEEP_TXR_100M_OFFSET 0 #define RTL8367C_EEEP_TXR_100M_MASK 0xFF #define RTL8367C_REG_BACK_PRESSURE_IPG 0x12be #define RTL8367C_BACK_PRESSURE_IPG_OFFSET 0 #define RTL8367C_BACK_PRESSURE_IPG_MASK 0x3 #define RTL8367C_REG_TX_ESD_LEVEL 0x12bf #define RTL8367C_TX_ESD_LEVEL_MODE_OFFSET 8 #define RTL8367C_TX_ESD_LEVEL_MODE_MASK 0x100 #define RTL8367C_LEVEL_OFFSET 0 #define RTL8367C_LEVEL_MASK 0xFF #define RTL8367C_REG_RRCP_CTRL4 0x12e0 #define RTL8367C_REG_RRCP_CTRL5 0x12e1 #define RTL8367C_REG_RRCP_CTRL6 0x12e2 #define RTL8367C_REG_RRCP_CTRL7 0x12e3 #define RTL8367C_REG_RRCP_CTRL8 0x12e4 #define RTL8367C_REG_RRCP_CTRL9 0x12e5 #define RTL8367C_REG_RRCP_CTRL10 0x12e6 #define RTL8367C_REG_FIELD_SELECTOR0 0x12e7 #define RTL8367C_FIELD_SELECTOR0_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR0_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR0_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR0_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR1 0x12e8 #define RTL8367C_FIELD_SELECTOR1_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR1_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR1_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR1_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR2 0x12e9 #define RTL8367C_FIELD_SELECTOR2_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR2_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR2_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR2_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR3 0x12ea #define RTL8367C_FIELD_SELECTOR3_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR3_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR3_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR3_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR4 0x12eb #define RTL8367C_FIELD_SELECTOR4_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR4_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR4_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR4_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR5 0x12ec #define RTL8367C_FIELD_SELECTOR5_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR5_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR5_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR5_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR6 0x12ed #define RTL8367C_FIELD_SELECTOR6_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR6_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR6_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR6_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR7 0x12ee #define RTL8367C_FIELD_SELECTOR7_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR7_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR7_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR7_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR8 0x12ef #define RTL8367C_FIELD_SELECTOR8_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR8_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR8_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR8_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR9 0x12f0 #define RTL8367C_FIELD_SELECTOR9_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR9_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR9_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR9_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR10 0x12f1 #define RTL8367C_FIELD_SELECTOR10_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR10_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR10_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR10_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR11 0x12f2 #define RTL8367C_FIELD_SELECTOR11_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR11_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR11_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR11_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR12 0x12f3 #define RTL8367C_FIELD_SELECTOR12_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR12_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR12_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR12_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR13 0x12f4 #define RTL8367C_FIELD_SELECTOR13_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR13_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR13_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR13_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR14 0x12f5 #define RTL8367C_FIELD_SELECTOR14_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR14_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR14_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR14_OFFSET_MASK 0xFF #define RTL8367C_REG_FIELD_SELECTOR15 0x12f6 #define RTL8367C_FIELD_SELECTOR15_FORMAT_OFFSET 8 #define RTL8367C_FIELD_SELECTOR15_FORMAT_MASK 0x700 #define RTL8367C_FIELD_SELECTOR15_OFFSET_OFFSET 0 #define RTL8367C_FIELD_SELECTOR15_OFFSET_MASK 0xFF #define RTL8367C_REG_HWPKT_GEN_MISC_H 0x12f7 #define RTL8367C_PKT_GEN_SUSPEND_P10_8_OFFSET 3 #define RTL8367C_PKT_GEN_SUSPEND_P10_8_MASK 0x38 #define RTL8367C_PKT_GEN_STATUS_P10_8_OFFSET 0 #define RTL8367C_PKT_GEN_STATUS_P10_8_MASK 0x7 #define RTL8367C_REG_MIRROR_SRC_PMSK 0x12fb #define RTL8367C_MIRROR_SRC_PMSK_OFFSET 0 #define RTL8367C_MIRROR_SRC_PMSK_MASK 0x7FF #define RTL8367C_REG_EEE_BURSTSIZE 0x12fc #define RTL8367C_REG_EEE_IFG_CFG 0x12fd #define RTL8367C_EEE_IFG_CFG_OFFSET 0 #define RTL8367C_EEE_IFG_CFG_MASK 0x1 #define RTL8367C_REG_FPGA_VER_MAC 0x12fe #define RTL8367C_REG_HWPKT_GEN_MISC 0x12ff #define RTL8367C_PKT_GEN_SUSPEND_OFFSET 8 #define RTL8367C_PKT_GEN_SUSPEND_MASK 0xFF00 #define RTL8367C_PKT_GEN_STATUS_OFFSET 0 #define RTL8367C_PKT_GEN_STATUS_MASK 0xFF /* (16'h1300)chip_reg */ #define RTL8367C_REG_CHIP_NUMBER 0x1300 #define RTL8367C_REG_CHIP_VER 0x1301 #define RTL8367C_VERID_OFFSET 12 #define RTL8367C_VERID_MASK 0xF000 #define RTL8367C_MCID_OFFSET 8 #define RTL8367C_MCID_MASK 0xF00 #define RTL8367C_MODEL_ID_OFFSET 4 #define RTL8367C_MODEL_ID_MASK 0xF0 #define RTL8367C_AFE_VERSION_OFFSET 0 #define RTL8367C_AFE_VERSION_MASK 0x1 #define RTL8367C_REG_CHIP_DEBUG0 0x1303 #define RTL8367C_SEL33_EXT2_OFFSET 10 #define RTL8367C_SEL33_EXT2_MASK 0x400 #define RTL8367C_SEL33_EXT1_OFFSET 9 #define RTL8367C_SEL33_EXT1_MASK 0x200 #define RTL8367C_SEL33_EXT0_OFFSET 8 #define RTL8367C_SEL33_EXT0_MASK 0x100 #define RTL8367C_DRI_OTHER_OFFSET 7 #define RTL8367C_DRI_OTHER_MASK 0x80 #define RTL8367C_DRI_EXT1_RG_OFFSET 6 #define RTL8367C_DRI_EXT1_RG_MASK 0x40 #define RTL8367C_DRI_EXT0_RG_OFFSET 5 #define RTL8367C_DRI_EXT0_RG_MASK 0x20 #define RTL8367C_DRI_EXT1_OFFSET 4 #define RTL8367C_DRI_EXT1_MASK 0x10 #define RTL8367C_DRI_EXT0_OFFSET 3 #define RTL8367C_DRI_EXT0_MASK 0x8 #define RTL8367C_SLR_OTHER_OFFSET 2 #define RTL8367C_SLR_OTHER_MASK 0x4 #define RTL8367C_SLR_EXT1_OFFSET 1 #define RTL8367C_SLR_EXT1_MASK 0x2 #define RTL8367C_SLR_EXT0_OFFSET 0 #define RTL8367C_SLR_EXT0_MASK 0x1 #define RTL8367C_REG_CHIP_DEBUG1 0x1304 #define RTL8367C_RG1_DN_OFFSET 12 #define RTL8367C_RG1_DN_MASK 0x7000 #define RTL8367C_RG1_DP_OFFSET 8 #define RTL8367C_RG1_DP_MASK 0x700 #define RTL8367C_RG0_DN_OFFSET 4 #define RTL8367C_RG0_DN_MASK 0x70 #define RTL8367C_RG0_DP_OFFSET 0 #define RTL8367C_RG0_DP_MASK 0x7 #define RTL8367C_REG_DIGITAL_INTERFACE_SELECT 0x1305 #define RTL8367C_ORG_COL_OFFSET 15 #define RTL8367C_ORG_COL_MASK 0x8000 #define RTL8367C_ORG_CRS_OFFSET 14 #define RTL8367C_ORG_CRS_MASK 0x4000 #define RTL8367C_SKIP_MII_1_RXER_OFFSET 13 #define RTL8367C_SKIP_MII_1_RXER_MASK 0x2000 #define RTL8367C_SKIP_MII_0_RXER_OFFSET 12 #define RTL8367C_SKIP_MII_0_RXER_MASK 0x1000 #define RTL8367C_SELECT_GMII_1_OFFSET 4 #define RTL8367C_SELECT_GMII_1_MASK 0xF0 #define RTL8367C_SELECT_GMII_0_OFFSET 0 #define RTL8367C_SELECT_GMII_0_MASK 0xF #define RTL8367C_REG_EXT0_RGMXF 0x1306 #define RTL8367C_EXT0_RGTX_INV_OFFSET 6 #define RTL8367C_EXT0_RGTX_INV_MASK 0x40 #define RTL8367C_EXT0_RGRX_INV_OFFSET 5 #define RTL8367C_EXT0_RGRX_INV_MASK 0x20 #define RTL8367C_EXT0_RGMXF_OFFSET 0 #define RTL8367C_EXT0_RGMXF_MASK 0x1F #define RTL8367C_REG_EXT1_RGMXF 0x1307 #define RTL8367C_EXT1_RGTX_INV_OFFSET 6 #define RTL8367C_EXT1_RGTX_INV_MASK 0x40 #define RTL8367C_EXT1_RGRX_INV_OFFSET 5 #define RTL8367C_EXT1_RGRX_INV_MASK 0x20 #define RTL8367C_EXT1_RGMXF_OFFSET 0 #define RTL8367C_EXT1_RGMXF_MASK 0x1F #define RTL8367C_REG_BISR_CTRL 0x1308 #define RTL8367C_BISR_CTRL_OFFSET 0 #define RTL8367C_BISR_CTRL_MASK 0x7 #define RTL8367C_REG_SLF_IF 0x1309 #define RTL8367C_LINK_DOWN_CLR_FIFO_OFFSET 7 #define RTL8367C_LINK_DOWN_CLR_FIFO_MASK 0x80 #define RTL8367C_LOOPBACK_OFFSET 6 #define RTL8367C_LOOPBACK_MASK 0x40 #define RTL8367C_WATER_LEVEL_OFFSET 4 #define RTL8367C_WATER_LEVEL_MASK 0x30 #define RTL8367C_SLF_IF_OFFSET 0 #define RTL8367C_SLF_IF_MASK 0x3 #define RTL8367C_REG_I2C_CLOCK_DIV 0x130a #define RTL8367C_I2C_CLOCK_DIV_OFFSET 0 #define RTL8367C_I2C_CLOCK_DIV_MASK 0x3FF #define RTL8367C_REG_MDX_MDC_DIV 0x130b #define RTL8367C_MDX_MDC_DIV_OFFSET 0 #define RTL8367C_MDX_MDC_DIV_MASK 0x3FF #define RTL8367C_REG_MISCELLANEOUS_CONFIGURE0 0x130c #define RTL8367C_ADCCKI_FROM_PAD_OFFSET 14 #define RTL8367C_ADCCKI_FROM_PAD_MASK 0x4000 #define RTL8367C_ADCCKI_EN_OFFSET 13 #define RTL8367C_ADCCKI_EN_MASK 0x2000 #define RTL8367C_FLASH_ENABLE_OFFSET 12 #define RTL8367C_FLASH_ENABLE_MASK 0x1000 #define RTL8367C_EEE_ENABLE_OFFSET 11 #define RTL8367C_EEE_ENABLE_MASK 0x800 #define RTL8367C_NIC_ENABLE_OFFSET 10 #define RTL8367C_NIC_ENABLE_MASK 0x400 #define RTL8367C_FT_ENABLE_OFFSET 9 #define RTL8367C_FT_ENABLE_MASK 0x200 #define RTL8367C_OLT_ENABLE_OFFSET 8 #define RTL8367C_OLT_ENABLE_MASK 0x100 #define RTL8367C_RTCT_EN_OFFSET 7 #define RTL8367C_RTCT_EN_MASK 0x80 #define RTL8367C_PON_LIGHT_EN_OFFSET 6 #define RTL8367C_PON_LIGHT_EN_MASK 0x40 #define RTL8367C_DW8051_EN_OFFSET 5 #define RTL8367C_DW8051_EN_MASK 0x20 #define RTL8367C_AUTOLOAD_EN_OFFSET 4 #define RTL8367C_AUTOLOAD_EN_MASK 0x10 #define RTL8367C_NRESTORE_EN_OFFSET 3 #define RTL8367C_NRESTORE_EN_MASK 0x8 #define RTL8367C_DIS_PON_TABLE_INIT_OFFSET 2 #define RTL8367C_DIS_PON_TABLE_INIT_MASK 0x4 #define RTL8367C_DIS_PON_BIST_OFFSET 1 #define RTL8367C_DIS_PON_BIST_MASK 0x2 #define RTL8367C_EFUSE_EN_OFFSET 0 #define RTL8367C_EFUSE_EN_MASK 0x1 #define RTL8367C_REG_MISCELLANEOUS_CONFIGURE1 0x130d #define RTL8367C_EEPROM_DEV_ADR_OFFSET 8 #define RTL8367C_EEPROM_DEV_ADR_MASK 0x7F00 #define RTL8367C_EEPROM_MSB_OFFSET 7 #define RTL8367C_EEPROM_MSB_MASK 0x80 #define RTL8367C_EEPROM_ADDRESS_16B_OFFSET 6 #define RTL8367C_EEPROM_ADDRESS_16B_MASK 0x40 #define RTL8367C_EEPROM_DWONLOAD_COMPLETE_OFFSET 3 #define RTL8367C_EEPROM_DWONLOAD_COMPLETE_MASK 0x8 #define RTL8367C_SPI_SLAVE_EN_OFFSET 2 #define RTL8367C_SPI_SLAVE_EN_MASK 0x4 #define RTL8367C_SMI_SEL_OFFSET 0 #define RTL8367C_SMI_SEL_MASK 0x3 #define RTL8367C_REG_PHY_AD 0x130f #define RTL8367C_EN_PHY_MAX_POWER_OFFSET 14 #define RTL8367C_EN_PHY_MAX_POWER_MASK 0x4000 #define RTL8367C_EN_PHY_SEL_DEG_OFFSET 13 #define RTL8367C_EN_PHY_SEL_DEG_MASK 0x2000 #define RTL8367C_EXTPHY_AD_OFFSET 8 #define RTL8367C_EXTPHY_AD_MASK 0x1F00 #define RTL8367C_EN_PHY_LOW_POWER_MODE_OFFSET 7 #define RTL8367C_EN_PHY_LOW_POWER_MODE_MASK 0x80 #define RTL8367C_EN_PHY_GREEN_OFFSET 6 #define RTL8367C_EN_PHY_GREEN_MASK 0x40 #define RTL8367C_PDNPHY_OFFSET 5 #define RTL8367C_PDNPHY_MASK 0x20 #define RTL8367C_INTPHY_AD_OFFSET 0 #define RTL8367C_INTPHY_AD_MASK 0x1F #define RTL8367C_REG_DIGITAL_INTERFACE0_FORCE 0x1310 #define RTL8367C_GMII_0_FORCE_OFFSET 12 #define RTL8367C_GMII_0_FORCE_MASK 0x1000 #define RTL8367C_RGMII_0_FORCE_OFFSET 0 #define RTL8367C_RGMII_0_FORCE_MASK 0xFFF #define RTL8367C_REG_DIGITAL_INTERFACE1_FORCE 0x1311 #define RTL8367C_GMII_1_FORCE_OFFSET 12 #define RTL8367C_GMII_1_FORCE_MASK 0x1000 #define RTL8367C_RGMII_1_FORCE_OFFSET 0 #define RTL8367C_RGMII_1_FORCE_MASK 0xFFF #define RTL8367C_REG_MAC0_FORCE_SELECT 0x1312 #define RTL8367C_EN_MAC0_FORCE_OFFSET 12 #define RTL8367C_EN_MAC0_FORCE_MASK 0x1000 #define RTL8367C_MAC0_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC0_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC1_FORCE_SELECT 0x1313 #define RTL8367C_EN_MAC1_FORCE_OFFSET 12 #define RTL8367C_EN_MAC1_FORCE_MASK 0x1000 #define RTL8367C_MAC1_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC1_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC2_FORCE_SELECT 0x1314 #define RTL8367C_EN_MAC2_FORCE_OFFSET 12 #define RTL8367C_EN_MAC2_FORCE_MASK 0x1000 #define RTL8367C_MAC2_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC2_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC3_FORCE_SELECT 0x1315 #define RTL8367C_EN_MAC3_FORCE_OFFSET 12 #define RTL8367C_EN_MAC3_FORCE_MASK 0x1000 #define RTL8367C_MAC3_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC3_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC4_FORCE_SELECT 0x1316 #define RTL8367C_EN_MAC4_FORCE_OFFSET 12 #define RTL8367C_EN_MAC4_FORCE_MASK 0x1000 #define RTL8367C_MAC4_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC4_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC5_FORCE_SELECT 0x1317 #define RTL8367C_EN_MAC5_FORCE_OFFSET 12 #define RTL8367C_EN_MAC5_FORCE_MASK 0x1000 #define RTL8367C_MAC5_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC5_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC6_FORCE_SELECT 0x1318 #define RTL8367C_EN_MAC6_FORCE_OFFSET 12 #define RTL8367C_EN_MAC6_FORCE_MASK 0x1000 #define RTL8367C_MAC6_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC6_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_MAC7_FORCE_SELECT 0x1319 #define RTL8367C_EN_MAC7_FORCE_OFFSET 12 #define RTL8367C_EN_MAC7_FORCE_MASK 0x1000 #define RTL8367C_MAC7_FORCE_ABLTY_OFFSET 0 #define RTL8367C_MAC7_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_M10_FORCE_SELECT 0x131c #define RTL8367C_EN_M10_FORCE_OFFSET 12 #define RTL8367C_EN_M10_FORCE_MASK 0x1000 #define RTL8367C_M10_FORCE_ABLTY_OFFSET 0 #define RTL8367C_M10_FORCE_ABLTY_MASK 0xFFF #define RTL8367C_REG_CHIP_RESET 0x1322 #define RTL8367C_GPHY_RESET_OFFSET 6 #define RTL8367C_GPHY_RESET_MASK 0x40 #define RTL8367C_NIC_RST_OFFSET 5 #define RTL8367C_NIC_RST_MASK 0x20 #define RTL8367C_DW8051_RST_OFFSET 4 #define RTL8367C_DW8051_RST_MASK 0x10 #define RTL8367C_SDS_RST_OFFSET 3 #define RTL8367C_SDS_RST_MASK 0x8 #define RTL8367C_CONFIG_RST_OFFSET 2 #define RTL8367C_CONFIG_RST_MASK 0x4 #define RTL8367C_SW_RST_OFFSET 1 #define RTL8367C_SW_RST_MASK 0x2 #define RTL8367C_CHIP_RST_OFFSET 0 #define RTL8367C_CHIP_RST_MASK 0x1 #define RTL8367C_REG_DIGITAL_DEBUG_0 0x1323 #define RTL8367C_REG_DIGITAL_DEBUG_1 0x1324 #define RTL8367C_REG_INTERNAL_PHY_MDC_DRIVER 0x1325 #define RTL8367C_INTERNAL_PHY_MDC_DRIVER_OFFSET 0 #define RTL8367C_INTERNAL_PHY_MDC_DRIVER_MASK 0x3FF #define RTL8367C_REG_LINKDOWN_TIME_CTRL 0x1326 #define RTL8367C_LINKDOWN_TIME_CFG_OFFSET 9 #define RTL8367C_LINKDOWN_TIME_CFG_MASK 0x7E00 #define RTL8367C_LINKDOWN_TIME_ENABLE_OFFSET 8 #define RTL8367C_LINKDOWN_TIME_ENABLE_MASK 0x100 #define RTL8367C_LINKDOWN_TIME_OFFSET 0 #define RTL8367C_LINKDOWN_TIME_MASK 0xFF #define RTL8367C_REG_PHYACK_TIMEOUT 0x1331 #define RTL8367C_REG_MDXACK_TIMEOUT 0x1333 #define RTL8367C_REG_DW8051_RDY 0x1336 #define RTL8367C_VIAROM_WRITE_EN_OFFSET 9 #define RTL8367C_VIAROM_WRITE_EN_MASK 0x200 #define RTL8367C_SPIF_CK2_OFFSET 8 #define RTL8367C_SPIF_CK2_MASK 0x100 #define RTL8367C_RRCP_MDOE_OFFSET 7 #define RTL8367C_RRCP_MDOE_MASK 0x80 #define RTL8367C_DW8051_RATE_OFFSET 4 #define RTL8367C_DW8051_RATE_MASK 0x70 #define RTL8367C_IROM_MSB_OFFSET 2 #define RTL8367C_IROM_MSB_MASK 0xC #define RTL8367C_ACS_IROM_ENABLE_OFFSET 1 #define RTL8367C_ACS_IROM_ENABLE_MASK 0x2 #define RTL8367C_DW8051_READY_OFFSET 0 #define RTL8367C_DW8051_READY_MASK 0x1 #define RTL8367C_REG_BIST_CTRL 0x133c #define RTL8367C_DRF_BIST_DONE_ALL_OFFSET 5 #define RTL8367C_DRF_BIST_DONE_ALL_MASK 0x20 #define RTL8367C_DRF_BIST_PAUSE_ALL_OFFSET 4 #define RTL8367C_DRF_BIST_PAUSE_ALL_MASK 0x10 #define RTL8367C_BIST_DOAN_ALL_OFFSET 3 #define RTL8367C_BIST_DOAN_ALL_MASK 0x8 #define RTL8367C_BIST_PASS_OFFSET 0 #define RTL8367C_BIST_PASS_MASK 0x7 #define RTL8367C_REG_DIAG_MODE2 0x133d #define RTL8367C_DIAG_MODE2_ACTRAM_OFFSET 1 #define RTL8367C_DIAG_MODE2_ACTRAM_MASK 0x2 #define RTL8367C_DIAG_MODE2_BCAM_ACTION_OFFSET 0 #define RTL8367C_DIAG_MODE2_BCAM_ACTION_MASK 0x1 #define RTL8367C_REG_MDX_PHY_REG0 0x133e #define RTL8367C_PHY_BRD_MASK_OFFSET 4 #define RTL8367C_PHY_BRD_MASK_MASK 0x1F0 #define RTL8367C_MDX_INDACC_PAGE_OFFSET 0 #define RTL8367C_MDX_INDACC_PAGE_MASK 0xF #define RTL8367C_REG_MDX_PHY_REG1 0x133f #define RTL8367C_PHY_BRD_MODE_OFFSET 5 #define RTL8367C_PHY_BRD_MODE_MASK 0x20 #define RTL8367C_BRD_PHYAD_OFFSET 0 #define RTL8367C_BRD_PHYAD_MASK 0x1F #define RTL8367C_REG_DEBUG_SIGNAL_SELECT_SW 0x1340 #define RTL8367C_REG_DEBUG_SIGNAL_SELECT_B 0x1341 #define RTL8367C_DEBUG_MX_OFFSET 9 #define RTL8367C_DEBUG_MX_MASK 0xE00 #define RTL8367C_DEBUG_SHIFT_MISC_OFFSET 6 #define RTL8367C_DEBUG_SHIFT_MISC_MASK 0x1C0 #define RTL8367C_DEBUG_SHIFT_SW_OFFSET 3 #define RTL8367C_DEBUG_SHIFT_SW_MASK 0x38 #define RTL8367C_DEBUG_SHIFT_GPHY_OFFSET 0 #define RTL8367C_DEBUG_SHIFT_GPHY_MASK 0x7 #define RTL8367C_REG_DEBUG_SIGNAL_I 0x1343 #define RTL8367C_REG_DEBUG_SIGNAL_H 0x1344 #define RTL8367C_REG_DBGO_SEL_GPHY 0x1345 #define RTL8367C_REG_DBGO_SEL_MISC 0x1346 #define RTL8367C_REG_BYPASS_ABLTY_LOCK 0x1349 #define RTL8367C_BYPASS_ABLTY_LOCK_OFFSET 0 #define RTL8367C_BYPASS_ABLTY_LOCK_MASK 0xFF #define RTL8367C_REG_BYPASS_ABLTY_LOCK_EXT 0x134a #define RTL8367C_BYPASS_P10_ABILIITY_LOCK_OFFSET 3 #define RTL8367C_BYPASS_P10_ABILIITY_LOCK_MASK 0x8 #define RTL8367C_BYPASS_EXT_ABILITY_LOCK_OFFSET 0 #define RTL8367C_BYPASS_EXT_ABILITY_LOCK_MASK 0x7 #define RTL8367C_REG_ACL_GPIO 0x134f #define RTL8367C_ACL_GPIO_13_OFFSET 13 #define RTL8367C_ACL_GPIO_13_MASK 0x2000 #define RTL8367C_ACL_GPIO_12_OFFSET 12 #define RTL8367C_ACL_GPIO_12_MASK 0x1000 #define RTL8367C_ACL_GPIO_11_OFFSET 11 #define RTL8367C_ACL_GPIO_11_MASK 0x800 #define RTL8367C_ACL_GPIO_10_OFFSET 10 #define RTL8367C_ACL_GPIO_10_MASK 0x400 #define RTL8367C_ACL_GPIO_9_OFFSET 9 #define RTL8367C_ACL_GPIO_9_MASK 0x200 #define RTL8367C_ACL_GPIO_8_OFFSET 8 #define RTL8367C_ACL_GPIO_8_MASK 0x100 #define RTL8367C_ACL_GPIO_7_OFFSET 7 #define RTL8367C_ACL_GPIO_7_MASK 0x80 #define RTL8367C_ACL_GPIO_6_OFFSET 6 #define RTL8367C_ACL_GPIO_6_MASK 0x40 #define RTL8367C_ACL_GPIO_5_OFFSET 5 #define RTL8367C_ACL_GPIO_5_MASK 0x20 #define RTL8367C_ACL_GPIO_4_OFFSET 4 #define RTL8367C_ACL_GPIO_4_MASK 0x10 #define RTL8367C_ACL_GPIO_3_OFFSET 3 #define RTL8367C_ACL_GPIO_3_MASK 0x8 #define RTL8367C_ACL_GPIO_2_OFFSET 2 #define RTL8367C_ACL_GPIO_2_MASK 0x4 #define RTL8367C_ACL_GPIO_1_OFFSET 1 #define RTL8367C_ACL_GPIO_1_MASK 0x2 #define RTL8367C_ACL_GPIO_0_OFFSET 0 #define RTL8367C_ACL_GPIO_0_MASK 0x1 #define RTL8367C_REG_EN_GPIO 0x1350 #define RTL8367C_EN_GPIO_13_OFFSET 13 #define RTL8367C_EN_GPIO_13_MASK 0x2000 #define RTL8367C_EN_GPIO_12_OFFSET 12 #define RTL8367C_EN_GPIO_12_MASK 0x1000 #define RTL8367C_EN_GPIO_11_OFFSET 11 #define RTL8367C_EN_GPIO_11_MASK 0x800 #define RTL8367C_EN_GPIO_10_OFFSET 10 #define RTL8367C_EN_GPIO_10_MASK 0x400 #define RTL8367C_EN_GPIO_9_OFFSET 9 #define RTL8367C_EN_GPIO_9_MASK 0x200 #define RTL8367C_EN_GPIO_8_OFFSET 8 #define RTL8367C_EN_GPIO_8_MASK 0x100 #define RTL8367C_EN_GPIO_7_OFFSET 7 #define RTL8367C_EN_GPIO_7_MASK 0x80 #define RTL8367C_EN_GPIO_6_OFFSET 6 #define RTL8367C_EN_GPIO_6_MASK 0x40 #define RTL8367C_EN_GPIO_5_OFFSET 5 #define RTL8367C_EN_GPIO_5_MASK 0x20 #define RTL8367C_EN_GPIO_4_OFFSET 4 #define RTL8367C_EN_GPIO_4_MASK 0x10 #define RTL8367C_EN_GPIO_3_OFFSET 3 #define RTL8367C_EN_GPIO_3_MASK 0x8 #define RTL8367C_EN_GPIO_2_OFFSET 2 #define RTL8367C_EN_GPIO_2_MASK 0x4 #define RTL8367C_EN_GPIO_1_OFFSET 1 #define RTL8367C_EN_GPIO_1_MASK 0x2 #define RTL8367C_EN_GPIO_0_OFFSET 0 #define RTL8367C_EN_GPIO_0_MASK 0x1 #define RTL8367C_REG_CFG_MULTI_PIN 0x1351 #define RTL8367C_CFG_MULTI_PIN_OFFSET 0 #define RTL8367C_CFG_MULTI_PIN_MASK 0x3 #define RTL8367C_REG_PORT0_STATUS 0x1352 #define RTL8367C_PORT0_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT0_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT0_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT0_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT0_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT0_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT0_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT0_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT0_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT0_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT0_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT0_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT0_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT0_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT1_STATUS 0x1353 #define RTL8367C_PORT1_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT1_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT1_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT1_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT1_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT1_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT1_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT1_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT1_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT1_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT1_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT1_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT1_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT1_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT2_STATUS 0x1354 #define RTL8367C_PORT2_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT2_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT2_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT2_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT2_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT2_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT2_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT2_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT2_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT2_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT2_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT2_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT2_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT2_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT3_STATUS 0x1355 #define RTL8367C_PORT3_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT3_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT3_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT3_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT3_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT3_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT3_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT3_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT3_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT3_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT3_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT3_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT3_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT3_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT4_STATUS 0x1356 #define RTL8367C_PORT4_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT4_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT4_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT4_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT4_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT4_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT4_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT4_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT4_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT4_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT4_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT4_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT4_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT4_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT5_STATUS 0x1357 #define RTL8367C_PORT5_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT5_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT5_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT5_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT5_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT5_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT5_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT5_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT5_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT5_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT5_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT5_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT5_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT5_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT6_STATUS 0x1358 #define RTL8367C_PORT6_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT6_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT6_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT6_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT6_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT6_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT6_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT6_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT6_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT6_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT6_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT6_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT6_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT6_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT7_STATUS 0x1359 #define RTL8367C_PORT7_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT7_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT7_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT7_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT7_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT7_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT7_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT7_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT7_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT7_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT7_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT7_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT7_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT7_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT8_STATUS 0x135a #define RTL8367C_PORT8_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT8_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT8_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT8_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT8_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT8_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT8_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT8_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT8_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT8_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT8_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT8_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT8_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT8_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT9_STATUS 0x135b #define RTL8367C_PORT9_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT9_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT9_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT9_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT9_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT9_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT9_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT9_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT9_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT9_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT9_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT9_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT9_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT9_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_PORT10_STATUS 0x135c #define RTL8367C_PORT10_STATUS_EN_1000_LPI_OFFSET 11 #define RTL8367C_PORT10_STATUS_EN_1000_LPI_MASK 0x800 #define RTL8367C_PORT10_STATUS_EN_100_LPI_OFFSET 10 #define RTL8367C_PORT10_STATUS_EN_100_LPI_MASK 0x400 #define RTL8367C_PORT10_STATUS_NWAY_FAULT_OFFSET 9 #define RTL8367C_PORT10_STATUS_NWAY_FAULT_MASK 0x200 #define RTL8367C_PORT10_STATUS_LINK_ON_MASTER_OFFSET 8 #define RTL8367C_PORT10_STATUS_LINK_ON_MASTER_MASK 0x100 #define RTL8367C_PORT10_STATUS_NWAY_CAP_OFFSET 7 #define RTL8367C_PORT10_STATUS_NWAY_CAP_MASK 0x80 #define RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 #define RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 #define RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 #define RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 #define RTL8367C_PORT10_STATUS_LINK_STATE_OFFSET 4 #define RTL8367C_PORT10_STATUS_LINK_STATE_MASK 0x10 #define RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_OFFSET 2 #define RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_MASK 0x4 #define RTL8367C_PORT10_STATUS_LINK_SPEED_OFFSET 0 #define RTL8367C_PORT10_STATUS_LINK_SPEED_MASK 0x3 #define RTL8367C_REG_UPS_CTRL0 0x1362 #define RTL8367C_P3_REF_SD_BIT0_OFFSET 8 #define RTL8367C_P3_REF_SD_BIT0_MASK 0xFF00 #define RTL8367C_P2_REF_SD_OFFSET 0 #define RTL8367C_P2_REF_SD_MASK 0xFF #define RTL8367C_REG_UPS_CTRL1 0x1363 #define RTL8367C_UPS_OUT_OFFSET 8 #define RTL8367C_UPS_OUT_MASK 0xFF00 #define RTL8367C_UPS_WRITE_PULSE_OFFSET 1 #define RTL8367C_UPS_WRITE_PULSE_MASK 0x2 #define RTL8367C_UPS_EN_OFFSET 0 #define RTL8367C_UPS_EN_MASK 0x1 #define RTL8367C_REG_UPS_CTRL2 0x1364 #define RTL8367C_IGNOE_MAC8_LINK_OFFSET 15 #define RTL8367C_IGNOE_MAC8_LINK_MASK 0x8000 #define RTL8367C_AGREE_SLEEP_OFFSET 14 #define RTL8367C_AGREE_SLEEP_MASK 0x4000 #define RTL8367C_WAIT_FOR_AGREEMENT_OFFSET 13 #define RTL8367C_WAIT_FOR_AGREEMENT_MASK 0x2000 #define RTL8367C_WAKE_UP_BY_LINK_OFFSET 12 #define RTL8367C_WAKE_UP_BY_LINK_MASK 0x1000 #define RTL8367C_WAKE_UP_BY_PHY_OFFSET 11 #define RTL8367C_WAKE_UP_BY_PHY_MASK 0x800 #define RTL8367C_SLOW_CLK_TGL_RATE_OFFSET 7 #define RTL8367C_SLOW_CLK_TGL_RATE_MASK 0x780 #define RTL8367C_PLL_G1_CTRL_EN_OFFSET 6 #define RTL8367C_PLL_G1_CTRL_EN_MASK 0x40 #define RTL8367C_PLL_G0_CTRL_EN_OFFSET 5 #define RTL8367C_PLL_G0_CTRL_EN_MASK 0x20 #define RTL8367C_SLOW_DOWN_PLL_EN_OFFSET 4 #define RTL8367C_SLOW_DOWN_PLL_EN_MASK 0x10 #define RTL8367C_SLOW_DOWN_CLK_EN_OFFSET 3 #define RTL8367C_SLOW_DOWN_CLK_EN_MASK 0x8 #define RTL8367C_GATING_CLK_SDS_EN_OFFSET 2 #define RTL8367C_GATING_CLK_SDS_EN_MASK 0x4 #define RTL8367C_GATING_CLK_CHIP_EN_OFFSET 1 #define RTL8367C_GATING_CLK_CHIP_EN_MASK 0x2 #define RTL8367C_GATING_SW_EN_OFFSET 0 #define RTL8367C_GATING_SW_EN_MASK 0x1 #define RTL8367C_REG_GATING_CLK_1 0x1365 #define RTL8367C_ALDPS_MODE_4_OFFSET 15 #define RTL8367C_ALDPS_MODE_4_MASK 0x8000 #define RTL8367C_ALDPS_MODE_3_OFFSET 14 #define RTL8367C_ALDPS_MODE_3_MASK 0x4000 #define RTL8367C_ALDPS_MODE_2_OFFSET 13 #define RTL8367C_ALDPS_MODE_2_MASK 0x2000 #define RTL8367C_ALDPS_MODE_1_OFFSET 12 #define RTL8367C_ALDPS_MODE_1_MASK 0x1000 #define RTL8367C_ALDPS_MODE_0_OFFSET 11 #define RTL8367C_ALDPS_MODE_0_MASK 0x800 #define RTL8367C_UPS_DBGO_OFFSET 10 #define RTL8367C_UPS_DBGO_MASK 0x400 #define RTL8367C_IFMX_AFF_NOT_FF_OUT_OFFSET 9 #define RTL8367C_IFMX_AFF_NOT_FF_OUT_MASK 0x200 #define RTL8367C_WATER_LEVEL_FD_OFFSET 6 #define RTL8367C_WATER_LEVEL_FD_MASK 0x1C0 #define RTL8367C_WATER_LEVEL_Y2X_OFFSET 3 #define RTL8367C_WATER_LEVEL_Y2X_MASK 0x38 #define RTL8367C_WATER_LEVEL_X2Y_2_OFFSET 2 #define RTL8367C_WATER_LEVEL_X2Y_2_MASK 0x4 #define RTL8367C_IGNOE_MAC10_LINK_OFFSET 1 #define RTL8367C_IGNOE_MAC10_LINK_MASK 0x2 #define RTL8367C_IGNOE_MAC9_LINK_OFFSET 0 #define RTL8367C_IGNOE_MAC9_LINK_MASK 0x1 #define RTL8367C_REG_UPS_CTRL4 0x1366 #define RTL8367C_PROB_EN_OFFSET 6 #define RTL8367C_PROB_EN_MASK 0x40 #define RTL8367C_PLL_DOWN_OFFSET 1 #define RTL8367C_PLL_DOWN_MASK 0x2 #define RTL8367C_XTAL_DOWN_OFFSET 0 #define RTL8367C_XTAL_DOWN_MASK 0x1 #define RTL8367C_REG_UPS_CTRL5 0x1367 #define RTL8367C_FRC_CPU_ACPT_OFFSET 3 #define RTL8367C_FRC_CPU_ACPT_MASK 0x8 #define RTL8367C_UPS_CPU_ACPT_OFFSET 2 #define RTL8367C_UPS_CPU_ACPT_MASK 0x4 #define RTL8367C_UPS_DBG_4_OFFSET 0 #define RTL8367C_UPS_DBG_4_MASK 0x3 #define RTL8367C_REG_UPS_CTRL6 0x1368 #define RTL8367C_UPS_CTRL6_OFFSET 0 #define RTL8367C_UPS_CTRL6_MASK 0xF #define RTL8367C_REG_EFUSE_CMD_70B 0x1369 #define RTL8367C_REG_EFUSE_CMD 0x1370 #define RTL8367C_EFUSE_TIME_OUT_FLAG_OFFSET 3 #define RTL8367C_EFUSE_TIME_OUT_FLAG_MASK 0x8 #define RTL8367C_EFUSE_ACCESS_BUSY_OFFSET 2 #define RTL8367C_EFUSE_ACCESS_BUSY_MASK 0x4 #define RTL8367C_EFUSE_COMMAND_EN_OFFSET 1 #define RTL8367C_EFUSE_COMMAND_EN_MASK 0x2 #define RTL8367C_EFUSE_WR_OFFSET 0 #define RTL8367C_EFUSE_WR_MASK 0x1 #define RTL8367C_REG_EFUSE_ADR 0x1371 #define RTL8367C_DUMMY_15_10_OFFSET 8 #define RTL8367C_DUMMY_15_10_MASK 0xFF00 #define RTL8367C_EFUSE_ADDRESS_OFFSET 0 #define RTL8367C_EFUSE_ADDRESS_MASK 0xFF #define RTL8367C_REG_EFUSE_WDAT 0x1372 #define RTL8367C_REG_EFUSE_RDAT 0x1373 #define RTL8367C_REG_I2C_CTRL 0x1374 #define RTL8367C_MDX_MST_FAIL_LAT_OFFSET 1 #define RTL8367C_MDX_MST_FAIL_LAT_MASK 0x2 #define RTL8367C_MDX_MST_FAIL_CLRPS_OFFSET 0 #define RTL8367C_MDX_MST_FAIL_CLRPS_MASK 0x1 #define RTL8367C_REG_EEE_CFG 0x1375 #define RTL8367C_CFG_BYPASS_GATELPTD_OFFSET 11 #define RTL8367C_CFG_BYPASS_GATELPTD_MASK 0x800 #define RTL8367C_EEE_ABT_ADDR2_OFFSET 6 #define RTL8367C_EEE_ABT_ADDR2_MASK 0x7C0 #define RTL8367C_EEE_ABT_ADDR1_OFFSET 1 #define RTL8367C_EEE_ABT_ADDR1_MASK 0x3E #define RTL8367C_EEE_POLL_EN_OFFSET 0 #define RTL8367C_EEE_POLL_EN_MASK 0x1 #define RTL8367C_REG_EEE_PAGE 0x1376 #define RTL8367C_REG_EEE_EXT_PAGE 0x1377 #define RTL8367C_REG_EEE_EN_SPD1000 0x1378 #define RTL8367C_REG_EEE_EN_SPD100 0x1379 #define RTL8367C_REG_EEE_LP_SPD1000 0x137a #define RTL8367C_REG_EEE_LP_SPD100 0x137b #define RTL8367C_REG_DW8051_PRO_REG0 0x13a0 #define RTL8367C_REG_DW8051_PRO_REG1 0x13a1 #define RTL8367C_REG_DW8051_PRO_REG2 0x13a2 #define RTL8367C_REG_DW8051_PRO_REG3 0x13a3 #define RTL8367C_REG_DW8051_PRO_REG4 0x13a4 #define RTL8367C_REG_DW8051_PRO_REG5 0x13a5 #define RTL8367C_REG_DW8051_PRO_REG6 0x13a6 #define RTL8367C_REG_DW8051_PRO_REG7 0x13a7 #define RTL8367C_REG_PROTECT_ID 0x13c0 #define RTL8367C_REG_CHIP_VER_INTL 0x13c1 #define RTL8367C_CHIP_VER_INTL_OFFSET 0 #define RTL8367C_CHIP_VER_INTL_MASK 0xF #define RTL8367C_REG_MAGIC_ID 0x13c2 #define RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1 0x13c3 #define RTL8367C_SKIP_MII_2_RXER_OFFSET 4 #define RTL8367C_SKIP_MII_2_RXER_MASK 0x10 #define RTL8367C_SELECT_GMII_2_OFFSET 0 #define RTL8367C_SELECT_GMII_2_MASK 0xF #define RTL8367C_REG_DIGITAL_INTERFACE2_FORCE 0x13c4 #define RTL8367C_GMII_2_FORCE_OFFSET 12 #define RTL8367C_GMII_2_FORCE_MASK 0x1000 #define RTL8367C_RGMII_2_FORCE_OFFSET 0 #define RTL8367C_RGMII_2_FORCE_MASK 0xFFF #define RTL8367C_REG_EXT2_RGMXF 0x13c5 #define RTL8367C_EXT2_RGTX_INV_OFFSET 6 #define RTL8367C_EXT2_RGTX_INV_MASK 0x40 #define RTL8367C_EXT2_RGRX_INV_OFFSET 5 #define RTL8367C_EXT2_RGRX_INV_MASK 0x20 #define RTL8367C_EXT2_RGMXF_OFFSET 0 #define RTL8367C_EXT2_RGMXF_MASK 0x1F #define RTL8367C_REG_ROUTER_UPS_CFG 0x13c6 #define RTL8367C_UPS_Status_OFFSET 1 #define RTL8367C_UPS_Status_MASK 0x2 #define RTL8367C_SoftStart_OFFSET 0 #define RTL8367C_SoftStart_MASK 0x1 #define RTL8367C_REG_CTRL_GPIO 0x13c7 #define RTL8367C_CTRL_GPIO_13_OFFSET 13 #define RTL8367C_CTRL_GPIO_13_MASK 0x2000 #define RTL8367C_CTRL_GPIO_12_OFFSET 12 #define RTL8367C_CTRL_GPIO_12_MASK 0x1000 #define RTL8367C_CTRL_GPIO_11_OFFSET 11 #define RTL8367C_CTRL_GPIO_11_MASK 0x800 #define RTL8367C_CTRL_GPIO_10_OFFSET 10 #define RTL8367C_CTRL_GPIO_10_MASK 0x400 #define RTL8367C_CTRL_GPIO_9_OFFSET 9 #define RTL8367C_CTRL_GPIO_9_MASK 0x200 #define RTL8367C_CTRL_GPIO_8_OFFSET 8 #define RTL8367C_CTRL_GPIO_8_MASK 0x100 #define RTL8367C_CTRL_GPIO_7_OFFSET 7 #define RTL8367C_CTRL_GPIO_7_MASK 0x80 #define RTL8367C_CTRL_GPIO_6_OFFSET 6 #define RTL8367C_CTRL_GPIO_6_MASK 0x40 #define RTL8367C_CTRL_GPIO_5_OFFSET 5 #define RTL8367C_CTRL_GPIO_5_MASK 0x20 #define RTL8367C_CTRL_GPIO_4_OFFSET 4 #define RTL8367C_CTRL_GPIO_4_MASK 0x10 #define RTL8367C_CTRL_GPIO_3_OFFSET 3 #define RTL8367C_CTRL_GPIO_3_MASK 0x8 #define RTL8367C_CTRL_GPIO_2_OFFSET 2 #define RTL8367C_CTRL_GPIO_2_MASK 0x4 #define RTL8367C_CTRL_GPIO_1_OFFSET 1 #define RTL8367C_CTRL_GPIO_1_MASK 0x2 #define RTL8367C_CTRL_GPIO_0_OFFSET 0 #define RTL8367C_CTRL_GPIO_0_MASK 0x1 #define RTL8367C_REG_SEL_GPIO 0x13c8 #define RTL8367C_SEL_GPIO_13_OFFSET 13 #define RTL8367C_SEL_GPIO_13_MASK 0x2000 #define RTL8367C_SEL_GPIO_12_OFFSET 12 #define RTL8367C_SEL_GPIO_12_MASK 0x1000 #define RTL8367C_SEL_GPIO_11_OFFSET 11 #define RTL8367C_SEL_GPIO_11_MASK 0x800 #define RTL8367C_SEL_GPIO_10_OFFSET 10 #define RTL8367C_SEL_GPIO_10_MASK 0x400 #define RTL8367C_SEL_GPIO_9_OFFSET 9 #define RTL8367C_SEL_GPIO_9_MASK 0x200 #define RTL8367C_SEL_GPIO_8_OFFSET 8 #define RTL8367C_SEL_GPIO_8_MASK 0x100 #define RTL8367C_SEL_GPIO_7_OFFSET 7 #define RTL8367C_SEL_GPIO_7_MASK 0x80 #define RTL8367C_SEL_GPIO_6_OFFSET 6 #define RTL8367C_SEL_GPIO_6_MASK 0x40 #define RTL8367C_SEL_GPIO_5_OFFSET 5 #define RTL8367C_SEL_GPIO_5_MASK 0x20 #define RTL8367C_SEL_GPIO_4_OFFSET 4 #define RTL8367C_SEL_GPIO_4_MASK 0x10 #define RTL8367C_SEL_GPIO_3_OFFSET 3 #define RTL8367C_SEL_GPIO_3_MASK 0x8 #define RTL8367C_SEL_GPIO_2_OFFSET 2 #define RTL8367C_SEL_GPIO_2_MASK 0x4 #define RTL8367C_SEL_GPIO_1_OFFSET 1 #define RTL8367C_SEL_GPIO_1_MASK 0x2 #define RTL8367C_SEL_GPIO_0_OFFSET 0 #define RTL8367C_SEL_GPIO_0_MASK 0x1 #define RTL8367C_REG_STATUS_GPIO 0x13c9 #define RTL8367C_STATUS_GPIO_OFFSET 0 #define RTL8367C_STATUS_GPIO_MASK 0x3FFF #define RTL8367C_REG_SYNC_ETH_CFG 0x13e0 #define RTL8367C_DUMMY2_OFFSET 9 #define RTL8367C_DUMMY2_MASK 0xFE00 #define RTL8367C_RFC2819_TYPE_OFFSET 8 #define RTL8367C_RFC2819_TYPE_MASK 0x100 #define RTL8367C_DUMMY1_OFFSET 7 #define RTL8367C_DUMMY1_MASK 0x80 #define RTL8367C_FIBER_SYNCE125_L_SEL_OFFSET 6 #define RTL8367C_FIBER_SYNCE125_L_SEL_MASK 0x40 #define RTL8367C_SYNC_ETH_EN_RTT2_OFFSET 5 #define RTL8367C_SYNC_ETH_EN_RTT2_MASK 0x20 #define RTL8367C_SYNC_ETH_EN_RTT1_OFFSET 4 #define RTL8367C_SYNC_ETH_EN_RTT1_MASK 0x10 #define RTL8367C_SYNC_ETH_SEL_DPLL_OFFSET 3 #define RTL8367C_SYNC_ETH_SEL_DPLL_MASK 0x8 #define RTL8367C_SYNC_ETH_SEL_PHYREF_OFFSET 2 #define RTL8367C_SYNC_ETH_SEL_PHYREF_MASK 0x4 #define RTL8367C_SYNC_ETH_SEL_XTAL_OFFSET 1 #define RTL8367C_SYNC_ETH_SEL_XTAL_MASK 0x2 #define RTL8367C_DUMMY0_OFFSET 0 #define RTL8367C_DUMMY0_MASK 0x1 #define RTL8367C_REG_LED_DRI_CFG 0x13e1 #define RTL8367C_LED_DRI_CFG_DUMMY_OFFSET 1 #define RTL8367C_LED_DRI_CFG_DUMMY_MASK 0xFFFE #define RTL8367C_LED_DRIVING_OFFSET 0 #define RTL8367C_LED_DRIVING_MASK 0x1 #define RTL8367C_REG_CHIP_DEBUG2 0x13e2 #define RTL8367C_RG2_DN_OFFSET 6 #define RTL8367C_RG2_DN_MASK 0x1C0 #define RTL8367C_RG2_DP_OFFSET 3 #define RTL8367C_RG2_DP_MASK 0x38 #define RTL8367C_DRI_EXT2_RG_OFFSET 2 #define RTL8367C_DRI_EXT2_RG_MASK 0x4 #define RTL8367C_DRI_EXT2_OFFSET 1 #define RTL8367C_DRI_EXT2_MASK 0x2 #define RTL8367C_SLR_EXT2_OFFSET 0 #define RTL8367C_SLR_EXT2_MASK 0x1 #define RTL8367C_REG_DIGITAL_DEBUG_2 0x13e3 #define RTL8367C_REG_FIBER_RTL_OUI_CFG0 0x13e4 #define RTL8367C_FIBER_RTL_OUI_CFG0_OFFSET 0 #define RTL8367C_FIBER_RTL_OUI_CFG0_MASK 0xFF #define RTL8367C_REG_FIBER_RTL_OUI_CFG1 0x13e5 #define RTL8367C_REG_FIBER_CFG_0 0x13e6 #define RTL8367C_REV_NUM_OFFSET 8 #define RTL8367C_REV_NUM_MASK 0xF00 #define RTL8367C_MODEL_NUM_OFFSET 0 #define RTL8367C_MODEL_NUM_MASK 0x3F #define RTL8367C_REG_FIBER_CFG_1 0x13e7 #define RTL8367C_SDS_FRC_REG4_OFFSET 12 #define RTL8367C_SDS_FRC_REG4_MASK 0x1000 #define RTL8367C_SDS_FRC_REG4_FIB100_OFFSET 11 #define RTL8367C_SDS_FRC_REG4_FIB100_MASK 0x800 #define RTL8367C_SEL_MASK_ONL_OFFSET 5 #define RTL8367C_SEL_MASK_ONL_MASK 0x20 #define RTL8367C_DIS_QUALITY_IN_MASK_OFFSET 4 #define RTL8367C_DIS_QUALITY_IN_MASK_MASK 0x10 #define RTL8367C_SDS_FRC_MODE_OFFSET 3 #define RTL8367C_SDS_FRC_MODE_MASK 0x8 #define RTL8367C_SDS_MODE_OFFSET 0 #define RTL8367C_SDS_MODE_MASK 0x7 #define RTL8367C_REG_FIBER_CFG_2 0x13e8 #define RTL8367C_SEL_SDET_PS_OFFSET 12 #define RTL8367C_SEL_SDET_PS_MASK 0xF000 #define RTL8367C_UTP_DIS_RX_OFFSET 10 #define RTL8367C_UTP_DIS_RX_MASK 0xC00 #define RTL8367C_UTP_FRC_LD_OFFSET 8 #define RTL8367C_UTP_FRC_LD_MASK 0x300 #define RTL8367C_SDS_RX_DISABLE_OFFSET 6 #define RTL8367C_SDS_RX_DISABLE_MASK 0xC0 #define RTL8367C_SDS_TX_DISABLE_OFFSET 4 #define RTL8367C_SDS_TX_DISABLE_MASK 0x30 #define RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_OFFSET 2 #define RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_MASK 0xC #define RTL8367C_SDS_FRC_LD_OFFSET 0 #define RTL8367C_SDS_FRC_LD_MASK 0x3 #define RTL8367C_REG_FIBER_CFG_3 0x13e9 #define RTL8367C_FIBER_CFG_3_OFFSET 0 #define RTL8367C_FIBER_CFG_3_MASK 0xFFF #define RTL8367C_REG_FIBER_CFG_4 0x13ea #define RTL8367C_REG_UTP_FIB_DET 0x13eb #define RTL8367C_FORCE_SEL_FIBER_OFFSET 14 #define RTL8367C_FORCE_SEL_FIBER_MASK 0xC000 #define RTL8367C_FIB_FINAL_TIMER_OFFSET 12 #define RTL8367C_FIB_FINAL_TIMER_MASK 0x3000 #define RTL8367C_FIB_LINK_TIMER_OFFSET 10 #define RTL8367C_FIB_LINK_TIMER_MASK 0xC00 #define RTL8367C_FIB_SDET_TIMER_OFFSET 8 #define RTL8367C_FIB_SDET_TIMER_MASK 0x300 #define RTL8367C_UTP_LINK_TIMER_OFFSET 6 #define RTL8367C_UTP_LINK_TIMER_MASK 0xC0 #define RTL8367C_UTP_SDET_TIMER_OFFSET 4 #define RTL8367C_UTP_SDET_TIMER_MASK 0x30 #define RTL8367C_FORCE_AUTODET_OFFSET 3 #define RTL8367C_FORCE_AUTODET_MASK 0x8 #define RTL8367C_AUTODET_FSM_CLR_OFFSET 2 #define RTL8367C_AUTODET_FSM_CLR_MASK 0x4 #define RTL8367C_UTP_FIRST_OFFSET 1 #define RTL8367C_UTP_FIRST_MASK 0x2 #define RTL8367C_UTP_FIB_DISAUTODET_OFFSET 0 #define RTL8367C_UTP_FIB_DISAUTODET_MASK 0x1 #define RTL8367C_REG_NRESTORE_MAGIC_NUM 0x13ec #define RTL8367C_NRESTORE_MAGIC_NUM_MASK 0xFFFF #define RTL8367C_EEPROM_PROGRAM_CYCLE_OFFSET 0 #define RTL8367C_EEPROM_PROGRAM_CYCLE_MASK 0x3 #define RTL8367C_REG_MAC_ACTIVE 0x13ee #define RTL8367C_MAC_ACTIVE_H_OFFSET 9 #define RTL8367C_MAC_ACTIVE_H_MASK 0xE00 #define RTL8367C_FORCE_MAC_ACTIVE_OFFSET 8 #define RTL8367C_FORCE_MAC_ACTIVE_MASK 0x100 #define RTL8367C_MAC_ACTIVE_OFFSET 0 #define RTL8367C_MAC_ACTIVE_MASK 0xFF #define RTL8367C_REG_SERDES_RESULT 0x13ef #define RTL8367C_FIB100_DET_1_OFFSET 12 #define RTL8367C_FIB100_DET_1_MASK 0x1000 #define RTL8367C_FIB_ISO_1_OFFSET 11 #define RTL8367C_FIB_ISO_1_MASK 0x800 #define RTL8367C_SDS_ANFAULT_1_OFFSET 10 #define RTL8367C_SDS_ANFAULT_1_MASK 0x400 #define RTL8367C_SDS_INTB_1_OFFSET 9 #define RTL8367C_SDS_INTB_1_MASK 0x200 #define RTL8367C_SDS_LINK_OK_1_OFFSET 8 #define RTL8367C_SDS_LINK_OK_1_MASK 0x100 #define RTL8367C_FIB100_DET_OFFSET 4 #define RTL8367C_FIB100_DET_MASK 0x10 #define RTL8367C_FIB_ISO_OFFSET 3 #define RTL8367C_FIB_ISO_MASK 0x8 #define RTL8367C_SDS_ANFAULT_OFFSET 2 #define RTL8367C_SDS_ANFAULT_MASK 0x4 #define RTL8367C_SDS_INTB_OFFSET 1 #define RTL8367C_SDS_INTB_MASK 0x2 #define RTL8367C_SDS_LINK_OK_OFFSET 0 #define RTL8367C_SDS_LINK_OK_MASK 0x1 #define RTL8367C_REG_CHIP_ECO 0x13f0 #define RTL8367C_CFG_CHIP_ECO_OFFSET 1 #define RTL8367C_CFG_CHIP_ECO_MASK 0xFFFE #define RTL8367C_CFG_CKOUTEN_OFFSET 0 #define RTL8367C_CFG_CKOUTEN_MASK 0x1 #define RTL8367C_REG_WAKELPI_SLOT_PRD 0x13f1 #define RTL8367C_WAKELPI_SLOT_PRD_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_PRD_MASK 0x1F #define RTL8367C_REG_WAKELPI_SLOT_PG0 0x13f2 #define RTL8367C_WAKELPI_SLOT_P1_OFFSET 8 #define RTL8367C_WAKELPI_SLOT_P1_MASK 0x1F00 #define RTL8367C_WAKELPI_SLOT_P0_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_P0_MASK 0x1F #define RTL8367C_REG_WAKELPI_SLOT_PG1 0x13f3 #define RTL8367C_WAKELPI_SLOT_P3_OFFSET 8 #define RTL8367C_WAKELPI_SLOT_P3_MASK 0x1F00 #define RTL8367C_WAKELPI_SLOT_P2_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_P2_MASK 0x1F #define RTL8367C_REG_WAKELPI_SLOT_PG2 0x13f4 #define RTL8367C_WAKELPI_SLOT_P5_OFFSET 8 #define RTL8367C_WAKELPI_SLOT_P5_MASK 0x1F00 #define RTL8367C_WAKELPI_SLOT_P4_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_P4_MASK 0x1F #define RTL8367C_REG_WAKELPI_SLOT_PG3 0x13f5 #define RTL8367C_WAKELPI_SLOT_P7_OFFSET 8 #define RTL8367C_WAKELPI_SLOT_P7_MASK 0x1F00 #define RTL8367C_WAKELPI_SLOT_P6_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_P6_MASK 0x1F #define RTL8367C_REG_SYNC_FIFO_0 0x13f6 #define RTL8367C_SYNC_FIFO_TX_OFFSET 8 #define RTL8367C_SYNC_FIFO_TX_MASK 0x700 #define RTL8367C_SYNC_FIFO_RX_OFFSET 0 #define RTL8367C_SYNC_FIFO_RX_MASK 0xFF #define RTL8367C_REG_SYNC_FIFO_1 0x13f7 #define RTL8367C_SYNC_FIFO_RX_ERR_P10_8_OFFSET 11 #define RTL8367C_SYNC_FIFO_RX_ERR_P10_8_MASK 0x3800 #define RTL8367C_SYNC_FIFO_TX_ERR_OFFSET 8 #define RTL8367C_SYNC_FIFO_TX_ERR_MASK 0x700 #define RTL8367C_SYNC_FIFO_RX_ERR_OFFSET 0 #define RTL8367C_SYNC_FIFO_RX_ERR_MASK 0xFF #define RTL8367C_REG_RGM_EEE 0x13f8 #define RTL8367C_EXT2_PAD_STOP_EN_OFFSET 14 #define RTL8367C_EXT2_PAD_STOP_EN_MASK 0x4000 #define RTL8367C_EXT1_PAD_STOP_EN_OFFSET 13 #define RTL8367C_EXT1_PAD_STOP_EN_MASK 0x2000 #define RTL8367C_EXT0_PAD_STOP_EN_OFFSET 12 #define RTL8367C_EXT0_PAD_STOP_EN_MASK 0x1000 #define RTL8367C_EXT2_CYCLE_PAD_OFFSET 8 #define RTL8367C_EXT2_CYCLE_PAD_MASK 0xF00 #define RTL8367C_EXT1_CYCLE_PAD_OFFSET 4 #define RTL8367C_EXT1_CYCLE_PAD_MASK 0xF0 #define RTL8367C_EXT0_CYCLE_PAD_OFFSET 0 #define RTL8367C_EXT0_CYCLE_PAD_MASK 0xF #define RTL8367C_REG_EXT_TXC_DLY 0x13f9 #define RTL8367C_EXT1_GMII_TX_DELAY_OFFSET 12 #define RTL8367C_EXT1_GMII_TX_DELAY_MASK 0x7000 #define RTL8367C_EXT0_GMII_TX_DELAY_OFFSET 9 #define RTL8367C_EXT0_GMII_TX_DELAY_MASK 0xE00 #define RTL8367C_EXT2_RGMII_TX_DELAY_OFFSET 6 #define RTL8367C_EXT2_RGMII_TX_DELAY_MASK 0x1C0 #define RTL8367C_EXT1_RGMII_TX_DELAY_OFFSET 3 #define RTL8367C_EXT1_RGMII_TX_DELAY_MASK 0x38 #define RTL8367C_EXT0_RGMII_TX_DELAY_OFFSET 0 #define RTL8367C_EXT0_RGMII_TX_DELAY_MASK 0x7 #define RTL8367C_REG_IO_MISC_CTRL 0x13fa #define RTL8367C_IO_BUZZER_EN_OFFSET 3 #define RTL8367C_IO_BUZZER_EN_MASK 0x8 #define RTL8367C_IO_INTRPT_EN_OFFSET 2 #define RTL8367C_IO_INTRPT_EN_MASK 0x4 #define RTL8367C_IO_NRESTORE_EN_OFFSET 1 #define RTL8367C_IO_NRESTORE_EN_MASK 0x2 #define RTL8367C_IO_UART_EN_OFFSET 0 #define RTL8367C_IO_UART_EN_MASK 0x1 #define RTL8367C_REG_CHIP_DUMMY_NO 0x13fb #define RTL8367C_CHIP_DUMMY_NO_OFFSET 0 #define RTL8367C_CHIP_DUMMY_NO_MASK 0xF #define RTL8367C_REG_RC_CALIB_CFG 0x13fc #define RTL8367C_TRIG_BURN_EFUSE_OFFSET 9 #define RTL8367C_TRIG_BURN_EFUSE_MASK 0x200 #define RTL8367C_AMP_CALIB_FAIL_OFFSET 8 #define RTL8367C_AMP_CALIB_FAIL_MASK 0x100 #define RTL8367C_R_CALIB_FAIL_OFFSET 7 #define RTL8367C_R_CALIB_FAIL_MASK 0x80 #define RTL8367C_CFG_CALIB_MODE_OFFSET 6 #define RTL8367C_CFG_CALIB_MODE_MASK 0x40 #define RTL8367C_CENTER_PORT_SEL_OFFSET 3 #define RTL8367C_CENTER_PORT_SEL_MASK 0x38 #define RTL8367C_CALIB_FINISH_OFFSET 2 #define RTL8367C_CALIB_FINISH_MASK 0x4 #define RTL8367C_CFG_CALIB_OPTION_OFFSET 1 #define RTL8367C_CFG_CALIB_OPTION_MASK 0x2 #define RTL8367C_CFG_CALIB_EN_OFFSET 0 #define RTL8367C_CFG_CALIB_EN_MASK 0x1 #define RTL8367C_REG_WAKELPI_SLOT_PG4 0x13fd #define RTL8367C_WAKELPI_SLOT_P9_OFFSET 8 #define RTL8367C_WAKELPI_SLOT_P9_MASK 0x1F00 #define RTL8367C_WAKELPI_SLOT_P8_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_P8_MASK 0x1F #define RTL8367C_REG_WAKELPI_SLOT_PG5 0x13fe #define RTL8367C_WAKELPI_SLOT_PG5_OFFSET 0 #define RTL8367C_WAKELPI_SLOT_PG5_MASK 0x1F /* (16'h1400)mtrpool_reg */ #define RTL8367C_REG_METER0_RATE_CTRL0 0x1400 #define RTL8367C_REG_METER0_RATE_CTRL1 0x1401 #define RTL8367C_METER0_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER0_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER1_RATE_CTRL0 0x1402 #define RTL8367C_REG_METER1_RATE_CTRL1 0x1403 #define RTL8367C_METER1_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER1_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER2_RATE_CTRL0 0x1404 #define RTL8367C_REG_METER2_RATE_CTRL1 0x1405 #define RTL8367C_METER2_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER2_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER3_RATE_CTRL0 0x1406 #define RTL8367C_REG_METER3_RATE_CTRL1 0x1407 #define RTL8367C_METER3_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER3_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER4_RATE_CTRL0 0x1408 #define RTL8367C_REG_METER4_RATE_CTRL1 0x1409 #define RTL8367C_METER4_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER4_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER5_RATE_CTRL0 0x140a #define RTL8367C_REG_METER5_RATE_CTRL1 0x140b #define RTL8367C_METER5_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER5_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER6_RATE_CTRL0 0x140c #define RTL8367C_REG_METER6_RATE_CTRL1 0x140d #define RTL8367C_METER6_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER6_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER7_RATE_CTRL0 0x140e #define RTL8367C_REG_METER7_RATE_CTRL1 0x140f #define RTL8367C_METER7_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER7_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER8_RATE_CTRL0 0x1410 #define RTL8367C_REG_METER8_RATE_CTRL1 0x1411 #define RTL8367C_METER8_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER8_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER9_RATE_CTRL0 0x1412 #define RTL8367C_REG_METER9_RATE_CTRL1 0x1413 #define RTL8367C_METER9_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER9_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER10_RATE_CTRL0 0x1414 #define RTL8367C_REG_METER10_RATE_CTRL1 0x1415 #define RTL8367C_METER10_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER10_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER11_RATE_CTRL0 0x1416 #define RTL8367C_REG_METER11_RATE_CTRL1 0x1417 #define RTL8367C_METER11_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER11_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER12_RATE_CTRL0 0x1418 #define RTL8367C_REG_METER12_RATE_CTRL1 0x1419 #define RTL8367C_METER12_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER12_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER13_RATE_CTRL0 0x141a #define RTL8367C_REG_METER13_RATE_CTRL1 0x141b #define RTL8367C_METER13_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER13_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER14_RATE_CTRL0 0x141c #define RTL8367C_REG_METER14_RATE_CTRL1 0x141d #define RTL8367C_METER14_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER14_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER15_RATE_CTRL0 0x141e #define RTL8367C_REG_METER15_RATE_CTRL1 0x141f #define RTL8367C_METER15_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER15_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER16_RATE_CTRL0 0x1420 #define RTL8367C_REG_METER16_RATE_CTRL1 0x1421 #define RTL8367C_METER16_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER16_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER17_RATE_CTRL0 0x1422 #define RTL8367C_REG_METER17_RATE_CTRL1 0x1423 #define RTL8367C_METER17_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER17_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER18_RATE_CTRL0 0x1424 #define RTL8367C_REG_METER18_RATE_CTRL1 0x1425 #define RTL8367C_METER18_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER18_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER19_RATE_CTRL0 0x1426 #define RTL8367C_REG_METER19_RATE_CTRL1 0x1427 #define RTL8367C_METER19_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER19_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER20_RATE_CTRL0 0x1428 #define RTL8367C_REG_METER20_RATE_CTRL1 0x1429 #define RTL8367C_METER20_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER20_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER21_RATE_CTRL0 0x142a #define RTL8367C_REG_METER21_RATE_CTRL1 0x142b #define RTL8367C_METER21_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER21_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER22_RATE_CTRL0 0x142c #define RTL8367C_REG_METER22_RATE_CTRL1 0x142d #define RTL8367C_METER22_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER22_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER23_RATE_CTRL0 0x142e #define RTL8367C_REG_METER23_RATE_CTRL1 0x142f #define RTL8367C_METER23_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER23_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER24_RATE_CTRL0 0x1430 #define RTL8367C_REG_METER24_RATE_CTRL1 0x1431 #define RTL8367C_METER24_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER24_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER25_RATE_CTRL0 0x1432 #define RTL8367C_REG_METER25_RATE_CTRL1 0x1433 #define RTL8367C_METER25_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER25_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER26_RATE_CTRL0 0x1434 #define RTL8367C_REG_METER26_RATE_CTRL1 0x1435 #define RTL8367C_METER26_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER26_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER27_RATE_CTRL0 0x1436 #define RTL8367C_REG_METER27_RATE_CTRL1 0x1437 #define RTL8367C_METER27_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER27_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER28_RATE_CTRL0 0x1438 #define RTL8367C_REG_METER28_RATE_CTRL1 0x1439 #define RTL8367C_METER28_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER28_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER29_RATE_CTRL0 0x143a #define RTL8367C_REG_METER29_RATE_CTRL1 0x143b #define RTL8367C_METER29_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER29_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER30_RATE_CTRL0 0x143c #define RTL8367C_REG_METER30_RATE_CTRL1 0x143d #define RTL8367C_METER30_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER30_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER31_RATE_CTRL0 0x143e #define RTL8367C_REG_METER31_RATE_CTRL1 0x143f #define RTL8367C_METER31_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER31_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER_MODE_SETTING0 0x1440 #define RTL8367C_REG_METER_MODE_SETTING1 0x1441 #define RTL8367C_REG_METER_MODE_TOKEN_CFG 0x1442 #define RTL8367C_METER_MODE_TOKEN_CFG_OFFSET 0 #define RTL8367C_METER_MODE_TOKEN_CFG_MASK 0x7FF #define RTL8367C_REG_METER0_BUCKET_SIZE 0x1600 #define RTL8367C_REG_METER1_BUCKET_SIZE 0x1601 #define RTL8367C_REG_METER2_BUCKET_SIZE 0x1602 #define RTL8367C_REG_METER3_BUCKET_SIZE 0x1603 #define RTL8367C_REG_METER4_BUCKET_SIZE 0x1604 #define RTL8367C_REG_METER5_BUCKET_SIZE 0x1605 #define RTL8367C_REG_METER6_BUCKET_SIZE 0x1606 #define RTL8367C_REG_METER7_BUCKET_SIZE 0x1607 #define RTL8367C_REG_METER8_BUCKET_SIZE 0x1608 #define RTL8367C_REG_METER9_BUCKET_SIZE 0x1609 #define RTL8367C_REG_METER10_BUCKET_SIZE 0x160a #define RTL8367C_REG_METER11_BUCKET_SIZE 0x160b #define RTL8367C_REG_METER12_BUCKET_SIZE 0x160c #define RTL8367C_REG_METER13_BUCKET_SIZE 0x160d #define RTL8367C_REG_METER14_BUCKET_SIZE 0x160e #define RTL8367C_REG_METER15_BUCKET_SIZE 0x160f #define RTL8367C_REG_METER16_BUCKET_SIZE 0x1610 #define RTL8367C_REG_METER17_BUCKET_SIZE 0x1611 #define RTL8367C_REG_METER18_BUCKET_SIZE 0x1612 #define RTL8367C_REG_METER19_BUCKET_SIZE 0x1613 #define RTL8367C_REG_METER20_BUCKET_SIZE 0x1614 #define RTL8367C_REG_METER21_BUCKET_SIZE 0x1615 #define RTL8367C_REG_METER22_BUCKET_SIZE 0x1616 #define RTL8367C_REG_METER23_BUCKET_SIZE 0x1617 #define RTL8367C_REG_METER24_BUCKET_SIZE 0x1618 #define RTL8367C_REG_METER25_BUCKET_SIZE 0x1619 #define RTL8367C_REG_METER26_BUCKET_SIZE 0x161a #define RTL8367C_REG_METER27_BUCKET_SIZE 0x161b #define RTL8367C_REG_METER28_BUCKET_SIZE 0x161c #define RTL8367C_REG_METER29_BUCKET_SIZE 0x161d #define RTL8367C_REG_METER30_BUCKET_SIZE 0x161e #define RTL8367C_REG_METER31_BUCKET_SIZE 0x161f #define RTL8367C_REG_METER_CTRL0 0x1700 #define RTL8367C_METER_OP_OFFSET 8 #define RTL8367C_METER_OP_MASK 0x100 #define RTL8367C_METER_TICK_OFFSET 0 #define RTL8367C_METER_TICK_MASK 0xFF #define RTL8367C_REG_METER_CTRL1 0x1701 #define RTL8367C_METER_CTRL1_OFFSET 0 #define RTL8367C_METER_CTRL1_MASK 0xFF #define RTL8367C_REG_METER_OVERRATE_INDICATOR0 0x1702 #define RTL8367C_REG_METER_OVERRATE_INDICATOR1 0x1703 #define RTL8367C_REG_METER_OVERRATE_INDICATOR0_8051 0x1704 #define RTL8367C_REG_METER_OVERRATE_INDICATOR1_8051 0x1705 #define RTL8367C_REG_METER_IFG_CTRL0 0x1712 #define RTL8367C_METER15_IFG_OFFSET 15 #define RTL8367C_METER15_IFG_MASK 0x8000 #define RTL8367C_METER14_IFG_OFFSET 14 #define RTL8367C_METER14_IFG_MASK 0x4000 #define RTL8367C_METER13_IFG_OFFSET 13 #define RTL8367C_METER13_IFG_MASK 0x2000 #define RTL8367C_METER12_IFG_OFFSET 12 #define RTL8367C_METER12_IFG_MASK 0x1000 #define RTL8367C_METER11_IFG_OFFSET 11 #define RTL8367C_METER11_IFG_MASK 0x800 #define RTL8367C_METER10_IFG_OFFSET 10 #define RTL8367C_METER10_IFG_MASK 0x400 #define RTL8367C_METER9_IFG_OFFSET 9 #define RTL8367C_METER9_IFG_MASK 0x200 #define RTL8367C_METER8_IFG_OFFSET 8 #define RTL8367C_METER8_IFG_MASK 0x100 #define RTL8367C_METER7_IFG_OFFSET 7 #define RTL8367C_METER7_IFG_MASK 0x80 #define RTL8367C_METER6_IFG_OFFSET 6 #define RTL8367C_METER6_IFG_MASK 0x40 #define RTL8367C_METER5_IFG_OFFSET 5 #define RTL8367C_METER5_IFG_MASK 0x20 #define RTL8367C_METER4_IFG_OFFSET 4 #define RTL8367C_METER4_IFG_MASK 0x10 #define RTL8367C_METER3_IFG_OFFSET 3 #define RTL8367C_METER3_IFG_MASK 0x8 #define RTL8367C_METER2_IFG_OFFSET 2 #define RTL8367C_METER2_IFG_MASK 0x4 #define RTL8367C_METER1_IFG_OFFSET 1 #define RTL8367C_METER1_IFG_MASK 0x2 #define RTL8367C_METER0_IFG_OFFSET 0 #define RTL8367C_METER0_IFG_MASK 0x1 #define RTL8367C_REG_METER_IFG_CTRL1 0x1713 #define RTL8367C_METER31_IFG_OFFSET 15 #define RTL8367C_METER31_IFG_MASK 0x8000 #define RTL8367C_METER30_IFG_OFFSET 14 #define RTL8367C_METER30_IFG_MASK 0x4000 #define RTL8367C_METER29_IFG_OFFSET 13 #define RTL8367C_METER29_IFG_MASK 0x2000 #define RTL8367C_METER28_IFG_OFFSET 12 #define RTL8367C_METER28_IFG_MASK 0x1000 #define RTL8367C_METER27_IFG_OFFSET 11 #define RTL8367C_METER27_IFG_MASK 0x800 #define RTL8367C_METER26_IFG_OFFSET 10 #define RTL8367C_METER26_IFG_MASK 0x400 #define RTL8367C_METER25_IFG_OFFSET 9 #define RTL8367C_METER25_IFG_MASK 0x200 #define RTL8367C_METER24_IFG_OFFSET 8 #define RTL8367C_METER24_IFG_MASK 0x100 #define RTL8367C_METER23_IFG_OFFSET 7 #define RTL8367C_METER23_IFG_MASK 0x80 #define RTL8367C_METER22_IFG_OFFSET 6 #define RTL8367C_METER22_IFG_MASK 0x40 #define RTL8367C_METER21_IFG_OFFSET 5 #define RTL8367C_METER21_IFG_MASK 0x20 #define RTL8367C_METER20_IFG_OFFSET 4 #define RTL8367C_METER20_IFG_MASK 0x10 #define RTL8367C_METER19_IFG_OFFSET 3 #define RTL8367C_METER19_IFG_MASK 0x8 #define RTL8367C_METER18_IFG_OFFSET 2 #define RTL8367C_METER18_IFG_MASK 0x4 #define RTL8367C_METER17_IFG_OFFSET 1 #define RTL8367C_METER17_IFG_MASK 0x2 #define RTL8367C_METER16_IFG_OFFSET 0 #define RTL8367C_METER16_IFG_MASK 0x1 #define RTL8367C_REG_METER_CTRL2 0x1722 #define RTL8367C_cfg_mtr_tick_8g_OFFSET 8 #define RTL8367C_cfg_mtr_tick_8g_MASK 0xFF00 #define RTL8367C_cfg_mtr_dec_cnt_8g_OFFSET 0 #define RTL8367C_cfg_mtr_dec_cnt_8g_MASK 0xFF #define RTL8367C_REG_DUMMY_1723 0x1723 #define RTL8367C_REG_DUMMY_1724 0x1724 #define RTL8367C_REG_DUMMY_1725 0x1725 #define RTL8367C_REG_DUMMY_1726 0x1726 #define RTL8367C_REG_DUMMY_1727 0x1727 #define RTL8367C_REG_DUMMY_1728 0x1728 #define RTL8367C_REG_DUMMY_1729 0x1729 #define RTL8367C_REG_DUMMY_172A 0x172a #define RTL8367C_REG_DUMMY_172B 0x172b #define RTL8367C_REG_DUMMY_172C 0x172c #define RTL8367C_REG_DUMMY_172D 0x172d #define RTL8367C_REG_DUMMY_172E 0x172e #define RTL8367C_REG_DUMMY_172F 0x172f #define RTL8367C_REG_DUMMY_1730 0x1730 #define RTL8367C_REG_DUMMY_1731 0x1731 #define RTL8367C_REG_METER32_RATE_CTRL0 0x1740 #define RTL8367C_REG_METER32_RATE_CTRL1 0x1741 #define RTL8367C_METER32_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER32_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER33_RATE_CTRL0 0x1742 #define RTL8367C_REG_METER33_RATE_CTRL1 0x1743 #define RTL8367C_METER33_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER33_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER34_RATE_CTRL0 0x1744 #define RTL8367C_REG_METER34_RATE_CTRL1 0x1745 #define RTL8367C_METER34_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER34_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER35_RATE_CTRL0 0x1746 #define RTL8367C_REG_METER35_RATE_CTRL1 0x1747 #define RTL8367C_METER35_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER35_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER36_RATE_CTRL0 0x1748 #define RTL8367C_REG_METER36_RATE_CTRL1 0x1749 #define RTL8367C_METER36_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER36_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER37_RATE_CTRL0 0x174a #define RTL8367C_REG_METER37_RATE_CTRL1 0x174b #define RTL8367C_METER37_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER37_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER38_RATE_CTRL0 0x174c #define RTL8367C_REG_METER38_RATE_CTRL1 0x174d #define RTL8367C_METER38_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER38_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER39_RATE_CTRL0 0x174e #define RTL8367C_REG_METER39_RATE_CTRL1 0x174f #define RTL8367C_METER39_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER39_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER40_RATE_CTRL0 0x1750 #define RTL8367C_REG_METER40_RATE_CTRL1 0x1751 #define RTL8367C_METER40_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER40_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER41_RATE_CTRL0 0x1752 #define RTL8367C_REG_METER41_RATE_CTRL1 0x1753 #define RTL8367C_METER41_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER41_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER42_RATE_CTRL0 0x1754 #define RTL8367C_REG_METER42_RATE_CTRL1 0x1755 #define RTL8367C_METER42_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER42_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER43_RATE_CTRL0 0x1756 #define RTL8367C_REG_METER43_RATE_CTRL1 0x1757 #define RTL8367C_METER43_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER43_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER44_RATE_CTRL0 0x1758 #define RTL8367C_REG_METER44_RATE_CTRL1 0x1759 #define RTL8367C_METER44_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER44_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER45_RATE_CTRL0 0x175a #define RTL8367C_REG_METER45_RATE_CTRL1 0x175b #define RTL8367C_METER45_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER45_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER46_RATE_CTRL0 0x175c #define RTL8367C_REG_METER46_RATE_CTRL1 0x175d #define RTL8367C_METER46_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER46_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER47_RATE_CTRL0 0x175e #define RTL8367C_REG_METER47_RATE_CTRL1 0x175f #define RTL8367C_METER47_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER47_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER48_RATE_CTRL0 0x1760 #define RTL8367C_REG_METER48_RATE_CTRL1 0x1761 #define RTL8367C_METER48_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER48_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER49_RATE_CTRL0 0x1762 #define RTL8367C_REG_METER49_RATE_CTRL1 0x1763 #define RTL8367C_METER49_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER49_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER50_RATE_CTRL0 0x1764 #define RTL8367C_REG_METER50_RATE_CTRL1 0x1765 #define RTL8367C_METER50_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER50_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER51_RATE_CTRL0 0x1766 #define RTL8367C_REG_METER51_RATE_CTRL1 0x1767 #define RTL8367C_METER51_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER51_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER52_RATE_CTRL0 0x1768 #define RTL8367C_REG_METER52_RATE_CTRL1 0x1769 #define RTL8367C_METER52_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER52_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER53_RATE_CTRL0 0x176a #define RTL8367C_REG_METER53_RATE_CTRL1 0x176b #define RTL8367C_METER53_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER53_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER54_RATE_CTRL0 0x176c #define RTL8367C_REG_METER54_RATE_CTRL1 0x176d #define RTL8367C_METER54_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER54_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER55_RATE_CTRL0 0x176e #define RTL8367C_REG_METER55_RATE_CTRL1 0x176f #define RTL8367C_METER55_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER55_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER56_RATE_CTRL0 0x1770 #define RTL8367C_REG_METER56_RATE_CTRL1 0x1771 #define RTL8367C_METER56_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER56_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER57_RATE_CTRL0 0x1772 #define RTL8367C_REG_METER57_RATE_CTRL1 0x1773 #define RTL8367C_METER57_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER57_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER58_RATE_CTRL0 0x1774 #define RTL8367C_REG_METER58_RATE_CTRL1 0x1775 #define RTL8367C_METER58_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER58_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER59_RATE_CTRL0 0x1776 #define RTL8367C_REG_METER59_RATE_CTRL1 0x1777 #define RTL8367C_METER59_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER59_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER60_RATE_CTRL0 0x1778 #define RTL8367C_REG_METER60_RATE_CTRL1 0x1779 #define RTL8367C_METER60_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER60_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER61_RATE_CTRL0 0x177a #define RTL8367C_REG_METER61_RATE_CTRL1 0x177b #define RTL8367C_METER61_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER61_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER62_RATE_CTRL0 0x177c #define RTL8367C_REG_METER62_RATE_CTRL1 0x177d #define RTL8367C_METER62_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER62_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER63_RATE_CTRL0 0x177e #define RTL8367C_REG_METER63_RATE_CTRL1 0x177f #define RTL8367C_METER63_RATE_CTRL1_OFFSET 0 #define RTL8367C_METER63_RATE_CTRL1_MASK 0x7 #define RTL8367C_REG_METER_MODE_SETTING2 0x1780 #define RTL8367C_REG_METER_MODE_SETTING3 0x1781 #define RTL8367C_REG_METER32_BUCKET_SIZE 0x1790 #define RTL8367C_REG_METER33_BUCKET_SIZE 0x1791 #define RTL8367C_REG_METER34_BUCKET_SIZE 0x1792 #define RTL8367C_REG_METER35_BUCKET_SIZE 0x1793 #define RTL8367C_REG_METER36_BUCKET_SIZE 0x1794 #define RTL8367C_REG_METER37_BUCKET_SIZE 0x1795 #define RTL8367C_REG_METER38_BUCKET_SIZE 0x1796 #define RTL8367C_REG_METER39_BUCKET_SIZE 0x1797 #define RTL8367C_REG_METER40_BUCKET_SIZE 0x1798 #define RTL8367C_REG_METER41_BUCKET_SIZE 0x1799 #define RTL8367C_REG_METER42_BUCKET_SIZE 0x179a #define RTL8367C_REG_METER43_BUCKET_SIZE 0x179b #define RTL8367C_REG_METER44_BUCKET_SIZE 0x179c #define RTL8367C_REG_METER45_BUCKET_SIZE 0x179d #define RTL8367C_REG_METER46_BUCKET_SIZE 0x179e #define RTL8367C_REG_METER47_BUCKET_SIZE 0x179f #define RTL8367C_REG_METER48_BUCKET_SIZE 0x17a0 #define RTL8367C_REG_METER49_BUCKET_SIZE 0x17a1 #define RTL8367C_REG_METER50_BUCKET_SIZE 0x17a2 #define RTL8367C_REG_METER51_BUCKET_SIZE 0x17a3 #define RTL8367C_REG_METER52_BUCKET_SIZE 0x17a4 #define RTL8367C_REG_METER53_BUCKET_SIZE 0x17a5 #define RTL8367C_REG_METER54_BUCKET_SIZE 0x17a6 #define RTL8367C_REG_METER55_BUCKET_SIZE 0x17a7 #define RTL8367C_REG_METER56_BUCKET_SIZE 0x17a8 #define RTL8367C_REG_METER57_BUCKET_SIZE 0x17a9 #define RTL8367C_REG_METER58_BUCKET_SIZE 0x17aa #define RTL8367C_REG_METER59_BUCKET_SIZE 0x17ab #define RTL8367C_REG_METER60_BUCKET_SIZE 0x17ac #define RTL8367C_REG_METER61_BUCKET_SIZE 0x17ad #define RTL8367C_REG_METER62_BUCKET_SIZE 0x17ae #define RTL8367C_REG_METER63_BUCKET_SIZE 0x17af #define RTL8367C_REG_METER_OVERRATE_INDICATOR2 0x17b0 #define RTL8367C_REG_METER_OVERRATE_INDICATOR3 0x17b1 #define RTL8367C_REG_METER_OVERRATE_INDICATOR2_8051 0x17b2 #define RTL8367C_REG_METER_OVERRATE_INDICATOR3_8051 0x17b3 #define RTL8367C_REG_METER_IFG_CTRL2 0x17b4 #define RTL8367C_METER47_IFG_OFFSET 15 #define RTL8367C_METER47_IFG_MASK 0x8000 #define RTL8367C_METER46_IFG_OFFSET 14 #define RTL8367C_METER46_IFG_MASK 0x4000 #define RTL8367C_METER45_IFG_OFFSET 13 #define RTL8367C_METER45_IFG_MASK 0x2000 #define RTL8367C_METER44_IFG_OFFSET 12 #define RTL8367C_METER44_IFG_MASK 0x1000 #define RTL8367C_METER43_IFG_OFFSET 11 #define RTL8367C_METER43_IFG_MASK 0x800 #define RTL8367C_METER42_IFG_OFFSET 10 #define RTL8367C_METER42_IFG_MASK 0x400 #define RTL8367C_METER41_IFG_OFFSET 9 #define RTL8367C_METER41_IFG_MASK 0x200 #define RTL8367C_METER40_IFG_OFFSET 8 #define RTL8367C_METER40_IFG_MASK 0x100 #define RTL8367C_METER39_IFG_OFFSET 7 #define RTL8367C_METER39_IFG_MASK 0x80 #define RTL8367C_METER38_IFG_OFFSET 6 #define RTL8367C_METER38_IFG_MASK 0x40 #define RTL8367C_METER37_IFG_OFFSET 5 #define RTL8367C_METER37_IFG_MASK 0x20 #define RTL8367C_METER36_IFG_OFFSET 4 #define RTL8367C_METER36_IFG_MASK 0x10 #define RTL8367C_METER35_IFG_OFFSET 3 #define RTL8367C_METER35_IFG_MASK 0x8 #define RTL8367C_METER34_IFG_OFFSET 2 #define RTL8367C_METER34_IFG_MASK 0x4 #define RTL8367C_METER33_IFG_OFFSET 1 #define RTL8367C_METER33_IFG_MASK 0x2 #define RTL8367C_METER32_IFG_OFFSET 0 #define RTL8367C_METER32_IFG_MASK 0x1 #define RTL8367C_REG_METER_IFG_CTRL3 0x17b5 #define RTL8367C_METER63_IFG_OFFSET 15 #define RTL8367C_METER63_IFG_MASK 0x8000 #define RTL8367C_METER62_IFG_OFFSET 14 #define RTL8367C_METER62_IFG_MASK 0x4000 #define RTL8367C_METER61_IFG_OFFSET 13 #define RTL8367C_METER61_IFG_MASK 0x2000 #define RTL8367C_METER60_IFG_OFFSET 12 #define RTL8367C_METER60_IFG_MASK 0x1000 #define RTL8367C_METER59_IFG_OFFSET 11 #define RTL8367C_METER59_IFG_MASK 0x800 #define RTL8367C_METER58_IFG_OFFSET 10 #define RTL8367C_METER58_IFG_MASK 0x400 #define RTL8367C_METER57_IFG_OFFSET 9 #define RTL8367C_METER57_IFG_MASK 0x200 #define RTL8367C_METER56_IFG_OFFSET 8 #define RTL8367C_METER56_IFG_MASK 0x100 #define RTL8367C_METER55_IFG_OFFSET 7 #define RTL8367C_METER55_IFG_MASK 0x80 #define RTL8367C_METER54_IFG_OFFSET 6 #define RTL8367C_METER54_IFG_MASK 0x40 #define RTL8367C_METER53_IFG_OFFSET 5 #define RTL8367C_METER53_IFG_MASK 0x20 #define RTL8367C_METER52_IFG_OFFSET 4 #define RTL8367C_METER52_IFG_MASK 0x10 #define RTL8367C_METER51_IFG_OFFSET 3 #define RTL8367C_METER51_IFG_MASK 0x8 #define RTL8367C_METER50_IFG_OFFSET 2 #define RTL8367C_METER50_IFG_MASK 0x4 #define RTL8367C_METER49_IFG_OFFSET 1 #define RTL8367C_METER49_IFG_MASK 0x2 #define RTL8367C_METER48_IFG_OFFSET 0 #define RTL8367C_METER48_IFG_MASK 0x1 #define RTL8367C_REG_METER_MISC 0x17b6 #define RTL8367C_METER_MISC_OFFSET 0 #define RTL8367C_METER_MISC_MASK 0x1 /* (16'h1800)8051_RLDP_EEE_reg */ #define RTL8367C_REG_EEELLDP_CTRL0 0x1820 #define RTL8367C_EEELLDP_SUBTYPE_OFFSET 6 #define RTL8367C_EEELLDP_SUBTYPE_MASK 0x3FC0 #define RTL8367C_EEELLDP_TRAP_8051_OFFSET 2 #define RTL8367C_EEELLDP_TRAP_8051_MASK 0x4 #define RTL8367C_EEELLDP_TRAP_CPU_OFFSET 1 #define RTL8367C_EEELLDP_TRAP_CPU_MASK 0x2 #define RTL8367C_EEELLDP_ENABLE_OFFSET 0 #define RTL8367C_EEELLDP_ENABLE_MASK 0x1 #define RTL8367C_REG_EEELLDP_PMSK 0x1822 #define RTL8367C_EEELLDP_PMSK_OFFSET 0 #define RTL8367C_EEELLDP_PMSK_MASK 0x7FF #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_08 0x1843 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_07 0x1844 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_06 0x1845 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_05 0x1846 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_04 0x1847 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_03 0x1848 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_02 0x1849 #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_01 0x184a #define RTL8367C_REG_EEELLDP_RX_VALUE_P00_00 0x184b #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_08 0x184c #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_07 0x184d #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_06 0x184e #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_05 0x184f #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_04 0x1850 #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_03 0x1851 #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_02 0x1852 #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_01 0x1853 #define RTL8367C_REG_EEELLDP_RX_VALUE_P01_00 0x1854 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_08 0x1855 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_07 0x1856 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_06 0x1857 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_05 0x1858 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_04 0x1859 #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_03 0x185a #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_02 0x185b #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_01 0x185c #define RTL8367C_REG_EEELLDP_RX_VALUE_P02_00 0x185d #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_08 0x185e #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_07 0x185f #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_06 0x1860 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_05 0x1861 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_04 0x1862 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_03 0x1863 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_02 0x1864 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_01 0x1865 #define RTL8367C_REG_EEELLDP_RX_VALUE_P03_00 0x1866 #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_08 0x1867 #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_07 0x1868 #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_06 0x1869 #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_05 0x186a #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_04 0x186b #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_03 0x186c #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_02 0x186d #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_01 0x186e #define RTL8367C_REG_EEELLDP_RX_VALUE_P04_00 0x186f #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_08 0x1870 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_07 0x1871 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_06 0x1872 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_05 0x1873 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_04 0x1874 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_03 0x1875 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_02 0x1876 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_01 0x1877 #define RTL8367C_REG_EEELLDP_RX_VALUE_P05_00 0x1878 #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_08 0x1879 #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_07 0x187a #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_06 0x187b #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_05 0x187c #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_04 0x187d #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_03 0x187e #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_02 0x187f #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_01 0x1880 #define RTL8367C_REG_EEELLDP_RX_VALUE_P06_00 0x1881 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_08 0x1882 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_07 0x1883 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_06 0x1884 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_05 0x1885 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_04 0x1886 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_03 0x1887 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_02 0x1888 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_01 0x1889 #define RTL8367C_REG_EEELLDP_RX_VALUE_P07_00 0x188a #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_08 0x188b #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_07 0x188c #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_06 0x188d #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_05 0x188e #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_04 0x188f #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_03 0x1890 #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_02 0x1891 #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_01 0x1892 #define RTL8367C_REG_EEELLDP_RX_VALUE_P08_00 0x1893 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_08 0x1894 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_07 0x1895 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_06 0x1896 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_05 0x1897 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_04 0x1898 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_03 0x1899 #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_02 0x189a #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_01 0x189b #define RTL8367C_REG_EEELLDP_RX_VALUE_P09_00 0x189c #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_08 0x189d #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_07 0x189e #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_06 0x189f #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_05 0x18a0 #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_04 0x18a1 #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_03 0x18a2 #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_02 0x18a3 #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_01 0x18a4 #define RTL8367C_REG_EEELLDP_RX_VALUE_P10_00 0x18a5 #define RTL8367C_REG_RLDP_CTRL0 0x18e0 #define RTL8367C_RLDP_TRIGGER_MODE_OFFSET 14 #define RTL8367C_RLDP_TRIGGER_MODE_MASK 0x4000 #define RTL8367C_RLDP_8051_LOOP_PORTMSK_OFFSET 6 #define RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK 0x3FC0 #define RTL8367C_RLPP_8051_TRAP_OFFSET 5 #define RTL8367C_RLPP_8051_TRAP_MASK 0x20 #define RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET 4 #define RTL8367C_RLDP_INDICATOR_SOURCE_MASK 0x10 #define RTL8367C_RLDP_GEN_RANDOM_OFFSET 3 #define RTL8367C_RLDP_GEN_RANDOM_MASK 0x8 #define RTL8367C_RLDP_COMP_ID_OFFSET 2 #define RTL8367C_RLDP_COMP_ID_MASK 0x4 #define RTL8367C_RLDP_8051_ENABLE_OFFSET 1 #define RTL8367C_RLDP_8051_ENABLE_MASK 0x2 #define RTL8367C_RLDP_ENABLE_OFFSET 0 #define RTL8367C_RLDP_ENABLE_MASK 0x1 #define RTL8367C_REG_RLDP_CTRL1 0x18e1 #define RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET 8 #define RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK 0xFF00 #define RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_OFFSET 0 #define RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK 0xFF #define RTL8367C_REG_RLDP_CTRL2 0x18e2 #define RTL8367C_REG_RLDP_CTRL3 0x18e3 #define RTL8367C_REG_RLDP_CTRL4 0x18e4 #define RTL8367C_RLDP_CTRL4_OFFSET 0 #define RTL8367C_RLDP_CTRL4_MASK 0x7FF #define RTL8367C_REG_RLDP_RAND_NUM0 0x18e5 #define RTL8367C_REG_RLDP_RAND_NUM1 0x18e6 #define RTL8367C_REG_RLDP_RAND_NUM2 0x18e7 #define RTL8367C_REG_RLDP_MAGIC_NUM0 0x18e8 #define RTL8367C_REG_RLDP_MAGIC_NUM1 0x18e9 #define RTL8367C_REG_RLDP_MAGIC_NUM2 0x18ea #define RTL8367C_REG_RLDP_LOOPED_INDICATOR 0x18eb #define RTL8367C_RLDP_LOOPED_INDICATOR_OFFSET 0 #define RTL8367C_RLDP_LOOPED_INDICATOR_MASK 0x7FF #define RTL8367C_REG_RLDP_LOOP_PORT_REG0 0x18ec #define RTL8367C_RLDP_LOOP_PORT_01_OFFSET 8 #define RTL8367C_RLDP_LOOP_PORT_01_MASK 0xF00 #define RTL8367C_RLDP_LOOP_PORT_00_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_00_MASK 0xF #define RTL8367C_REG_RLDP_LOOP_PORT_REG1 0x18ed #define RTL8367C_RLDP_LOOP_PORT_03_OFFSET 8 #define RTL8367C_RLDP_LOOP_PORT_03_MASK 0xF00 #define RTL8367C_RLDP_LOOP_PORT_02_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_02_MASK 0xF #define RTL8367C_REG_RLDP_LOOP_PORT_REG2 0x18ee #define RTL8367C_RLDP_LOOP_PORT_05_OFFSET 8 #define RTL8367C_RLDP_LOOP_PORT_05_MASK 0xF00 #define RTL8367C_RLDP_LOOP_PORT_04_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_04_MASK 0xF #define RTL8367C_REG_RLDP_LOOP_PORT_REG3 0x18ef #define RTL8367C_RLDP_LOOP_PORT_07_OFFSET 8 #define RTL8367C_RLDP_LOOP_PORT_07_MASK 0xF00 #define RTL8367C_RLDP_LOOP_PORT_06_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_06_MASK 0xF #define RTL8367C_REG_RLDP_RELEASED_INDICATOR 0x18f0 #define RTL8367C_RLDP_RELEASED_INDICATOR_OFFSET 0 #define RTL8367C_RLDP_RELEASED_INDICATOR_MASK 0x7FF #define RTL8367C_REG_RLDP_LOOPSTATUS_INDICATOR 0x18f1 #define RTL8367C_RLDP_LOOPSTATUS_INDICATOR_OFFSET 0 #define RTL8367C_RLDP_LOOPSTATUS_INDICATOR_MASK 0x7FF #define RTL8367C_REG_RLDP_LOOP_PORT_REG4 0x18f2 #define RTL8367C_RLDP_LOOP_PORT_9_OFFSET 8 #define RTL8367C_RLDP_LOOP_PORT_9_MASK 0xF00 #define RTL8367C_RLDP_LOOP_PORT_8_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_8_MASK 0xF #define RTL8367C_REG_RLDP_LOOP_PORT_REG5 0x18f3 #define RTL8367C_RLDP_LOOP_PORT_REG5_OFFSET 0 #define RTL8367C_RLDP_LOOP_PORT_REG5_MASK 0xF #define RTL8367C_REG_RLDP_CTRL5 0x18f4 #define RTL8367C_RLDP_CTRL5_OFFSET 0 #define RTL8367C_RLDP_CTRL5_MASK 0x7 /* (16'h1900)EEE_EEEP_reg */ #define RTL8367C_REG_EEE_500M_CTRL0 0x1900 #define RTL8367C_EEE_500M_CTRL0_OFFSET 0 #define RTL8367C_EEE_500M_CTRL0_MASK 0xFF #define RTL8367C_REG_EEE_RXIDLE_GIGA_CTRL 0x1901 #define RTL8367C_EEE_RXIDLE_GIGA_EN_OFFSET 8 #define RTL8367C_EEE_RXIDLE_GIGA_EN_MASK 0x100 #define RTL8367C_EEE_RXIDLE_GIGA_OFFSET 0 #define RTL8367C_EEE_RXIDLE_GIGA_MASK 0xFF #define RTL8367C_REG_EEE_RXIDLE_500M_CTRL 0x1902 #define RTL8367C_EEE_RXIDLE_500M_EN_OFFSET 8 #define RTL8367C_EEE_RXIDLE_500M_EN_MASK 0x100 #define RTL8367C_EEE_RXIDLE_500M_OFFSET 0 #define RTL8367C_EEE_RXIDLE_500M_MASK 0xFF #define RTL8367C_REG_EEE_DECISION_GIGA_500M 0x1903 #define RTL8367C_EEE_DECISION_GIGA_OFFSET 8 #define RTL8367C_EEE_DECISION_GIGA_MASK 0xFF00 #define RTL8367C_EEE_DECISION_500M_OFFSET 0 #define RTL8367C_EEE_DECISION_500M_MASK 0xFF #define RTL8367C_REG_EEE_DECISION_100M 0x1904 #define RTL8367C_EEE_DECISION_100M_OFFSET 0 #define RTL8367C_EEE_DECISION_100M_MASK 0xFF #define RTL8367C_REG_EEEP_DEFER_TXLPI 0x1905 #define RTL8367C_EEEP_DEFER_TXLPI_OFFSET 0 #define RTL8367C_EEEP_DEFER_TXLPI_MASK 0x1 #define RTL8367C_REG_EEEP_EN 0x1906 #define RTL8367C_EEEP_SLAVE_EN_OFFSET 3 #define RTL8367C_EEEP_SLAVE_EN_MASK 0x8 #define RTL8367C_EEEP_100M_OFFSET 2 #define RTL8367C_EEEP_100M_MASK 0x4 #define RTL8367C_EEEP_500M_OFFSET 1 #define RTL8367C_EEEP_500M_MASK 0x2 #define RTL8367C_EEEP_GIGA_OFFSET 0 #define RTL8367C_EEEP_GIGA_MASK 0x1 #define RTL8367C_REG_EEEP_TI_GIGA_500M 0x1907 #define RTL8367C_EEEP_TI_GIGA_OFFSET 8 #define RTL8367C_EEEP_TI_GIGA_MASK 0xFF00 #define RTL8367C_EEEP_TI_500M_OFFSET 0 #define RTL8367C_EEEP_TI_500M_MASK 0xFF #define RTL8367C_REG_EEEP_TI_100M 0x1908 #define RTL8367C_EEEP_TI_100M_OFFSET 0 #define RTL8367C_EEEP_TI_100M_MASK 0xFF #define RTL8367C_REG_EEEP_CTRL2 0x1909 #define RTL8367C_EEEP_CTRL2_OFFSET 0 #define RTL8367C_EEEP_CTRL2_MASK 0xFF #define RTL8367C_REG_EEEP_RX_RATE_500M 0x190b #define RTL8367C_REG_EEEP_RW_GIGA_SLV 0x190c #define RTL8367C_EEEP_RW_GIGA_SLV_OFFSET 0 #define RTL8367C_EEEP_RW_GIGA_SLV_MASK 0xFF #define RTL8367C_REG_EEEP_TMR_GIGA 0x190d #define RTL8367C_RX_IDLE_EEEP_GIGA_OFFSET 8 #define RTL8367C_RX_IDLE_EEEP_GIGA_MASK 0xFF00 #define RTL8367C_RX_MIN_SLP_TMR_GIGA_OFFSET 0 #define RTL8367C_RX_MIN_SLP_TMR_GIGA_MASK 0xFF #define RTL8367C_REG_EEEP_TMR_500M 0x190e #define RTL8367C_RX_IDLE_EEEP_500M_OFFSET 8 #define RTL8367C_RX_IDLE_EEEP_500M_MASK 0xFF00 #define RTL8367C_RX_MIN_SLP_TMR_500M_OFFSET 0 #define RTL8367C_RX_MIN_SLP_TMR_500M_MASK 0xFF #define RTL8367C_REG_EEEP_TMR_100M 0x190f #define RTL8367C_RX_IDLE_EEEP_100M_OFFSET 8 #define RTL8367C_RX_IDLE_EEEP_100M_MASK 0xFF00 #define RTL8367C_RX_MIN_SLP_TMR_100M_OFFSET 0 #define RTL8367C_RX_MIN_SLP_TMR_100M_MASK 0xFF #define RTL8367C_REG_EEEP_RW_500M_MST_SLV 0x1910 #define RTL8367C_EEEP_RW_500M_MST_OFFSET 8 #define RTL8367C_EEEP_RW_500M_MST_MASK 0xFF00 #define RTL8367C_EEEP_RW_500M_SLV_OFFSET 0 #define RTL8367C_EEEP_RW_500M_SLV_MASK 0xFF #define RTL8367C_REG_EEEP_500M_CTRL0 0x1911 #define RTL8367C_EEEP_500M_CTRL0_OFFSET 0 #define RTL8367C_EEEP_500M_CTRL0_MASK 0xFF #define RTL8367C_REG_EEEP_500M_CTRL1 0x1912 #define RTL8367C_EEEP_TW_500M_OFFSET 8 #define RTL8367C_EEEP_TW_500M_MASK 0xFF00 #define RTL8367C_EEEP_TP_500M_OFFSET 0 #define RTL8367C_EEEP_TP_500M_MASK 0xFF #define RTL8367C_REG_EEEP_500M_CTRL2 0x1913 #define RTL8367C_EEEP_TXEN_500M_OFFSET 12 #define RTL8367C_EEEP_TXEN_500M_MASK 0x1000 #define RTL8367C_EEEP_TU_500M_OFFSET 8 #define RTL8367C_EEEP_TU_500M_MASK 0x300 #define RTL8367C_EEEP_TS_500M_OFFSET 0 #define RTL8367C_EEEP_TS_500M_MASK 0xFF #define RTL8367C_REG_EEE_NEW_CTRL0 0x1914 #define RTL8367C_LINK_UP_DELAY_OFFSET 3 #define RTL8367C_LINK_UP_DELAY_MASK 0x18 #define RTL8367C_EEE_TXLPI_ORI_OFFSET 2 #define RTL8367C_EEE_TXLPI_ORI_MASK 0x4 #define RTL8367C_REALTX_SEL_OFFSET 1 #define RTL8367C_REALTX_SEL_MASK 0x2 #define RTL8367C_EN_FC_EFCT_OFFSET 0 #define RTL8367C_EN_FC_EFCT_MASK 0x1 #define RTL8367C_REG_EEE_LONGIDLE_100M 0x1915 #define RTL8367C_EEE_LONGIDLE_100M_OFFSET 0 #define RTL8367C_EEE_LONGIDLE_100M_MASK 0x3FF #define RTL8367C_REG_EEE_LONGIDLE_500M 0x1916 #define RTL8367C_EEE_LONGIDLE_500M_OFFSET 0 #define RTL8367C_EEE_LONGIDLE_500M_MASK 0x3FF #define RTL8367C_REG_EEE_LONGIDLE_GIGA 0x1917 #define RTL8367C_EEE_LONGIDLE_GIGA_OFFSET 0 #define RTL8367C_EEE_LONGIDLE_GIGA_MASK 0x3FF #define RTL8367C_REG_EEE_MINIPG_100M 0x1918 #define RTL8367C_REG_EEE_MINIPG_500M 0x1919 #define RTL8367C_REG_EEE_MINIPG_GIGA 0x191A #define RTL8367C_REG_EEE_LONGIDLE_CTRL0 0x191B #define RTL8367C_TX_IDLEN_REQ_100M_OFFSET 10 #define RTL8367C_TX_IDLEN_REQ_100M_MASK 0x400 #define RTL8367C_TX_IDLEN_REQ_500M_OFFSET 9 #define RTL8367C_TX_IDLEN_REQ_500M_MASK 0x200 #define RTL8367C_TX_IDLEN_REQ_GIGA_OFFSET 8 #define RTL8367C_TX_IDLEN_REQ_GIGA_MASK 0x100 #define RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_OFFSET 0 #define RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_MASK 0xFF #define RTL8367C_REG_EEE_LONGIDLE_CTRL1 0x191C #define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_OFFSET 8 #define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_MASK 0xFF00 #define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_OFFSET 0 #define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_MASK 0xFF #define RTL8367C_REG_EEE_TD_CTRL_H 0x191d #define RTL8367C_REF_RXLPI_OFFSET 8 #define RTL8367C_REF_RXLPI_MASK 0x100 #define RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_OFFSET 4 #define RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_MASK 0xF0 #define RTL8367C_LOW_Q_TX_DELAY_FE_H_OFFSET 0 #define RTL8367C_LOW_Q_TX_DELAY_FE_H_MASK 0xF /* (16'h1a00)nic_reg */ #define RTL8367C_REG_NIC_RXRDRL 0x1a04 #define RTL8367C_NIC_RXRDRL_OFFSET 0 #define RTL8367C_NIC_RXRDRL_MASK 0xFF #define RTL8367C_REG_NIC_RXRDRH 0x1a05 #define RTL8367C_NIC_RXRDRH_OFFSET 0 #define RTL8367C_NIC_RXRDRH_MASK 0xFF #define RTL8367C_REG_NIC_TXASRL 0x1a08 #define RTL8367C_NIC_TXASRL_OFFSET 0 #define RTL8367C_NIC_TXASRL_MASK 0xFF #define RTL8367C_REG_NIC_TXASRH 0x1a09 #define RTL8367C_NIC_TXASRH_OFFSET 0 #define RTL8367C_NIC_TXASRH_MASK 0xFF #define RTL8367C_REG_NIC_RXCMDR 0x1a0c #define RTL8367C_NIC_RXCMDR_OFFSET 0 #define RTL8367C_NIC_RXCMDR_MASK 0x1 #define RTL8367C_REG_NIC_TXCMDR 0x1a0d #define RTL8367C_NIC_TXCMDR_OFFSET 0 #define RTL8367C_NIC_TXCMDR_MASK 0x1 #define RTL8367C_REG_NIC_IMS 0x1a0e #define RTL8367C_NIC_RXIS_OFFSET 7 #define RTL8367C_NIC_RXIS_MASK 0x80 #define RTL8367C_NIC_TXIS_OFFSET 6 #define RTL8367C_NIC_TXIS_MASK 0x40 #define RTL8367C_NIC_TXES_OFFSET 5 #define RTL8367C_NIC_TXES_MASK 0x20 #define RTL8367C_NIC_IMS_DMY_OFFSET 4 #define RTL8367C_NIC_IMS_DMY_MASK 0x10 #define RTL8367C_NIC_RXBUS_OFFSET 3 #define RTL8367C_NIC_RXBUS_MASK 0x8 #define RTL8367C_NIC_TXBOS_OFFSET 2 #define RTL8367C_NIC_TXBOS_MASK 0x4 #define RTL8367C_NIC_RXMIS_OFFSET 1 #define RTL8367C_NIC_RXMIS_MASK 0x2 #define RTL8367C_NIC_TXNLS_OFFSET 0 #define RTL8367C_NIC_TXNLS_MASK 0x1 #define RTL8367C_REG_NIC_IMR 0x1a0f #define RTL8367C_NIC_RXIE_OFFSET 7 #define RTL8367C_NIC_RXIE_MASK 0x80 #define RTL8367C_NIC_TXIE_OFFSET 6 #define RTL8367C_NIC_TXIE_MASK 0x40 #define RTL8367C_NIC_TXEE_OFFSET 5 #define RTL8367C_NIC_TXEE_MASK 0x20 #define RTL8367C_NIC_IMR_DMY_OFFSET 4 #define RTL8367C_NIC_IMR_DMY_MASK 0x10 #define RTL8367C_NIC_RXBUE_OFFSET 3 #define RTL8367C_NIC_RXBUE_MASK 0x8 #define RTL8367C_NIC_TXBOE_OFFSET 2 #define RTL8367C_NIC_TXBOE_MASK 0x4 #define RTL8367C_NIC_RXMIE_OFFSET 1 #define RTL8367C_NIC_RXMIE_MASK 0x2 #define RTL8367C_NIC_TXNLE_OFFSET 0 #define RTL8367C_NIC_TXNLE_MASK 0x1 #define RTL8367C_REG_NIC_RXCR0 0x1a14 #define RTL8367C_NIC_HFPPE_OFFSET 7 #define RTL8367C_NIC_HFPPE_MASK 0x80 #define RTL8367C_NIC_HFMPE_OFFSET 6 #define RTL8367C_NIC_HFMPE_MASK 0x40 #define RTL8367C_NIC_RXBPE_OFFSET 5 #define RTL8367C_NIC_RXBPE_MASK 0x20 #define RTL8367C_NIC_RXMPE_OFFSET 4 #define RTL8367C_NIC_RXMPE_MASK 0x10 #define RTL8367C_NIC_RXPPS_OFFSET 2 #define RTL8367C_NIC_RXPPS_MASK 0xC #define RTL8367C_NIC_RXAPE_OFFSET 1 #define RTL8367C_NIC_RXAPE_MASK 0x2 #define RTL8367C_NIC_ARPPE_OFFSET 0 #define RTL8367C_NIC_ARPPE_MASK 0x1 #define RTL8367C_REG_NIC_RXCR1 0x1a15 #define RTL8367C_NIC_RL4CEPE_OFFSET 4 #define RTL8367C_NIC_RL4CEPE_MASK 0x10 #define RTL8367C_NIC_RL3CEPE_OFFSET 3 #define RTL8367C_NIC_RL3CEPE_MASK 0x8 #define RTL8367C_NIC_RCRCEPE_OFFSET 2 #define RTL8367C_NIC_RCRCEPE_MASK 0x4 #define RTL8367C_NIC_RMCRC_OFFSET 1 #define RTL8367C_NIC_RMCRC_MASK 0x2 #define RTL8367C_NIC_RXENABLE_OFFSET 0 #define RTL8367C_NIC_RXENABLE_MASK 0x1 #define RTL8367C_REG_NIC_TXCR 0x1a16 #define RTL8367C_NIC_LBE_OFFSET 2 #define RTL8367C_NIC_LBE_MASK 0x4 #define RTL8367C_NIC_TXMFM_OFFSET 1 #define RTL8367C_NIC_TXMFM_MASK 0x2 #define RTL8367C_NIC_TXENABLE_OFFSET 0 #define RTL8367C_NIC_TXENABLE_MASK 0x1 #define RTL8367C_REG_NIC_GCR 0x1a17 #define RTL8367C_DUMMY_7_6_OFFSET 6 #define RTL8367C_DUMMY_7_6_MASK 0xC0 #define RTL8367C_NIC_RXMTU_OFFSET 4 #define RTL8367C_NIC_RXMTU_MASK 0x30 #define RTL8367C_NIC_GCR_DUMMY_0_OFFSET 0 #define RTL8367C_NIC_GCR_DUMMY_0_MASK 0x1 #define RTL8367C_REG_NIC_MHR0 0x1a24 #define RTL8367C_NIC_MHR0_OFFSET 0 #define RTL8367C_NIC_MHR0_MASK 0xFF #define RTL8367C_REG_NIC_MHR1 0x1a25 #define RTL8367C_NIC_MHR1_OFFSET 0 #define RTL8367C_NIC_MHR1_MASK 0xFF #define RTL8367C_REG_NIC_MHR2 0x1a26 #define RTL8367C_NIC_MHR2_OFFSET 0 #define RTL8367C_NIC_MHR2_MASK 0xFF #define RTL8367C_REG_NIC_MHR3 0x1a27 #define RTL8367C_NIC_MHR3_OFFSET 0 #define RTL8367C_NIC_MHR3_MASK 0xFF #define RTL8367C_REG_NIC_MHR4 0x1a28 #define RTL8367C_NIC_MHR4_OFFSET 0 #define RTL8367C_NIC_MHR4_MASK 0xFF #define RTL8367C_REG_NIC_MHR5 0x1a29 #define RTL8367C_NIC_MHR5_OFFSET 0 #define RTL8367C_NIC_MHR5_MASK 0xFF #define RTL8367C_REG_NIC_MHR6 0x1a2a #define RTL8367C_NIC_MHR6_OFFSET 0 #define RTL8367C_NIC_MHR6_MASK 0xFF #define RTL8367C_REG_NIC_MHR7 0x1a2b #define RTL8367C_NIC_MHR7_OFFSET 0 #define RTL8367C_NIC_MHR7_MASK 0xFF #define RTL8367C_REG_NIC_PAHR0 0x1a2c #define RTL8367C_NIC_PAHR0_OFFSET 0 #define RTL8367C_NIC_PAHR0_MASK 0xFF #define RTL8367C_REG_NIC_PAHR1 0x1a2d #define RTL8367C_NIC_PAHR1_OFFSET 0 #define RTL8367C_NIC_PAHR1_MASK 0xFF #define RTL8367C_REG_NIC_PAHR2 0x1a2e #define RTL8367C_NIC_PAHR2_OFFSET 0 #define RTL8367C_NIC_PAHR2_MASK 0xFF #define RTL8367C_REG_NIC_PAHR3 0x1a2f #define RTL8367C_NIC_PAHR3_OFFSET 0 #define RTL8367C_NIC_PAHR3_MASK 0xFF #define RTL8367C_REG_NIC_PAHR4 0x1a30 #define RTL8367C_NIC_PAHR4_OFFSET 0 #define RTL8367C_NIC_PAHR4_MASK 0xFF #define RTL8367C_REG_NIC_PAHR5 0x1a31 #define RTL8367C_NIC_PAHR5_OFFSET 0 #define RTL8367C_NIC_PAHR5_MASK 0xFF #define RTL8367C_REG_NIC_PAHR6 0x1a32 #define RTL8367C_NIC_PAHR6_OFFSET 0 #define RTL8367C_NIC_PAHR6_MASK 0xFF #define RTL8367C_REG_NIC_PAHR7 0x1a33 #define RTL8367C_NIC_PAHR7_OFFSET 0 #define RTL8367C_NIC_PAHR7_MASK 0xFF #define RTL8367C_REG_NIC_TXSTOPRL 0x1a44 #define RTL8367C_NIC_TXSTOPRL_OFFSET 0 #define RTL8367C_NIC_TXSTOPRL_MASK 0xFF #define RTL8367C_REG_NIC_TXSTOPRH 0x1a45 #define RTL8367C_NIC_TXSTOPRH_OFFSET 0 #define RTL8367C_NIC_TXSTOPRH_MASK 0x3 #define RTL8367C_REG_NIC_RXSTOPRL 0x1a46 #define RTL8367C_NIC_RXSTOPRL_OFFSET 0 #define RTL8367C_NIC_RXSTOPRL_MASK 0xFF #define RTL8367C_REG_NIC_RXSTOPRH 0x1a47 #define RTL8367C_NIC_RXSTOPRH_OFFSET 0 #define RTL8367C_NIC_RXSTOPRH_MASK 0x3 #define RTL8367C_REG_NIC_RXFSTR 0x1a48 #define RTL8367C_NIC_RXFSTR_OFFSET 0 #define RTL8367C_NIC_RXFSTR_MASK 0xFF #define RTL8367C_REG_NIC_RXMBTRL 0x1a4c #define RTL8367C_NIC_RXMBTRL_OFFSET 0 #define RTL8367C_NIC_RXMBTRL_MASK 0xFF #define RTL8367C_REG_NIC_RXMBTRH 0x1a4d #define RTL8367C_NIC_RXMBTRH_OFFSET 0 #define RTL8367C_NIC_RXMBTRH_MASK 0x7F #define RTL8367C_REG_NIC_RXMPTR 0x1a4e #define RTL8367C_NIC_RXMPTR_OFFSET 0 #define RTL8367C_NIC_RXMPTR_MASK 0xFF #define RTL8367C_REG_NIC_T0TR 0x1a4f #define RTL8367C_NIC_T0TR_OFFSET 0 #define RTL8367C_NIC_T0TR_MASK 0xFF #define RTL8367C_REG_NIC_CRXCPRL 0x1a50 #define RTL8367C_NIC_CRXCPRL_OFFSET 0 #define RTL8367C_NIC_CRXCPRL_MASK 0xFF #define RTL8367C_REG_NIC_CRXCPRH 0x1a51 #define RTL8367C_NIC_CRXCPRH_OFFSET 0 #define RTL8367C_NIC_CRXCPRH_MASK 0xFF #define RTL8367C_REG_NIC_CTXCPRL 0x1a52 #define RTL8367C_NIC_CTXCPRL_OFFSET 0 #define RTL8367C_NIC_CTXCPRL_MASK 0xFF #define RTL8367C_REG_NIC_CTXPCRH 0x1a53 #define RTL8367C_NIC_CTXPCRH_OFFSET 0 #define RTL8367C_NIC_CTXPCRH_MASK 0xFF #define RTL8367C_REG_NIC_SRXCURPKTRL 0x1a54 #define RTL8367C_NIC_SRXCURPKTRL_OFFSET 0 #define RTL8367C_NIC_SRXCURPKTRL_MASK 0xFF #define RTL8367C_REG_NIC_SRXCURPKTRH 0x1a55 #define RTL8367C_NIC_SRXCURPKTRH_OFFSET 0 #define RTL8367C_NIC_SRXCURPKTRH_MASK 0xFF #define RTL8367C_REG_NIC_STXCURPKTRL 0x1a56 #define RTL8367C_NIC_STXCURPKTRL_OFFSET 0 #define RTL8367C_NIC_STXCURPKTRL_MASK 0xFF #define RTL8367C_REG_NIC_STXCURPKTRH 0x1a57 #define RTL8367C_NIC_STXCURPKTRH_OFFSET 0 #define RTL8367C_NIC_STXCURPKTRH_MASK 0xFF #define RTL8367C_REG_NIC_STXPKTLENRL 0x1a58 #define RTL8367C_NIC_STXPKTLENRL_OFFSET 0 #define RTL8367C_NIC_STXPKTLENRL_MASK 0xFF #define RTL8367C_REG_NIC_STXPKTLENRH 0x1a59 #define RTL8367C_NIC_STXPKTLENRH_OFFSET 0 #define RTL8367C_NIC_STXPKTLENRH_MASK 0xFF #define RTL8367C_REG_NIC_STXCURUNITRL 0x1a5a #define RTL8367C_NIC_STXCURUNITRL_OFFSET 0 #define RTL8367C_NIC_STXCURUNITRL_MASK 0xFF #define RTL8367C_REG_NIC_STXCURUNITRH 0x1a5b #define RTL8367C_NIC_STXCURUNITRH_OFFSET 0 #define RTL8367C_NIC_STXCURUNITRH_MASK 0xFF #define RTL8367C_REG_NIC_DROP_MODE 0x1a5c #define RTL8367C_NIC_RXDV_MODE_OFFSET 1 #define RTL8367C_NIC_RXDV_MODE_MASK 0x2 #define RTL8367C_NIC_DROP_MODE_OFFSET 0 #define RTL8367C_NIC_DROP_MODE_MASK 0x1 /* (16'h1b00)LED */ #define RTL8367C_REG_LED_SYS_CONFIG 0x1b00 #define RTL8367C_LED_SYS_CONFIG_DUMMY_15_OFFSET 15 #define RTL8367C_LED_SYS_CONFIG_DUMMY_15_MASK 0x8000 #define RTL8367C_LED_SERIAL_OUT_MODE_OFFSET 14 #define RTL8367C_LED_SERIAL_OUT_MODE_MASK 0x4000 #define RTL8367C_LED_EEE_LPI_MODE_OFFSET 13 #define RTL8367C_LED_EEE_LPI_MODE_MASK 0x2000 #define RTL8367C_LED_EEE_LPI_EN_OFFSET 12 #define RTL8367C_LED_EEE_LPI_EN_MASK 0x1000 #define RTL8367C_LED_EEE_LPI_10_OFFSET 11 #define RTL8367C_LED_EEE_LPI_10_MASK 0x800 #define RTL8367C_LED_EEE_CAP_10_OFFSET 10 #define RTL8367C_LED_EEE_CAP_10_MASK 0x400 #define RTL8367C_LED_LPI_SEL_OFFSET 8 #define RTL8367C_LED_LPI_SEL_MASK 0x300 #define RTL8367C_SERI_LED_ACT_LOW_OFFSET 7 #define RTL8367C_SERI_LED_ACT_LOW_MASK 0x80 #define RTL8367C_LED_POWERON_2_OFFSET 6 #define RTL8367C_LED_POWERON_2_MASK 0x40 #define RTL8367C_LED_POWERON_1_OFFSET 5 #define RTL8367C_LED_POWERON_1_MASK 0x20 #define RTL8367C_LED_POWERON_0_OFFSET 4 #define RTL8367C_LED_POWERON_0_MASK 0x10 #define RTL8367C_LED_IO_DISABLE_OFFSET 3 #define RTL8367C_LED_IO_DISABLE_MASK 0x8 #define RTL8367C_DUMMY_2_2_OFFSET 2 #define RTL8367C_DUMMY_2_2_MASK 0x4 #define RTL8367C_LED_SELECT_OFFSET 0 #define RTL8367C_LED_SELECT_MASK 0x3 #define RTL8367C_REG_LED_SYS_CONFIG2 0x1b01 #define RTL8367C_LED_SYS_CONFIG2_DUMMY_OFFSET 2 #define RTL8367C_LED_SYS_CONFIG2_DUMMY_MASK 0xFFFC #define RTL8367C_GATE_LPTD_BYPASS_OFFSET 1 #define RTL8367C_GATE_LPTD_BYPASS_MASK 0x2 #define RTL8367C_LED_SPD_MODE_OFFSET 0 #define RTL8367C_LED_SPD_MODE_MASK 0x1 #define RTL8367C_REG_LED_MODE 0x1b02 #define RTL8367C_DLINK_TIME_OFFSET 15 #define RTL8367C_DLINK_TIME_MASK 0x8000 #define RTL8367C_LED_BUZZ_DUTY_OFFSET 14 #define RTL8367C_LED_BUZZ_DUTY_MASK 0x4000 #define RTL8367C_BUZZER_RATE_OFFSET 12 #define RTL8367C_BUZZER_RATE_MASK 0x3000 #define RTL8367C_LOOP_DETECT_MODE_OFFSET 11 #define RTL8367C_LOOP_DETECT_MODE_MASK 0x800 #define RTL8367C_SEL_PWRON_TIME_OFFSET 9 #define RTL8367C_SEL_PWRON_TIME_MASK 0x600 #define RTL8367C_EN_DLINK_LED_OFFSET 8 #define RTL8367C_EN_DLINK_LED_MASK 0x100 #define RTL8367C_LOOP_DETECT_RATE_OFFSET 6 #define RTL8367C_LOOP_DETECT_RATE_MASK 0xC0 #define RTL8367C_FORCE_RATE_OFFSET 4 #define RTL8367C_FORCE_RATE_MASK 0x30 #define RTL8367C_SEL_LEDRATE_OFFSET 1 #define RTL8367C_SEL_LEDRATE_MASK 0xE #define RTL8367C_SPEED_UP_OFFSET 0 #define RTL8367C_SPEED_UP_MASK 0x1 #define RTL8367C_REG_LED_CONFIGURATION 0x1b03 #define RTL8367C_LED_CONFIGURATION_DUMMY_OFFSET 15 #define RTL8367C_LED_CONFIGURATION_DUMMY_MASK 0x8000 #define RTL8367C_LED_CONFIG_SEL_OFFSET 14 #define RTL8367C_LED_CONFIG_SEL_MASK 0x4000 #define RTL8367C_DATA_LED_OFFSET 12 #define RTL8367C_DATA_LED_MASK 0x3000 #define RTL8367C_LED2_CFG_OFFSET 8 #define RTL8367C_LED2_CFG_MASK 0xF00 #define RTL8367C_LED1_CFG_OFFSET 4 #define RTL8367C_LED1_CFG_MASK 0xF0 #define RTL8367C_LED0_CFG_OFFSET 0 #define RTL8367C_LED0_CFG_MASK 0xF #define RTL8367C_REG_RTCT_RESULTS_CFG 0x1b04 #define RTL8367C_RTCT_2PAIR_FTT_OFFSET 15 #define RTL8367C_RTCT_2PAIR_FTT_MASK 0x8000 #define RTL8367C_RTCT_2PAIR_MODE_OFFSET 14 #define RTL8367C_RTCT_2PAIR_MODE_MASK 0x4000 #define RTL8367C_BLINK_EN_OFFSET 13 #define RTL8367C_BLINK_EN_MASK 0x2000 #define RTL8367C_TIMEOUT_OFFSET 12 #define RTL8367C_TIMEOUT_MASK 0x1000 #define RTL8367C_EN_CD_SAME_SHORT_OFFSET 11 #define RTL8367C_EN_CD_SAME_SHORT_MASK 0x800 #define RTL8367C_EN_CD_SAME_OPEN_OFFSET 10 #define RTL8367C_EN_CD_SAME_OPEN_MASK 0x400 #define RTL8367C_EN_CD_SAME_LINEDRIVER_OFFSET 9 #define RTL8367C_EN_CD_SAME_LINEDRIVER_MASK 0x200 #define RTL8367C_EN_CD_SAME_MISMATCH_OFFSET 8 #define RTL8367C_EN_CD_SAME_MISMATCH_MASK 0x100 #define RTL8367C_EN_CD_SHORT_OFFSET 7 #define RTL8367C_EN_CD_SHORT_MASK 0x80 #define RTL8367C_EN_AB_SHORT_OFFSET 6 #define RTL8367C_EN_AB_SHORT_MASK 0x40 #define RTL8367C_EN_CD_OPEN_OFFSET 5 #define RTL8367C_EN_CD_OPEN_MASK 0x20 #define RTL8367C_EN_AB_OPEN_OFFSET 4 #define RTL8367C_EN_AB_OPEN_MASK 0x10 #define RTL8367C_EN_CD_MISMATCH_OFFSET 3 #define RTL8367C_EN_CD_MISMATCH_MASK 0x8 #define RTL8367C_EN_AB_MISMATCH_OFFSET 2 #define RTL8367C_EN_AB_MISMATCH_MASK 0x4 #define RTL8367C_EN_CD_LINEDRIVER_OFFSET 1 #define RTL8367C_EN_CD_LINEDRIVER_MASK 0x2 #define RTL8367C_EN_AB_LINEDRIVER_OFFSET 0 #define RTL8367C_EN_AB_LINEDRIVER_MASK 0x1 #define RTL8367C_REG_RTCT_LED 0x1b05 #define RTL8367C_DUMMY_1b05a_OFFSET 12 #define RTL8367C_DUMMY_1b05a_MASK 0xF000 #define RTL8367C_RTCT_LED2_OFFSET 8 #define RTL8367C_RTCT_LED2_MASK 0xF00 #define RTL8367C_RTCT_LED1_OFFSET 4 #define RTL8367C_RTCT_LED1_MASK 0xF0 #define RTL8367C_RTCT_LED0_OFFSET 0 #define RTL8367C_RTCT_LED0_MASK 0xF #define RTL8367C_REG_CPU_FORCE_LED_CFG 0x1b07 #define RTL8367C_DUMMY_1b07a_OFFSET 8 #define RTL8367C_DUMMY_1b07a_MASK 0xFF00 #define RTL8367C_LED_FORCE_MODE_OFFSET 2 #define RTL8367C_LED_FORCE_MODE_MASK 0xFC #define RTL8367C_FORCE_MODE_OFFSET 0 #define RTL8367C_FORCE_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED0_CFG0 0x1b08 #define RTL8367C_PORT7_LED0_MODE_OFFSET 14 #define RTL8367C_PORT7_LED0_MODE_MASK 0xC000 #define RTL8367C_PORT6_LED0_MODE_OFFSET 12 #define RTL8367C_PORT6_LED0_MODE_MASK 0x3000 #define RTL8367C_PORT5_LED0_MODE_OFFSET 10 #define RTL8367C_PORT5_LED0_MODE_MASK 0xC00 #define RTL8367C_PORT4_LED0_MODE_OFFSET 8 #define RTL8367C_PORT4_LED0_MODE_MASK 0x300 #define RTL8367C_PORT3_LED0_MODE_OFFSET 6 #define RTL8367C_PORT3_LED0_MODE_MASK 0xC0 #define RTL8367C_PORT2_LED0_MODE_OFFSET 4 #define RTL8367C_PORT2_LED0_MODE_MASK 0x30 #define RTL8367C_PORT1_LED0_MODE_OFFSET 2 #define RTL8367C_PORT1_LED0_MODE_MASK 0xC #define RTL8367C_PORT0_LED0_MODE_OFFSET 0 #define RTL8367C_PORT0_LED0_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED0_CFG1 0x1b09 #define RTL8367C_DUMMY_1b09a_OFFSET 4 #define RTL8367C_DUMMY_1b09a_MASK 0xFFF0 #define RTL8367C_PORT9_LED0_MODE_OFFSET 2 #define RTL8367C_PORT9_LED0_MODE_MASK 0xC #define RTL8367C_PORT8_LED0_MODE_OFFSET 0 #define RTL8367C_PORT8_LED0_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED1_CFG0 0x1b0a #define RTL8367C_PORT7_LED1_MODE_OFFSET 14 #define RTL8367C_PORT7_LED1_MODE_MASK 0xC000 #define RTL8367C_PORT6_LED1_MODE_OFFSET 12 #define RTL8367C_PORT6_LED1_MODE_MASK 0x3000 #define RTL8367C_PORT5_LED1_MODE_OFFSET 10 #define RTL8367C_PORT5_LED1_MODE_MASK 0xC00 #define RTL8367C_PORT4_LED1_MODE_OFFSET 8 #define RTL8367C_PORT4_LED1_MODE_MASK 0x300 #define RTL8367C_PORT3_LED1_MODE_OFFSET 6 #define RTL8367C_PORT3_LED1_MODE_MASK 0xC0 #define RTL8367C_PORT2_LED1_MODE_OFFSET 4 #define RTL8367C_PORT2_LED1_MODE_MASK 0x30 #define RTL8367C_PORT1_LED1_MODE_OFFSET 2 #define RTL8367C_PORT1_LED1_MODE_MASK 0xC #define RTL8367C_PORT0_LED1_MODE_OFFSET 0 #define RTL8367C_PORT0_LED1_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED1_CFG1 0x1b0b #define RTL8367C_DUMMY_1b0ba_OFFSET 4 #define RTL8367C_DUMMY_1b0ba_MASK 0xFFF0 #define RTL8367C_PORT9_LED1_MODE_OFFSET 2 #define RTL8367C_PORT9_LED1_MODE_MASK 0xC #define RTL8367C_PORT8_LED1_MODE_OFFSET 0 #define RTL8367C_PORT8_LED1_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED2_CFG0 0x1b0c #define RTL8367C_PORT7_LED2_MODE_OFFSET 14 #define RTL8367C_PORT7_LED2_MODE_MASK 0xC000 #define RTL8367C_PORT6_LED2_MODE_OFFSET 12 #define RTL8367C_PORT6_LED2_MODE_MASK 0x3000 #define RTL8367C_PORT5_LED2_MODE_OFFSET 10 #define RTL8367C_PORT5_LED2_MODE_MASK 0xC00 #define RTL8367C_PORT4_LED2_MODE_OFFSET 8 #define RTL8367C_PORT4_LED2_MODE_MASK 0x300 #define RTL8367C_PORT3_LED2_MODE_OFFSET 6 #define RTL8367C_PORT3_LED2_MODE_MASK 0xC0 #define RTL8367C_PORT2_LED2_MODE_OFFSET 4 #define RTL8367C_PORT2_LED2_MODE_MASK 0x30 #define RTL8367C_PORT1_LED2_MODE_OFFSET 2 #define RTL8367C_PORT1_LED2_MODE_MASK 0xC #define RTL8367C_PORT0_LED2_MODE_OFFSET 0 #define RTL8367C_PORT0_LED2_MODE_MASK 0x3 #define RTL8367C_REG_CPU_FORCE_LED2_CFG1 0x1b0d #define RTL8367C_DUMMY_1b0da_OFFSET 4 #define RTL8367C_DUMMY_1b0da_MASK 0xFFF0 #define RTL8367C_PORT9_LED2_MODE_OFFSET 2 #define RTL8367C_PORT9_LED2_MODE_MASK 0xC #define RTL8367C_PORT8_LED2_MODE_OFFSET 0 #define RTL8367C_PORT8_LED2_MODE_MASK 0x3 #define RTL8367C_REG_LED_ACTIVE_LOW_CFG0 0x1b0e #define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_OFFSET 15 #define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_MASK 0x8000 #define RTL8367C_PORT3_LED_ACTIVE_LOW_OFFSET 12 #define RTL8367C_PORT3_LED_ACTIVE_LOW_MASK 0x7000 #define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_OFFSET 11 #define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_MASK 0x800 #define RTL8367C_PORT2_LED_ACTIVE_LOW_OFFSET 8 #define RTL8367C_PORT2_LED_ACTIVE_LOW_MASK 0x700 #define RTL8367C_DUMMY_7_OFFSET 7 #define RTL8367C_DUMMY_7_MASK 0x80 #define RTL8367C_PORT1_LED_ACTIVE_LOW_OFFSET 4 #define RTL8367C_PORT1_LED_ACTIVE_LOW_MASK 0x70 #define RTL8367C_DUMMY_3_OFFSET 3 #define RTL8367C_DUMMY_3_MASK 0x8 #define RTL8367C_PORT0_LED_ACTIVE_LOW_OFFSET 0 #define RTL8367C_PORT0_LED_ACTIVE_LOW_MASK 0x7 #define RTL8367C_REG_LED_ACTIVE_LOW_CFG1 0x1b0f #define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_OFFSET 15 #define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_MASK 0x8000 #define RTL8367C_PORT7_LED_ACTIVE_LOW_OFFSET 12 #define RTL8367C_PORT7_LED_ACTIVE_LOW_MASK 0x7000 #define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_OFFSET 11 #define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_MASK 0x800 #define RTL8367C_PORT6_LED_ACTIVE_LOW_OFFSET 8 #define RTL8367C_PORT6_LED_ACTIVE_LOW_MASK 0x700 #define RTL8367C_DUMMY_1b0f_b_OFFSET 7 #define RTL8367C_DUMMY_1b0f_b_MASK 0x80 #define RTL8367C_PORT5_LED_ACTIVE_LOW_OFFSET 4 #define RTL8367C_PORT5_LED_ACTIVE_LOW_MASK 0x70 #define RTL8367C_DUMMY_1b0f_a_OFFSET 3 #define RTL8367C_DUMMY_1b0f_a_MASK 0x8 #define RTL8367C_PORT4_LED_ACTIVE_LOW_OFFSET 0 #define RTL8367C_PORT4_LED_ACTIVE_LOW_MASK 0x7 #define RTL8367C_REG_LED_ACTIVE_LOW_CFG2 0x1b10 #define RTL8367C_DUMMY_1b10_b_OFFSET 7 #define RTL8367C_DUMMY_1b10_b_MASK 0xFF80 #define RTL8367C_PORT9_LED_ACTIVE_LOW_OFFSET 4 #define RTL8367C_PORT9_LED_ACTIVE_LOW_MASK 0x70 #define RTL8367C_DUMMY_1b10_a_OFFSET 3 #define RTL8367C_DUMMY_1b10_a_MASK 0x8 #define RTL8367C_PORT8_LED_ACTIVE_LOW_OFFSET 0 #define RTL8367C_PORT8_LED_ACTIVE_LOW_MASK 0x7 #define RTL8367C_REG_SEL_RTCT_PARA 0x1b21 #define RTL8367C_DO_RTCT_COMMAND_OFFSET 15 #define RTL8367C_DO_RTCT_COMMAND_MASK 0x8000 #define RTL8367C_SEL_RTCT_PARA_DUMMY_OFFSET 12 #define RTL8367C_SEL_RTCT_PARA_DUMMY_MASK 0x7000 #define RTL8367C_SEL_RTCT_RLSTLED_TIME_OFFSET 10 #define RTL8367C_SEL_RTCT_RLSTLED_TIME_MASK 0xC00 #define RTL8367C_SEL_RTCT_TEST_LED_TIME_OFFSET 8 #define RTL8367C_SEL_RTCT_TEST_LED_TIME_MASK 0x300 #define RTL8367C_EN_SCAN_RTCT_OFFSET 7 #define RTL8367C_EN_SCAN_RTCT_MASK 0x80 #define RTL8367C_EN_RTCT_TIMOUT_OFFSET 6 #define RTL8367C_EN_RTCT_TIMOUT_MASK 0x40 #define RTL8367C_EN_ALL_RTCT_OFFSET 5 #define RTL8367C_EN_ALL_RTCT_MASK 0x20 #define RTL8367C_SEL_RTCT_PLE_WID_OFFSET 0 #define RTL8367C_SEL_RTCT_PLE_WID_MASK 0x1F #define RTL8367C_REG_RTCT_ENABLE 0x1b22 #define RTL8367C_RTCT_ENABLE_DUMMY_OFFSET 8 #define RTL8367C_RTCT_ENABLE_DUMMY_MASK 0xFF00 #define RTL8367C_RTCT_ENABLE_PORT_MASK_OFFSET 0 #define RTL8367C_RTCT_ENABLE_PORT_MASK_MASK 0xFF #define RTL8367C_REG_RTCT_TIMEOUT 0x1b23 #define RTL8367C_REG_PARA_LED_IO_EN1 0x1b24 #define RTL8367C_LED1_PARA_P07_00_OFFSET 8 #define RTL8367C_LED1_PARA_P07_00_MASK 0xFF00 #define RTL8367C_LED0_PARA_P07_00_OFFSET 0 #define RTL8367C_LED0_PARA_P07_00_MASK 0xFF #define RTL8367C_REG_PARA_LED_IO_EN2 0x1b25 #define RTL8367C_DUMMY_15_8_OFFSET 8 #define RTL8367C_DUMMY_15_8_MASK 0xFF00 #define RTL8367C_LED2_PARA_P07_00_OFFSET 0 #define RTL8367C_LED2_PARA_P07_00_MASK 0xFF #define RTL8367C_REG_SCAN0_LED_IO_EN1 0x1b26 #define RTL8367C_SCAN0_LED_IO_EN1_DUMMY_OFFSET 3 #define RTL8367C_SCAN0_LED_IO_EN1_DUMMY_MASK 0xFFF8 #define RTL8367C_LED_LOOP_DET_BUZZER_EN_OFFSET 2 #define RTL8367C_LED_LOOP_DET_BUZZER_EN_MASK 0x4 #define RTL8367C_LED_SERI_DATA_EN_OFFSET 1 #define RTL8367C_LED_SERI_DATA_EN_MASK 0x2 #define RTL8367C_LED_SERI_CLK_EN_OFFSET 0 #define RTL8367C_LED_SERI_CLK_EN_MASK 0x1 #define RTL8367C_REG_SCAN1_LED_IO_EN2 0x1b27 #define RTL8367C_LED_SCAN1_BI_PORT_EN_OFFSET 8 #define RTL8367C_LED_SCAN1_BI_PORT_EN_MASK 0xFF00 #define RTL8367C_LED_SCAN1_BI_STA_EN_OFFSET 7 #define RTL8367C_LED_SCAN1_BI_STA_EN_MASK 0x80 #define RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_OFFSET 6 #define RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_MASK 0x40 #define RTL8367C_LED_SCAN1_SI_PORT_EN_OFFSET 2 #define RTL8367C_LED_SCAN1_SI_PORT_EN_MASK 0x3C #define RTL8367C_LED_SCAN1_SI_STA_EN_OFFSET 0 #define RTL8367C_LED_SCAN1_SI_STA_EN_MASK 0x3 #define RTL8367C_REG_LPI_LED_OPT1 0x1b28 #define RTL8367C_LPI_TAG4_OFFSET 12 #define RTL8367C_LPI_TAG4_MASK 0xF000 #define RTL8367C_LPI_TAG3_OFFSET 8 #define RTL8367C_LPI_TAG3_MASK 0xF00 #define RTL8367C_LPI_TAG2_OFFSET 4 #define RTL8367C_LPI_TAG2_MASK 0xF0 #define RTL8367C_LPI_TAG1_OFFSET 0 #define RTL8367C_LPI_TAG1_MASK 0xF #define RTL8367C_REG_LPI_LED_OPT2 0x1b29 #define RTL8367C_LPI_LED_OPT2_DUMMY_OFFSET 15 #define RTL8367C_LPI_LED_OPT2_DUMMY_MASK 0x8000 #define RTL8367C_LPI_LED2_WEAK_OFFSET 14 #define RTL8367C_LPI_LED2_WEAK_MASK 0x4000 #define RTL8367C_LPI_LED1_WEAK_OFFSET 13 #define RTL8367C_LPI_LED1_WEAK_MASK 0x2000 #define RTL8367C_LPI_LED0_WEAK_OFFSET 12 #define RTL8367C_LPI_LED0_WEAK_MASK 0x1000 #define RTL8367C_LPI_LED2_OFFSET 11 #define RTL8367C_LPI_LED2_MASK 0x800 #define RTL8367C_LPI_LED1_OFFSET 10 #define RTL8367C_LPI_LED1_MASK 0x400 #define RTL8367C_LPI_LED0_OFFSET 9 #define RTL8367C_LPI_LED0_MASK 0x200 #define RTL8367C_LPI_TAG8_OFFSET 8 #define RTL8367C_LPI_TAG8_MASK 0x100 #define RTL8367C_LPI_TAG7_OFFSET 6 #define RTL8367C_LPI_TAG7_MASK 0xC0 #define RTL8367C_LPI_TAG6_OFFSET 4 #define RTL8367C_LPI_TAG6_MASK 0x30 #define RTL8367C_LPI_TAG5_OFFSET 0 #define RTL8367C_LPI_TAG5_MASK 0xF #define RTL8367C_REG_LPI_LED_OPT3 0x1b2a #define RTL8367C_LPI_LED_OPT3_DUMMY_OFFSET 3 #define RTL8367C_LPI_LED_OPT3_DUMMY_MASK 0xFFF8 #define RTL8367C_RESTORE_LED_RATE_SEL_OFFSET 1 #define RTL8367C_RESTORE_LED_RATE_SEL_MASK 0x6 #define RTL8367C_RESTORE_LED_SEL_OFFSET 0 #define RTL8367C_RESTORE_LED_SEL_MASK 0x1 #define RTL8367C_REG_P0_LED_MUX 0x1b2b #define RTL8367C_CFG_P0_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P0_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P0_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P0_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P0_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P0_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P1_LED_MUX 0x1b2c #define RTL8367C_CFG_P1_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P1_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P1_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P1_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P1_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P1_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P2_LED_MUX 0x1b2d #define RTL8367C_CFG_P2_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P2_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P2_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P2_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P2_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P2_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P3_LED_MUX 0x1b2e #define RTL8367C_CFG_P3_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P3_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P3_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P3_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P3_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P3_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P4_LED_MUX 0x1b2f #define RTL8367C_CFG_P4_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P4_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P4_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P4_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P4_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P4_LED0_MUX_MASK 0x1F #define RTL8367C_REG_LED0_DATA_CTRL 0x1b30 #define RTL8367C_CFG_DATA_LED0_SEL_OFFSET 6 #define RTL8367C_CFG_DATA_LED0_SEL_MASK 0x40 #define RTL8367C_CFG_DATA_LED0_ACT_OFFSET 4 #define RTL8367C_CFG_DATA_LED0_ACT_MASK 0x30 #define RTL8367C_CFG_DATA_LED0_SPD_OFFSET 0 #define RTL8367C_CFG_DATA_LED0_SPD_MASK 0xF #define RTL8367C_REG_LED1_DATA_CTRL 0x1b31 #define RTL8367C_CFG_DATA_LED1_SEL_OFFSET 6 #define RTL8367C_CFG_DATA_LED1_SEL_MASK 0x40 #define RTL8367C_CFG_DATA_LED1_ACT_OFFSET 4 #define RTL8367C_CFG_DATA_LED1_ACT_MASK 0x30 #define RTL8367C_CFG_DATA_LED1_SPD_OFFSET 0 #define RTL8367C_CFG_DATA_LED1_SPD_MASK 0xF #define RTL8367C_REG_LED2_DATA_CTRL 0x1b32 #define RTL8367C_CFG_DATA_LED2_SEL_OFFSET 6 #define RTL8367C_CFG_DATA_LED2_SEL_MASK 0x40 #define RTL8367C_CFG_DATA_LED2_ACT_OFFSET 4 #define RTL8367C_CFG_DATA_LED2_ACT_MASK 0x30 #define RTL8367C_CFG_DATA_LED2_SPD_OFFSET 0 #define RTL8367C_CFG_DATA_LED2_SPD_MASK 0xF #define RTL8367C_REG_PARA_LED_IO_EN3 0x1b33 #define RTL8367C_dummy_1b33a_OFFSET 6 #define RTL8367C_dummy_1b33a_MASK 0xFFC0 #define RTL8367C_LED2_PARA_P09_08_OFFSET 4 #define RTL8367C_LED2_PARA_P09_08_MASK 0x30 #define RTL8367C_LED1_PARA_P09_08_OFFSET 2 #define RTL8367C_LED1_PARA_P09_08_MASK 0xC #define RTL8367C_LED0_PARA_P09_08_OFFSET 0 #define RTL8367C_LED0_PARA_P09_08_MASK 0x3 #define RTL8367C_REG_SCAN1_LED_IO_EN3 0x1b34 #define RTL8367C_dummy_1b34a_OFFSET 3 #define RTL8367C_dummy_1b34a_MASK 0xFFF8 #define RTL8367C_LED_SCAN1_BI_PORT9_8_EN_OFFSET 1 #define RTL8367C_LED_SCAN1_BI_PORT9_8_EN_MASK 0x6 #define RTL8367C_LED_SCAN1_SI_PORT9_8_EN_OFFSET 0 #define RTL8367C_LED_SCAN1_SI_PORT9_8_EN_MASK 0x1 #define RTL8367C_REG_P5_LED_MUX 0x1b35 #define RTL8367C_CFG_P5_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P5_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P5_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P5_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P5_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P5_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P6_LED_MUX 0x1b36 #define RTL8367C_CFG_P6_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P6_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P6_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P6_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P6_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P6_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P7_LED_MUX 0x1b37 #define RTL8367C_CFG_P7_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P7_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P7_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P7_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P7_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P7_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P8_LED_MUX 0x1b38 #define RTL8367C_CFG_P8_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P8_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P8_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P8_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P8_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P8_LED0_MUX_MASK 0x1F #define RTL8367C_REG_P9_LED_MUX 0x1b39 #define RTL8367C_CFG_P9_LED2_MUX_OFFSET 10 #define RTL8367C_CFG_P9_LED2_MUX_MASK 0x7C00 #define RTL8367C_CFG_P9_LED1_MUX_OFFSET 5 #define RTL8367C_CFG_P9_LED1_MUX_MASK 0x3E0 #define RTL8367C_CFG_P9_LED0_MUX_OFFSET 0 #define RTL8367C_CFG_P9_LED0_MUX_MASK 0x1F #define RTL8367C_REG_SERIAL_LED_CTRL 0x1b3a #define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_OFFSET 13 #define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_MASK 0x6000 #define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_OFFSET 12 #define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_MASK 0x1000 #define RTL8367C_SERIAL_LED_GROUP_NUM_OFFSET 10 #define RTL8367C_SERIAL_LED_GROUP_NUM_MASK 0xC00 #define RTL8367C_SERIAL_LED_PORT_EN_OFFSET 0 #define RTL8367C_SERIAL_LED_PORT_EN_MASK 0x3FF /* (16'h1c00)IGMP_EAV */ #define RTL8367C_REG_IGMP_MLD_CFG0 0x1c00 #define RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET 15 #define RTL8367C_IGMP_MLD_PORTISO_LEAKY_MASK 0x8000 #define RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET 14 #define RTL8367C_IGMP_MLD_VLAN_LEAKY_MASK 0x4000 #define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET 13 #define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000 #define RTL8367C_REPORT_FORWARD_OFFSET 12 #define RTL8367C_REPORT_FORWARD_MASK 0x1000 #define RTL8367C_ROBURSTNESS_VAR_OFFSET 9 #define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00 #define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8 #define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100 #define RTL8367C_REPORT_SUPPRESSION_OFFSET 7 #define RTL8367C_REPORT_SUPPRESSION_MASK 0x80 #define RTL8367C_LEAVE_TIMER_OFFSET 4 #define RTL8367C_LEAVE_TIMER_MASK 0x70 #define RTL8367C_FAST_LEAVE_EN_OFFSET 3 #define RTL8367C_FAST_LEAVE_EN_MASK 0x8 #define RTL8367C_CKS_ERR_OP_OFFSET 1 #define RTL8367C_CKS_ERR_OP_MASK 0x6 #define RTL8367C_IGMP_MLD_EN_OFFSET 0 #define RTL8367C_IGMP_MLD_EN_MASK 0x1 #define RTL8367C_REG_IGMP_MLD_CFG1 0x1c01 #define RTL8367C_DROP_LEAVE_ZERO_OFFSET 2 #define RTL8367C_DROP_LEAVE_ZERO_MASK 0x4 #define RTL8367C_TABLE_FULL_OP_OFFSET 0 #define RTL8367C_TABLE_FULL_OP_MASK 0x3 #define RTL8367C_REG_IGMP_MLD_CFG2 0x1c02 #define RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT 0x1c03 #define RTL8367C_D_ROUTER_PORT_2_OFFSET 11 #define RTL8367C_D_ROUTER_PORT_2_MASK 0x7800 #define RTL8367C_D_ROUTER_PORT_TMR_2_OFFSET 8 #define RTL8367C_D_ROUTER_PORT_TMR_2_MASK 0x700 #define RTL8367C_D_ROUTER_PORT_1_OFFSET 3 #define RTL8367C_D_ROUTER_PORT_1_MASK 0x78 #define RTL8367C_D_ROUTER_PORT_TMR_1_OFFSET 0 #define RTL8367C_D_ROUTER_PORT_TMR_1_MASK 0x7 #define RTL8367C_REG_IGMP_STATIC_ROUTER_PORT 0x1c04 #define RTL8367C_IGMP_STATIC_ROUTER_PORT_OFFSET 0 #define RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK 0x7FF #define RTL8367C_REG_IGMP_PORT0_CONTROL 0x1c05 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT1_CONTROL 0x1c06 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT2_CONTROL 0x1c07 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT3_CONTROL 0x1c08 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT4_CONTROL 0x1c09 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT5_CONTROL 0x1c0a #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT6_CONTROL 0x1c0b #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT7_CONTROL 0x1c0c #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT01_MAX_GROUP 0x1c0d #define RTL8367C_PORT1_MAX_GROUP_OFFSET 8 #define RTL8367C_PORT1_MAX_GROUP_MASK 0xFF00 #define RTL8367C_PORT0_MAX_GROUP_OFFSET 0 #define RTL8367C_PORT0_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT23_MAX_GROUP 0x1c0e #define RTL8367C_PORT3_MAX_GROUP_OFFSET 8 #define RTL8367C_PORT3_MAX_GROUP_MASK 0xFF00 #define RTL8367C_PORT2_MAX_GROUP_OFFSET 0 #define RTL8367C_PORT2_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT45_MAX_GROUP 0x1c0f #define RTL8367C_PORT5_MAX_GROUP_OFFSET 8 #define RTL8367C_PORT5_MAX_GROUP_MASK 0xFF00 #define RTL8367C_PORT4_MAX_GROUP_OFFSET 0 #define RTL8367C_PORT4_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT67_MAX_GROUP 0x1c10 #define RTL8367C_PORT7_MAX_GROUP_OFFSET 8 #define RTL8367C_PORT7_MAX_GROUP_MASK 0xFF00 #define RTL8367C_PORT6_MAX_GROUP_OFFSET 0 #define RTL8367C_PORT6_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT01_CURRENT_GROUP 0x1c11 #define RTL8367C_PORT1_CURRENT_GROUP_OFFSET 8 #define RTL8367C_PORT1_CURRENT_GROUP_MASK 0xFF00 #define RTL8367C_PORT0_CURRENT_GROUP_OFFSET 0 #define RTL8367C_PORT0_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT23_CURRENT_GROUP 0x1c12 #define RTL8367C_PORT3_CURRENT_GROUP_OFFSET 8 #define RTL8367C_PORT3_CURRENT_GROUP_MASK 0xFF00 #define RTL8367C_PORT2_CURRENT_GROUP_OFFSET 0 #define RTL8367C_PORT2_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT45_CURRENT_GROUP 0x1c13 #define RTL8367C_PORT5_CURRENT_GROUP_OFFSET 8 #define RTL8367C_PORT5_CURRENT_GROUP_MASK 0xFF00 #define RTL8367C_PORT4_CURRENT_GROUP_OFFSET 0 #define RTL8367C_PORT4_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT67_CURRENT_GROUP 0x1c14 #define RTL8367C_PORT7_CURRENT_GROUP_OFFSET 8 #define RTL8367C_PORT7_CURRENT_GROUP_MASK 0xFF00 #define RTL8367C_PORT6_CURRENT_GROUP_OFFSET 0 #define RTL8367C_PORT6_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_MLD_CFG3 0x1c15 #define RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET 5 #define RTL8367C_IGMP_MLD_IP6_BYPASS_MASK 0x20 #define RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET 4 #define RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_MASK 0x10 #define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET 3 #define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_MASK 0x8 #define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET 2 #define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_MASK 0x4 #define RTL8367C_REPORT_LEAVE_FORWARD_OFFSET 0 #define RTL8367C_REPORT_LEAVE_FORWARD_MASK 0x3 #define RTL8367C_REG_IGMP_MLD_CFG4 0x1c16 #define RTL8367C_IGMP_MLD_CFG4_OFFSET 0 #define RTL8367C_IGMP_MLD_CFG4_MASK 0x7FF #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST0 0x1c20 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST1 0x1c21 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST2 0x1c22 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST3 0x1c23 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST4 0x1c24 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST5 0x1c25 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST6 0x1c26 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST7 0x1c27 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST8 0x1c28 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST9 0x1c29 #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST10 0x1c2a #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST11 0x1c2b #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST12 0x1c2c #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST13 0x1c2d #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST14 0x1c2e #define RTL8367C_REG_IGMP_GROUP_USAGE_LIST15 0x1c2f #define RTL8367C_REG_EAV_CTRL0 0x1c30 #define RTL8367C_EAV_CTRL0_OFFSET 0 #define RTL8367C_EAV_CTRL0_MASK 0xFF #define RTL8367C_REG_EAV_CTRL1 0x1c31 #define RTL8367C_REMAP_EAV_PRI3_REGEN_OFFSET 9 #define RTL8367C_REMAP_EAV_PRI3_REGEN_MASK 0xE00 #define RTL8367C_REMAP_EAV_PRI2_REGEN_OFFSET 6 #define RTL8367C_REMAP_EAV_PRI2_REGEN_MASK 0x1C0 #define RTL8367C_REMAP_EAV_PRI1_REGEN_OFFSET 3 #define RTL8367C_REMAP_EAV_PRI1_REGEN_MASK 0x38 #define RTL8367C_REMAP_EAV_PRI0_REGEN_OFFSET 0 #define RTL8367C_REMAP_EAV_PRI0_REGEN_MASK 0x7 #define RTL8367C_REG_EAV_CTRL2 0x1c32 #define RTL8367C_REMAP_EAV_PRI7_REGEN_OFFSET 9 #define RTL8367C_REMAP_EAV_PRI7_REGEN_MASK 0xE00 #define RTL8367C_REMAP_EAV_PRI6_REGEN_OFFSET 6 #define RTL8367C_REMAP_EAV_PRI6_REGEN_MASK 0x1C0 #define RTL8367C_REMAP_EAV_PRI5_REGEN_OFFSET 3 #define RTL8367C_REMAP_EAV_PRI5_REGEN_MASK 0x38 #define RTL8367C_REMAP_EAV_PRI4_REGEN_OFFSET 0 #define RTL8367C_REMAP_EAV_PRI4_REGEN_MASK 0x7 #define RTL8367C_REG_SYS_TIME_FREQ 0x1c43 #define RTL8367C_REG_SYS_TIME_OFFSET_L 0x1c44 #define RTL8367C_REG_SYS_TIME_OFFSET_H 0x1c45 #define RTL8367C_REG_SYS_TIME_OFFSET_512NS_L 0x1c46 #define RTL8367C_REG_SYS_TIME_OFFSET_512NS_H 0x1c47 #define RTL8367C_SYS_TIME_OFFSET_TUNE_OFFSET 5 #define RTL8367C_SYS_TIME_OFFSET_TUNE_MASK 0x20 #define RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_OFFSET 0 #define RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_MASK 0x1F #define RTL8367C_REG_SYS_TIME_SEC_TRANSIT 0x1c48 #define RTL8367C_SYS_TIME_SEC_TRANSIT_OFFSET 0 #define RTL8367C_SYS_TIME_SEC_TRANSIT_MASK 0x1 #define RTL8367C_REG_SYS_TIME_SEC_HIGH_L 0x1c49 #define RTL8367C_REG_SYS_TIME_SEC_HIGH_H 0x1c4a #define RTL8367C_REG_SYS_TIME_512NS_L 0x1c4b #define RTL8367C_REG_SYS_TIME_512NS_H 0x1c4c #define RTL8367C_SYS_TIME_512NS_H_OFFSET 0 #define RTL8367C_SYS_TIME_512NS_H_MASK 0x1F #define RTL8367C_REG_FALLBACK_CTRL 0x1c70 #define RTL8367C_FALLBACK_PL_DEC_EN_OFFSET 15 #define RTL8367C_FALLBACK_PL_DEC_EN_MASK 0x8000 #define RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_OFFSET 14 #define RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_MASK 0x4000 #define RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_OFFSET 11 #define RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_MASK 0x3800 #define RTL8367C_FALLBACK_MONITORMAX_OFFSET 8 #define RTL8367C_FALLBACK_MONITORMAX_MASK 0x700 #define RTL8367C_FALLBACK_MONITOR_TIMEOUT_OFFSET 0 #define RTL8367C_FALLBACK_MONITOR_TIMEOUT_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT0_CFG0 0x1c71 #define RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT0_CFG1 0x1c72 #define RTL8367C_REG_FALLBACK_PORT0_CFG2 0x1c73 #define RTL8367C_FALLBACK_PORT0_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT0_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT0_CFG3 0x1c74 #define RTL8367C_FALLBACK_PORT0_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT0_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT1_CFG0 0x1c75 #define RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT1_CFG1 0x1c76 #define RTL8367C_REG_FALLBACK_PORT1_CFG2 0x1c77 #define RTL8367C_FALLBACK_PORT1_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT1_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT1_CFG3 0x1c78 #define RTL8367C_FALLBACK_PORT1_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT1_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT2_CFG0 0x1c79 #define RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT2_CFG1 0x1c7a #define RTL8367C_REG_FALLBACK_PORT2_CFG2 0x1c7b #define RTL8367C_FALLBACK_PORT2_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT2_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT2_CFG3 0x1c7c #define RTL8367C_FALLBACK_PORT2_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT2_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT3_CFG0 0x1c7d #define RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT3_CFG1 0x1c7e #define RTL8367C_REG_FALLBACK_PORT3_CFG2 0x1c7f #define RTL8367C_FALLBACK_PORT3_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT3_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT3_CFG3 0x1c80 #define RTL8367C_FALLBACK_PORT3_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT3_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT4_CFG0 0x1c81 #define RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT4_CFG1 0x1c82 #define RTL8367C_REG_FALLBACK_PORT4_CFG2 0x1c83 #define RTL8367C_FALLBACK_PORT4_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT4_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT4_CFG3 0x1c84 #define RTL8367C_FALLBACK_PORT4_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT4_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_CTRL1 0x1c85 #define RTL8367C_FALLBACK_VALIDFLOW_OFFSET 8 #define RTL8367C_FALLBACK_VALIDFLOW_MASK 0xFF00 #define RTL8367C_FALLBACK_STOP_TMR_OFFSET 0 #define RTL8367C_FALLBACK_STOP_TMR_MASK 0x1 #define RTL8367C_REG_FALLBACK_CPL 0x1c86 #define RTL8367C_PORT4_CPL_OFFSET 4 #define RTL8367C_PORT4_CPL_MASK 0x10 #define RTL8367C_PORT3_CPL_OFFSET 3 #define RTL8367C_PORT3_CPL_MASK 0x8 #define RTL8367C_PORT2_CPL_OFFSET 2 #define RTL8367C_PORT2_CPL_MASK 0x4 #define RTL8367C_PORT1_CPL_OFFSET 1 #define RTL8367C_PORT1_CPL_MASK 0x2 #define RTL8367C_PORT0_CPL_OFFSET 0 #define RTL8367C_PORT0_CPL_MASK 0x1 #define RTL8367C_REG_FALLBACK_PHY_PAGE 0x1c87 #define RTL8367C_FALLBACK_PHY_PAGE_OFFSET 0 #define RTL8367C_FALLBACK_PHY_PAGE_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PHY_REG 0x1c88 #define RTL8367C_FALLBACK_PHY_REG_OFFSET 0 #define RTL8367C_FALLBACK_PHY_REG_MASK 0x1F #define RTL8367C_REG_AFBK_INFO_X0 0x1c89 #define RTL8367C_REG_AFBK_INFO_X1 0x1c8a #define RTL8367C_REG_AFBK_INFO_X2 0x1c8b #define RTL8367C_REG_AFBK_INFO_X3 0x1c8c #define RTL8367C_REG_AFBK_INFO_X4 0x1c8d #define RTL8367C_REG_AFBK_INFO_X5 0x1c8e #define RTL8367C_REG_AFBK_INFO_X6 0x1c8f #define RTL8367C_REG_AFBK_INFO_X7 0x1c90 #define RTL8367C_REG_AFBK_INFO_X8 0x1c91 #define RTL8367C_REG_AFBK_INFO_X9 0x1c92 #define RTL8367C_REG_AFBK_INFO_X10 0x1c93 #define RTL8367C_REG_AFBK_INFO_X11 0x1c94 #define RTL8367C_REG_FALLBACK_PORT5_CFG0 0x1ca0 #define RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT5_CFG1 0x1ca1 #define RTL8367C_REG_FALLBACK_PORT5_CFG2 0x1ca2 #define RTL8367C_FALLBACK_PORT5_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT5_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT5_CFG3 0x1ca3 #define RTL8367C_FALLBACK_PORT5_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT5_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT6_CFG0 0x1ca4 #define RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT6_CFG1 0x1ca5 #define RTL8367C_REG_FALLBACK_PORT6_CFG2 0x1ca6 #define RTL8367C_FALLBACK_PORT6_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT6_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT6_CFG3 0x1ca7 #define RTL8367C_FALLBACK_PORT6_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT6_CFG3_MASK 0xFF #define RTL8367C_REG_FALLBACK_PORT7_CFG0 0x1ca8 #define RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_OFFSET 15 #define RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_MASK 0x8000 #define RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_OFFSET 14 #define RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_MASK 0x4000 #define RTL8367C_REG_FALLBACK_PORT7_CFG1 0x1ca9 #define RTL8367C_REG_FALLBACK_PORT7_CFG2 0x1caa #define RTL8367C_FALLBACK_PORT7_CFG2_OFFSET 0 #define RTL8367C_FALLBACK_PORT7_CFG2_MASK 0xFFF #define RTL8367C_REG_FALLBACK_PORT7_CFG3 0x1cab #define RTL8367C_FALLBACK_PORT7_CFG3_OFFSET 0 #define RTL8367C_FALLBACK_PORT7_CFG3_MASK 0xFF #define RTL8367C_REG_IGMP_PORT8_CONTROL 0x1cb0 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT9_CONTROL 0x1cb1 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT10_CONTROL 0x1cb2 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_OFFSET 14 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_MASK 0x4000 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_OFFSET 13 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_MASK 0x2000 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_OFFSET 12 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_MASK 0x1000 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_OFFSET 11 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_MASK 0x800 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_OFFSET 10 #define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_MASK 0x400 #define RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_OFFSET 8 #define RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_MASK 0x300 #define RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_OFFSET 6 #define RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_MASK 0xC0 #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_OFFSET 4 #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_MASK 0x30 #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_OFFSET 2 #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_MASK 0xC #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_OFFSET 0 #define RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_MASK 0x3 #define RTL8367C_REG_IGMP_PORT89_MAX_GROUP 0x1cb3 #define RTL8367C_PORT9_MAX_GROUP_OFFSET 8 #define RTL8367C_PORT9_MAX_GROUP_MASK 0xFF00 #define RTL8367C_PORT8_MAX_GROUP_OFFSET 0 #define RTL8367C_PORT8_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT10_MAX_GROUP 0x1cb4 #define RTL8367C_IGMP_PORT10_MAX_GROUP_OFFSET 0 #define RTL8367C_IGMP_PORT10_MAX_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT89_CURRENT_GROUP 0x1cb5 #define RTL8367C_PORT9_CURRENT_GROUP_OFFSET 8 #define RTL8367C_PORT9_CURRENT_GROUP_MASK 0xFF00 #define RTL8367C_PORT8_CURRENT_GROUP_OFFSET 0 #define RTL8367C_PORT8_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_PORT10_CURRENT_GROUP 0x1cb6 #define RTL8367C_IGMP_PORT10_CURRENT_GROUP_OFFSET 0 #define RTL8367C_IGMP_PORT10_CURRENT_GROUP_MASK 0xFF #define RTL8367C_REG_IGMP_L3_CHECKSUM_CHECK 0x1cb7 #define RTL8367C_IGMP_L3_CHECKSUM_CHECK_OFFSET 0 #define RTL8367C_IGMP_L3_CHECKSUM_CHECK_MASK 0x1 /* (16'h1d00)chip_70b_reg */ #define RTL8367C_REG_PCSXF_CFG 0x1d00 #define RTL8367C_PCSXF_CFG_Reserved_OFFSET 15 #define RTL8367C_PCSXF_CFG_Reserved_MASK 0x8000 #define RTL8367C_CFG_RST_RXFIFO_P7_5_OFFSET 12 #define RTL8367C_CFG_RST_RXFIFO_P7_5_MASK 0x7000 #define RTL8367C_CFG_PCSXF_OFFSET 8 #define RTL8367C_CFG_PCSXF_MASK 0xF00 #define RTL8367C_CFG_RST_RXFIFO_OFFSET 3 #define RTL8367C_CFG_RST_RXFIFO_MASK 0xF8 #define RTL8367C_CFG_COL2RXDV_OFFSET 2 #define RTL8367C_CFG_COL2RXDV_MASK 0x4 #define RTL8367C_CFG_PHY_SDET_OFFSET 0 #define RTL8367C_CFG_PHY_SDET_MASK 0x3 #define RTL8367C_REG_PHYID_CFG0 0x1d01 #define RTL8367C_CFG_PHY_BRD_MODE_P7_5_OFFSET 11 #define RTL8367C_CFG_PHY_BRD_MODE_P7_5_MASK 0x3800 #define RTL8367C_CFG_PHYAD_14C_OFFSET 10 #define RTL8367C_CFG_PHYAD_14C_MASK 0x400 #define RTL8367C_CFG_PHY_BRD_MODE_OFFSET 5 #define RTL8367C_CFG_PHY_BRD_MODE_MASK 0x3E0 #define RTL8367C_CFG_BRD_PHYAD_OFFSET 0 #define RTL8367C_CFG_BRD_PHYAD_MASK 0x1F #define RTL8367C_REG_PHYID_CFG1 0x1d02 #define RTL8367C_CFG_MSK_MDI_OFFSET 5 #define RTL8367C_CFG_MSK_MDI_MASK 0x1FE0 #define RTL8367C_CFG_BASE_PHYAD_OFFSET 0 #define RTL8367C_CFG_BASE_PHYAD_MASK 0x1F #define RTL8367C_REG_PHY_POLL_CFG0 0x1d03 #define RTL8367C_CFG_HOTCMD_PRD_EN_OFFSET 15 #define RTL8367C_CFG_HOTCMD_PRD_EN_MASK 0x8000 #define RTL8367C_CFG_HOTCMD_EN_OFFSET 12 #define RTL8367C_CFG_HOTCMD_EN_MASK 0x7000 #define RTL8367C_CFG_POLL_PERIOD_OFFSET 8 #define RTL8367C_CFG_POLL_PERIOD_MASK 0xF00 #define RTL8367C_CFG_PERI_CMDS_RD_OFFSET 4 #define RTL8367C_CFG_PERI_CMDS_RD_MASK 0xF0 #define RTL8367C_CFG_PERI_CMDS_WR_OFFSET 0 #define RTL8367C_CFG_PERI_CMDS_WR_MASK 0xF #define RTL8367C_REG_PHY_POLL_CFG1 0x1d04 #define RTL8367C_REG_PHY_POLL_CFG2 0x1d05 #define RTL8367C_REG_PHY_POLL_CFG3 0x1d06 #define RTL8367C_REG_PHY_POLL_CFG4 0x1d07 #define RTL8367C_REG_PHY_POLL_CFG5 0x1d08 #define RTL8367C_REG_PHY_POLL_CFG6 0x1d09 #define RTL8367C_REG_PHY_POLL_CFG7 0x1d0a #define RTL8367C_REG_PHY_POLL_CFG8 0x1d0b #define RTL8367C_REG_PHY_POLL_CFG9 0x1d0c #define RTL8367C_REG_PHY_POLL_CFG10 0x1d0d #define RTL8367C_REG_PHY_POLL_CFG11 0x1d0e #define RTL8367C_REG_PHY_POLL_CFG12 0x1d0f #define RTL8367C_REG_EFUSE_MISC 0x1d10 #define RTL8367C_CFG_SA_SEL_OFFSET 5 #define RTL8367C_CFG_SA_SEL_MASK 0x20 #define RTL8367C_CFG_PHYAD00_OFFSET 0 #define RTL8367C_CFG_PHYAD00_MASK 0x1F #define RTL8367C_REG_SDS_MISC 0x1d11 #define RTL8367C_CFG_SGMII_RXFC_OFFSET 14 #define RTL8367C_CFG_SGMII_RXFC_MASK 0x4000 #define RTL8367C_CFG_SGMII_TXFC_OFFSET 13 #define RTL8367C_CFG_SGMII_TXFC_MASK 0x2000 #define RTL8367C_INB_ARB_OFFSET 12 #define RTL8367C_INB_ARB_MASK 0x1000 #define RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET 11 #define RTL8367C_CFG_MAC8_SEL_HSGMII_MASK 0x800 #define RTL8367C_CFG_SGMII_FDUP_OFFSET 10 #define RTL8367C_CFG_SGMII_FDUP_MASK 0x400 #define RTL8367C_CFG_SGMII_LINK_OFFSET 9 #define RTL8367C_CFG_SGMII_LINK_MASK 0x200 #define RTL8367C_CFG_SGMII_SPD_OFFSET 7 #define RTL8367C_CFG_SGMII_SPD_MASK 0x180 #define RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET 6 #define RTL8367C_CFG_MAC8_SEL_SGMII_MASK 0x40 #define RTL8367C_CFG_INB_SEL_OFFSET 3 #define RTL8367C_CFG_INB_SEL_MASK 0x38 #define RTL8367C_CFG_SDS_MODE_18C_OFFSET 0 #define RTL8367C_CFG_SDS_MODE_18C_MASK 0x7 #define RTL8367C_REG_FIFO_CTRL 0x1d12 #define RTL8367C_CFG_LINK_DOWN_CLR_FIFO_OFFSET 11 #define RTL8367C_CFG_LINK_DOWN_CLR_FIFO_MASK 0x800 #define RTL8367C_CFG_LPBK_OFFSET 10 #define RTL8367C_CFG_LPBK_MASK 0x400 #define RTL8367C_CFG_NOT_FF_OUT_OFFSET 9 #define RTL8367C_CFG_NOT_FF_OUT_MASK 0x200 #define RTL8367C_CFG_WATER_LEVEL_FD_OFFSET 6 #define RTL8367C_CFG_WATER_LEVEL_FD_MASK 0x1C0 #define RTL8367C_CFG_WATER_LEVEL_Y2X_OFFSET 3 #define RTL8367C_CFG_WATER_LEVEL_Y2X_MASK 0x38 #define RTL8367C_CFG_WATER_LEVEL_X2Y_OFFSET 0 #define RTL8367C_CFG_WATER_LEVEL_X2Y_MASK 0x7 #define RTL8367C_REG_BCAM_SETTING 0x1d13 #define RTL8367C_CFG_BCAM_MDS_OFFSET 3 #define RTL8367C_CFG_BCAM_MDS_MASK 0x18 #define RTL8367C_CFG_BCAM_RDS_OFFSET 0 #define RTL8367C_CFG_BCAM_RDS_MASK 0x7 #define RTL8367C_REG_GPHY_ACS_MISC 0x1d14 #define RTL8367C_CFG_SEL_GPHY_SMI_OFFSET 3 #define RTL8367C_CFG_SEL_GPHY_SMI_MASK 0x8 #define RTL8367C_CFG_BRD_PHYIDX_OFFSET 0 #define RTL8367C_CFG_BRD_PHYIDX_MASK 0x7 #define RTL8367C_REG_GPHY_OCP_MSB_0 0x1d15 #define RTL8367C_CFG_CPU_OCPADR_MSB_OFFSET 6 #define RTL8367C_CFG_CPU_OCPADR_MSB_MASK 0xFC0 #define RTL8367C_CFG_DW8051_OCPADR_MSB_OFFSET 0 #define RTL8367C_CFG_DW8051_OCPADR_MSB_MASK 0x3F #define RTL8367C_REG_GPHY_OCP_MSB_1 0x1d16 #define RTL8367C_CFG_PATCH_OCPADR_MSB_OFFSET 6 #define RTL8367C_CFG_PATCH_OCPADR_MSB_MASK 0xFC0 #define RTL8367C_CFG_PHYSTS_OCPADR_MSB_OFFSET 0 #define RTL8367C_CFG_PHYSTS_OCPADR_MSB_MASK 0x3F #define RTL8367C_REG_GPHY_OCP_MSB_2 0x1d17 #define RTL8367C_CFG_RRCP_OCPADR_MSB_OFFSET 6 #define RTL8367C_CFG_RRCP_OCPADR_MSB_MASK 0xFC0 #define RTL8367C_CFG_RTCT_OCPADR_MSB_OFFSET 0 #define RTL8367C_CFG_RTCT_OCPADR_MSB_MASK 0x3F #define RTL8367C_REG_GPHY_OCP_MSB_3 0x1d18 #define RTL8367C_GPHY_OCP_MSB_3_OFFSET 0 #define RTL8367C_GPHY_OCP_MSB_3_MASK 0x3F #define RTL8367C_REG_GPIO_67C_I_X0 0x1d19 #define RTL8367C_REG_GPIO_67C_I_X1 0x1d1a #define RTL8367C_REG_GPIO_67C_I_X2 0x1d1b #define RTL8367C_REG_GPIO_67C_I_X3 0x1d1c #define RTL8367C_GPIO_67C_I_X3_OFFSET 0 #define RTL8367C_GPIO_67C_I_X3_MASK 0x3FFF #define RTL8367C_REG_GPIO_67C_O_X0 0x1d1d #define RTL8367C_REG_GPIO_67C_O_X1 0x1d1e #define RTL8367C_REG_GPIO_67C_O_X2 0x1d1f #define RTL8367C_REG_GPIO_67C_O_X3 0x1d20 #define RTL8367C_GPIO_67C_O_X3_OFFSET 0 #define RTL8367C_GPIO_67C_O_X3_MASK 0x3FFF #define RTL8367C_REG_GPIO_67C_OE_X0 0x1d21 #define RTL8367C_REG_GPIO_67C_OE_X1 0x1d22 #define RTL8367C_REG_GPIO_67C_OE_X2 0x1d23 #define RTL8367C_REG_GPIO_67C_OE_X3 0x1d24 #define RTL8367C_GPIO_67C_OE_X3_OFFSET 0 #define RTL8367C_GPIO_67C_OE_X3_MASK 0x3FFF #define RTL8367C_REG_GPIO_MODE_67C_X0 0x1d25 #define RTL8367C_REG_GPIO_MODE_67C_X1 0x1d26 #define RTL8367C_REG_GPIO_MODE_67C_X2 0x1d27 #define RTL8367C_REG_GPIO_MODE_67C_X3 0x1d28 #define RTL8367C_GPIO_MODE_67C_X3_OFFSET 0 #define RTL8367C_GPIO_MODE_67C_X3_MASK 0x3FFF #define RTL8367C_REG_WGPHY_MISC_0 0x1d29 #define RTL8367C_CFG_INIPHY_DISGIGA_P7_5_OFFSET 13 #define RTL8367C_CFG_INIPHY_DISGIGA_P7_5_MASK 0xE000 #define RTL8367C_CFG_INIPHY_PWRUP_OFFSET 5 #define RTL8367C_CFG_INIPHY_PWRUP_MASK 0x1FE0 #define RTL8367C_CFG_INIPHY_DISGIGA_OFFSET 0 #define RTL8367C_CFG_INIPHY_DISGIGA_MASK 0x1F #define RTL8367C_REG_WGPHY_MISC_1 0x1d2a #define RTL8367C_WGPHY_MISC_1_OFFSET 0 #define RTL8367C_WGPHY_MISC_1_MASK 0xFF #define RTL8367C_REG_WGPHY_MISC_2 0x1d2b #define RTL8367C_WGPHY_MISC_2_OFFSET 0 #define RTL8367C_WGPHY_MISC_2_MASK 0x3FF #define RTL8367C_REG_CFG_AFBK_GPHY_0 0x1d2c #define RTL8367C_CFG_AFBK_GPHY_0_OFFSET 0 #define RTL8367C_CFG_AFBK_GPHY_0_MASK 0x1F #define RTL8367C_REG_CFG_AFBK_GPHY_1 0x1d2d #define RTL8367C_CFG_AFBK_GPHY_1_OFFSET 0 #define RTL8367C_CFG_AFBK_GPHY_1_MASK 0xFFF #define RTL8367C_REG_EF_SLV_CTRL_0 0x1d2e #define RTL8367C_EF_SLV_BUSY_OFFSET 11 #define RTL8367C_EF_SLV_BUSY_MASK 0x800 #define RTL8367C_EF_SLV_ACK_OFFSET 10 #define RTL8367C_EF_SLV_ACK_MASK 0x400 #define RTL8367C_EF_SLV_A_OFFSET 2 #define RTL8367C_EF_SLV_A_MASK 0x3FC #define RTL8367C_EF_SLV_WE_OFFSET 1 #define RTL8367C_EF_SLV_WE_MASK 0x2 #define RTL8367C_EF_SLV_CE_OFFSET 0 #define RTL8367C_EF_SLV_CE_MASK 0x1 #define RTL8367C_REG_EF_SLV_CTRL_1 0x1d2f #define RTL8367C_REG_EF_SLV_CTRL_2 0x1d30 #define RTL8367C_REG_EFUSE_MISC_1 0x1d31 #define RTL8367C_EF_EN_EFUSE_OFFSET 10 #define RTL8367C_EF_EN_EFUSE_MASK 0x400 #define RTL8367C_EF_MODEL_ID_OFFSET 6 #define RTL8367C_EF_MODEL_ID_MASK 0x3C0 #define RTL8367C_EF_RSVD_OFFSET 2 #define RTL8367C_EF_RSVD_MASK 0x3C #define RTL8367C_EF_SYS_CLK_OFFSET 0 #define RTL8367C_EF_SYS_CLK_MASK 0x3 #define RTL8367C_REG_IO_MISC_FUNC 0x1d32 #define RTL8367C_TST_MODE_OFFSET 3 #define RTL8367C_TST_MODE_MASK 0x8 #define RTL8367C_UART_EN_OFFSET 2 #define RTL8367C_UART_EN_MASK 0x4 #define RTL8367C_INT_EN_OFFSET 1 #define RTL8367C_INT_EN_MASK 0x2 #define RTL8367C_BUZ_EN_OFFSET 0 #define RTL8367C_BUZ_EN_MASK 0x1 #define RTL8367C_REG_HTRAM_DVS 0x1d33 #define RTL8367C_HTRAM_DVS_OFFSET 0 #define RTL8367C_HTRAM_DVS_MASK 0x1 #define RTL8367C_REG_EF_SLV_CTRL_3 0x1d34 #define RTL8367C_EF_SLV_CTRL_3_OFFSET 0 #define RTL8367C_EF_SLV_CTRL_3_MASK 0x1 #define RTL8367C_REG_INBAND_EN14C 0x1d35 #define RTL8367C_INBAND_EN14C_OFFSET 0 #define RTL8367C_INBAND_EN14C_MASK 0x1 #define RTL8367C_REG_CFG_SWR_L 0x1d36 #define RTL8367C_ANARG_RDY_SWR_L_OFFSET 14 #define RTL8367C_ANARG_RDY_SWR_L_MASK 0x4000 #define RTL8367C_ANARG_VALID_SWR_L_OFFSET 13 #define RTL8367C_ANARG_VALID_SWR_L_MASK 0x2000 #define RTL8367C_SAW_SWR_L_OFFSET 9 #define RTL8367C_SAW_SWR_L_MASK 0x1E00 #define RTL8367C_SAW_VALID_SWR_L_OFFSET 8 #define RTL8367C_SAW_VALID_SWR_L_MASK 0x100 #define RTL8367C_UPS_DBGO_L_OFFSET 0 #define RTL8367C_UPS_DBGO_L_MASK 0xFF #define RTL8367C_REG_BTCAM_CTRL 0x1d37 #define RTL8367C_TCAM_RDS_OFFSET 2 #define RTL8367C_TCAM_RDS_MASK 0x1C #define RTL8367C_TCAM_MDS_OFFSET 0 #define RTL8367C_TCAM_MDS_MASK 0x3 #define RTL8367C_REG_PBRAM_BISR_CTRL 0x1d38 #define RTL8367C_HAS_HLDRMP_MD_OFFSET 9 #define RTL8367C_HAS_HLDRMP_MD_MASK 0x200 #define RTL8367C_PB_HLDRMP_MD_OFFSET 8 #define RTL8367C_PB_HLDRMP_MD_MASK 0x100 #define RTL8367C_HAS_BISR_BIRSTN_OFFSET 7 #define RTL8367C_HAS_BISR_BIRSTN_MASK 0x80 #define RTL8367C_SEC_RUN_HSA_OFFSET 6 #define RTL8367C_SEC_RUN_HSA_MASK 0x40 #define RTL8367C_HAS_HLDRMP_VAL_OFFSET 5 #define RTL8367C_HAS_HLDRMP_VAL_MASK 0x20 #define RTL8367C_HAS_BISR_PWRSTN_OFFSET 4 #define RTL8367C_HAS_BISR_PWRSTN_MASK 0x10 #define RTL8367C_SEC_RUN_PB_OFFSET 3 #define RTL8367C_SEC_RUN_PB_MASK 0x8 #define RTL8367C_PB_HLDRMP_VAL_OFFSET 2 #define RTL8367C_PB_HLDRMP_VAL_MASK 0x4 #define RTL8367C_PB_BISR_BIRSTN_OFFSET 1 #define RTL8367C_PB_BISR_BIRSTN_MASK 0x2 #define RTL8367C_PB_BISR_PWRSTN_OFFSET 0 #define RTL8367C_PB_BISR_PWRSTN_MASK 0x1 #define RTL8367C_REG_CVLANRAM_BISR_CTRL 0x1d39 #define RTL8367C_SEC_RUN_CVLAN_OFFSET 4 #define RTL8367C_SEC_RUN_CVLAN_MASK 0x10 #define RTL8367C_CVALN_HLDRMP_MD_OFFSET 3 #define RTL8367C_CVALN_HLDRMP_MD_MASK 0x8 #define RTL8367C_CVALN_HLDRMP_VAL_OFFSET 2 #define RTL8367C_CVALN_HLDRMP_VAL_MASK 0x4 #define RTL8367C_CVLAN_BISR_BIRSTN_OFFSET 1 #define RTL8367C_CVLAN_BISR_BIRSTN_MASK 0x2 #define RTL8367C_CVLAN_BISR_PWRSTN_OFFSET 0 #define RTL8367C_CVLAN_BISR_PWRSTN_MASK 0x1 #define RTL8367C_REG_CFG_1588_TIMER_EN_GPI 0x1d3a #define RTL8367C_CFG_1588_TIMER_EN_GPI_OFFSET 0 #define RTL8367C_CFG_1588_TIMER_EN_GPI_MASK 0x1 #define RTL8367C_REG_MDIO_PRMB_SUPP 0x1d3b #define RTL8367C_FIB_HIPRI_OFFSET 14 #define RTL8367C_FIB_HIPRI_MASK 0x4000 #define RTL8367C_SMT_EN_OFFSET 13 #define RTL8367C_SMT_EN_MASK 0x2000 #define RTL8367C_P4_FB_CPL_OFFSET 12 #define RTL8367C_P4_FB_CPL_MASK 0x1000 #define RTL8367C_P3_FB_CPL_OFFSET 11 #define RTL8367C_P3_FB_CPL_MASK 0x800 #define RTL8367C_P2_FB_CPL_OFFSET 10 #define RTL8367C_P2_FB_CPL_MASK 0x400 #define RTL8367C_P1_FB_CPL_OFFSET 9 #define RTL8367C_P1_FB_CPL_MASK 0x200 #define RTL8367C_P0_FB_CPL_OFFSET 8 #define RTL8367C_P0_FB_CPL_MASK 0x100 #define RTL8367C_DBG_PKG_8367N_OFFSET 7 #define RTL8367C_DBG_PKG_8367N_MASK 0x80 #define RTL8367C_DBG_PKG_8367VB_OFFSET 6 #define RTL8367C_DBG_PKG_8367VB_MASK 0x40 #define RTL8367C_CFG_DEBUG_EN_OFFSET 5 #define RTL8367C_CFG_DEBUG_EN_MASK 0x20 #define RTL8367C_CFG_TMR_ACK_OFFSET 1 #define RTL8367C_CFG_TMR_ACK_MASK 0x1E #define RTL8367C_CFG_PRMB_SUPP_OFFSET 0 #define RTL8367C_CFG_PRMB_SUPP_MASK 0x1 #define RTL8367C_REG_BOND4READ 0x1d3c #define RTL8367C_BOND_BOID0_OFFSET 8 #define RTL8367C_BOND_BOID0_MASK 0x100 #define RTL8367C_BOND_SYSCLK_OFFSET 7 #define RTL8367C_BOND_SYSCLK_MASK 0x80 #define RTL8367C_BOND_PHYMODE_OFFSET 6 #define RTL8367C_BOND_PHYMODE_MASK 0x40 #define RTL8367C_BOND_DIS_PON_BIST_OFFSET 5 #define RTL8367C_BOND_DIS_PON_BIST_MASK 0x20 #define RTL8367C_BOND_DIS_TABLE_INIT_OFFSET 4 #define RTL8367C_BOND_DIS_TABLE_INIT_MASK 0x10 #define RTL8367C_BOND_BYP_AFE_PLL_OFFSET 3 #define RTL8367C_BOND_BYP_AFE_PLL_MASK 0x8 #define RTL8367C_BOND_BYP_AFE_POR_OFFSET 2 #define RTL8367C_BOND_BYP_AFE_POR_MASK 0x4 #define RTL8367C_BOND_BISR_COND_OFFSET 1 #define RTL8367C_BOND_BISR_COND_MASK 0x2 #define RTL8367C_BOND_EF_EN_OFFSET 0 #define RTL8367C_BOND_EF_EN_MASK 0x1 #define RTL8367C_REG_REG_TO_ECO0 0x1d3d #define RTL8367C_REG_REG_TO_ECO1 0x1d3e #define RTL8367C_REG_REG_TO_ECO2 0x1d3f #define RTL8367C_REG_REG_TO_ECO3 0x1d40 #define RTL8367C_REG_REG_TO_ECO4 0x1d41 #define RTL8367C_REG_PHYSTS_CTRL0 0x1d42 #define RTL8367C_MACRX_DUPDET_EN_OFFSET 5 #define RTL8367C_MACRX_DUPDET_EN_MASK 0x20 #define RTL8367C_LNKUP_DLY_EN_OFFSET 4 #define RTL8367C_LNKUP_DLY_EN_MASK 0x10 #define RTL8367C_GE_100M_LNKUP_DLY_OFFSET 2 #define RTL8367C_GE_100M_LNKUP_DLY_MASK 0xC #define RTL8367C_PHYSTS_10M_LNKUP_DLY_OFFSET 0 #define RTL8367C_PHYSTS_10M_LNKUP_DLY_MASK 0x3 #define RTL8367C_REG_SSC_CTRL0_0 0x1d44 #define RTL8367C_SSC_CTRL0_0_SSC_TYPE_OFFSET 13 #define RTL8367C_SSC_CTRL0_0_SSC_TYPE_MASK 0x2000 #define RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_OFFSET 5 #define RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_MASK 0x1FE0 #define RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_OFFSET 4 #define RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_MASK 0x10 #define RTL8367C_SSC_CTRL0_0_DLL_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL0_0_DLL_MODE_MASK 0xC #define RTL8367C_SSC_CTRL0_0_SSC_EN_OFFSET 1 #define RTL8367C_SSC_CTRL0_0_SSC_EN_MASK 0x2 #define RTL8367C_SSC_CTRL0_0_SSC_MODE_OFFSET 0 #define RTL8367C_SSC_CTRL0_0_SSC_MODE_MASK 0x1 #define RTL8367C_REG_SSC_RDM_SEED 0x1d45 #define RTL8367C_REG_SSC_PN_POLY_SEL 0x1d46 #define RTL8367C_REG_SSC_CTRL0_3 0x1d47 #define RTL8367C_SSC_CTRL0_3_PHSFT_CNT_OFFSET 8 #define RTL8367C_SSC_CTRL0_3_PHSFT_CNT_MASK 0x7F00 #define RTL8367C_SSC_CTRL0_3_PHSFT_A_OFFSET 7 #define RTL8367C_SSC_CTRL0_3_PHSFT_A_MASK 0x80 #define RTL8367C_SSC_CTRL0_3_PHSFT_B_OFFSET 6 #define RTL8367C_SSC_CTRL0_3_PHSFT_B_MASK 0x40 #define RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_OFFSET 5 #define RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_MASK 0x20 #define RTL8367C_SSC_CTRL0_3_PHSFT_PRD_OFFSET 4 #define RTL8367C_SSC_CTRL0_3_PHSFT_PRD_MASK 0x10 #define RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_OFFSET 0 #define RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_MASK 0xF #define RTL8367C_REG_SSC_CTRL0_4 0x1d48 #define RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_OFFSET 15 #define RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_MASK 0x8000 #define RTL8367C_SSC_CTRL0_4_SSC_PERIOD_OFFSET 8 #define RTL8367C_SSC_CTRL0_4_SSC_PERIOD_MASK 0x7F00 #define RTL8367C_SSC_CTRL0_4_SSC_OFFSET_OFFSET 0 #define RTL8367C_SSC_CTRL0_4_SSC_OFFSET_MASK 0xFF #define RTL8367C_REG_SSC_CTRL0_5 0x1d49 #define RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_OFFSET 15 #define RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_MASK 0x8000 #define RTL8367C_SSC_CTRL0_5_PH_OFS_OFFSET 10 #define RTL8367C_SSC_CTRL0_5_PH_OFS_MASK 0x7C00 #define RTL8367C_SSC_CTRL0_5_SSC_STEP_OFFSET 4 #define RTL8367C_SSC_CTRL0_5_SSC_STEP_MASK 0x3F0 #define RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_MASK 0xC #define RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_OFFSET 0 #define RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_MASK 0x3 #define RTL8367C_REG_SSC_STS0 0x1d4a #define RTL8367C_SSC_STS0_OFS_BUSY_OFFSET 13 #define RTL8367C_SSC_STS0_OFS_BUSY_MASK 0x2000 #define RTL8367C_SSC_STS0_OFS_TOTAL_R_OFFSET 8 #define RTL8367C_SSC_STS0_OFS_TOTAL_R_MASK 0x1F00 #define RTL8367C_SSC_STS0_CNT_GRY0_OFFSET 4 #define RTL8367C_SSC_STS0_CNT_GRY0_MASK 0xF0 #define RTL8367C_SSC_STS0_OFS_GRY0_OFFSET 0 #define RTL8367C_SSC_STS0_OFS_GRY0_MASK 0xF #define RTL8367C_REG_SSC_CTRL1_0 0x1d4b #define RTL8367C_SSC_CTRL1_0_SSC_TYPE_OFFSET 13 #define RTL8367C_SSC_CTRL1_0_SSC_TYPE_MASK 0x2000 #define RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_OFFSET 5 #define RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_MASK 0x1FE0 #define RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_OFFSET 4 #define RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_MASK 0x10 #define RTL8367C_SSC_CTRL1_0_DLL_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL1_0_DLL_MODE_MASK 0xC #define RTL8367C_SSC_CTRL1_0_SSC_EN_OFFSET 1 #define RTL8367C_SSC_CTRL1_0_SSC_EN_MASK 0x2 #define RTL8367C_SSC_CTRL1_0_SSC_MODE_OFFSET 0 #define RTL8367C_SSC_CTRL1_0_SSC_MODE_MASK 0x1 #define RTL8367C_REG_SSC_RDM_SEED1 0x1d4c #define RTL8367C_REG_SSC_PN_POLY_SEL1 0x1d4d #define RTL8367C_REG_SSC_CTRL1_3 0x1d4e #define RTL8367C_SSC_CTRL1_3_PHSFT_CNT_OFFSET 8 #define RTL8367C_SSC_CTRL1_3_PHSFT_CNT_MASK 0x7F00 #define RTL8367C_SSC_CTRL1_3_PHSFT_A_OFFSET 7 #define RTL8367C_SSC_CTRL1_3_PHSFT_A_MASK 0x80 #define RTL8367C_SSC_CTRL1_3_PHSFT_B_OFFSET 6 #define RTL8367C_SSC_CTRL1_3_PHSFT_B_MASK 0x40 #define RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_OFFSET 5 #define RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_MASK 0x20 #define RTL8367C_SSC_CTRL1_3_PHSFT_PRD_OFFSET 4 #define RTL8367C_SSC_CTRL1_3_PHSFT_PRD_MASK 0x10 #define RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_OFFSET 0 #define RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_MASK 0xF #define RTL8367C_REG_SSC_CTRL1_4 0x1d4f #define RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_OFFSET 15 #define RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_MASK 0x8000 #define RTL8367C_SSC_CTRL1_4_SSC_PERIOD_OFFSET 8 #define RTL8367C_SSC_CTRL1_4_SSC_PERIOD_MASK 0x7F00 #define RTL8367C_SSC_CTRL1_4_SSC_OFFSET_OFFSET 0 #define RTL8367C_SSC_CTRL1_4_SSC_OFFSET_MASK 0xFF #define RTL8367C_REG_SSC_CTRL1_5 0x1d50 #define RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_OFFSET 15 #define RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_MASK 0x8000 #define RTL8367C_SSC_CTRL1_5_PH_OFS_OFFSET 10 #define RTL8367C_SSC_CTRL1_5_PH_OFS_MASK 0x7C00 #define RTL8367C_SSC_CTRL1_5_SSC_STEP_OFFSET 4 #define RTL8367C_SSC_CTRL1_5_SSC_STEP_MASK 0x3F0 #define RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_MASK 0xC #define RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_OFFSET 0 #define RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_MASK 0x3 #define RTL8367C_REG_SSC_STS1 0x1d51 #define RTL8367C_SSC_STS1_OFS_BUSY_OFFSET 13 #define RTL8367C_SSC_STS1_OFS_BUSY_MASK 0x2000 #define RTL8367C_SSC_STS1_OFS_TOTAL_R_OFFSET 8 #define RTL8367C_SSC_STS1_OFS_TOTAL_R_MASK 0x1F00 #define RTL8367C_SSC_STS1_CNT_GRY0_OFFSET 4 #define RTL8367C_SSC_STS1_CNT_GRY0_MASK 0xF0 #define RTL8367C_SSC_STS1_OFS_GRY0_OFFSET 0 #define RTL8367C_SSC_STS1_OFS_GRY0_MASK 0xF #define RTL8367C_REG_SSC_CTRL2_0 0x1d52 #define RTL8367C_SSC_CTRL2_0_SSC_TYPE_OFFSET 13 #define RTL8367C_SSC_CTRL2_0_SSC_TYPE_MASK 0x2000 #define RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_OFFSET 5 #define RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_MASK 0x1FE0 #define RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_OFFSET 4 #define RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_MASK 0x10 #define RTL8367C_SSC_CTRL2_0_DLL_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL2_0_DLL_MODE_MASK 0xC #define RTL8367C_SSC_CTRL2_0_SSC_EN_OFFSET 1 #define RTL8367C_SSC_CTRL2_0_SSC_EN_MASK 0x2 #define RTL8367C_SSC_CTRL2_0_SSC_MODE_OFFSET 0 #define RTL8367C_SSC_CTRL2_0_SSC_MODE_MASK 0x1 #define RTL8367C_REG_SSC_RDM_SEED2 0x1d53 #define RTL8367C_REG_SSC_PN_POLY_SEL2 0x1d54 #define RTL8367C_REG_SSC_CTRL2_3 0x1d55 #define RTL8367C_SSC_CTRL2_3_PHSFT_CNT_OFFSET 8 #define RTL8367C_SSC_CTRL2_3_PHSFT_CNT_MASK 0x7F00 #define RTL8367C_SSC_CTRL2_3_PHSFT_A_OFFSET 7 #define RTL8367C_SSC_CTRL2_3_PHSFT_A_MASK 0x80 #define RTL8367C_SSC_CTRL2_3_PHSFT_B_OFFSET 6 #define RTL8367C_SSC_CTRL2_3_PHSFT_B_MASK 0x40 #define RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_OFFSET 5 #define RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_MASK 0x20 #define RTL8367C_SSC_CTRL2_3_PHSFT_PRD_OFFSET 4 #define RTL8367C_SSC_CTRL2_3_PHSFT_PRD_MASK 0x10 #define RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_OFFSET 0 #define RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_MASK 0xF #define RTL8367C_REG_SSC_CTRL2_4 0x1d56 #define RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_OFFSET 15 #define RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_MASK 0x8000 #define RTL8367C_SSC_CTRL2_4_SSC_PERIOD_OFFSET 8 #define RTL8367C_SSC_CTRL2_4_SSC_PERIOD_MASK 0x7F00 #define RTL8367C_SSC_CTRL2_4_SSC_OFFSET_OFFSET 0 #define RTL8367C_SSC_CTRL2_4_SSC_OFFSET_MASK 0xFF #define RTL8367C_REG_SSC_CTRL2_5 0x1d57 #define RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_OFFSET 15 #define RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_MASK 0x8000 #define RTL8367C_SSC_CTRL2_5_PH_OFS_OFFSET 10 #define RTL8367C_SSC_CTRL2_5_PH_OFS_MASK 0x7C00 #define RTL8367C_SSC_CTRL2_5_SSC_STEP_OFFSET 4 #define RTL8367C_SSC_CTRL2_5_SSC_STEP_MASK 0x3F0 #define RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_MASK 0xC #define RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_OFFSET 0 #define RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_MASK 0x3 #define RTL8367C_REG_SSC_STS2 0x1d58 #define RTL8367C_SSC_STS2_OFS_BUSY_OFFSET 13 #define RTL8367C_SSC_STS2_OFS_BUSY_MASK 0x2000 #define RTL8367C_SSC_STS2_OFS_TOTAL_R_OFFSET 8 #define RTL8367C_SSC_STS2_OFS_TOTAL_R_MASK 0x1F00 #define RTL8367C_SSC_STS2_CNT_GRY0_OFFSET 4 #define RTL8367C_SSC_STS2_CNT_GRY0_MASK 0xF0 #define RTL8367C_SSC_STS2_OFS_GRY0_OFFSET 0 #define RTL8367C_SSC_STS2_OFS_GRY0_MASK 0xF #define RTL8367C_REG_SSC_CTRL3_0 0x1d59 #define RTL8367C_SSC_CTRL3_0_SSC_TYPE_OFFSET 13 #define RTL8367C_SSC_CTRL3_0_SSC_TYPE_MASK 0x2000 #define RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_OFFSET 5 #define RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_MASK 0x1FE0 #define RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_OFFSET 4 #define RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_MASK 0x10 #define RTL8367C_SSC_CTRL3_0_DLL_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL3_0_DLL_MODE_MASK 0xC #define RTL8367C_SSC_CTRL3_0_SSC_EN_OFFSET 1 #define RTL8367C_SSC_CTRL3_0_SSC_EN_MASK 0x2 #define RTL8367C_SSC_CTRL3_0_SSC_MODE_OFFSET 0 #define RTL8367C_SSC_CTRL3_0_SSC_MODE_MASK 0x1 #define RTL8367C_REG_SSC_RDM_SEED3 0x1d5a #define RTL8367C_REG_SSC_PN_POLY_SEL3 0x1d5b #define RTL8367C_REG_SSC_CTRL3_3 0x1d5c #define RTL8367C_SSC_CTRL3_3_PHSFT_CNT_OFFSET 8 #define RTL8367C_SSC_CTRL3_3_PHSFT_CNT_MASK 0x7F00 #define RTL8367C_SSC_CTRL3_3_PHSFT_A_OFFSET 7 #define RTL8367C_SSC_CTRL3_3_PHSFT_A_MASK 0x80 #define RTL8367C_SSC_CTRL3_3_PHSFT_B_OFFSET 6 #define RTL8367C_SSC_CTRL3_3_PHSFT_B_MASK 0x40 #define RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_OFFSET 5 #define RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_MASK 0x20 #define RTL8367C_SSC_CTRL3_3_PHSFT_PRD_OFFSET 4 #define RTL8367C_SSC_CTRL3_3_PHSFT_PRD_MASK 0x10 #define RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_OFFSET 0 #define RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_MASK 0xF #define RTL8367C_REG_SSC_CTRL3_4 0x1d5d #define RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_OFFSET 15 #define RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_MASK 0x8000 #define RTL8367C_SSC_CTRL3_4_SSC_PERIOD_OFFSET 8 #define RTL8367C_SSC_CTRL3_4_SSC_PERIOD_MASK 0x7F00 #define RTL8367C_SSC_CTRL3_4_SSC_OFFSET_OFFSET 0 #define RTL8367C_SSC_CTRL3_4_SSC_OFFSET_MASK 0xFF #define RTL8367C_REG_SSC_CTRL3_5 0x1d5e #define RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_OFFSET 15 #define RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_MASK 0x8000 #define RTL8367C_SSC_CTRL3_5_PH_OFS_OFFSET 10 #define RTL8367C_SSC_CTRL3_5_PH_OFS_MASK 0x7C00 #define RTL8367C_SSC_CTRL3_5_SSC_STEP_OFFSET 4 #define RTL8367C_SSC_CTRL3_5_SSC_STEP_MASK 0x3F0 #define RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_OFFSET 2 #define RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_MASK 0xC #define RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_OFFSET 0 #define RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_MASK 0x3 #define RTL8367C_REG_SSC_STS3 0x1d5f #define RTL8367C_SSC_STS3_OFS_BUSY_OFFSET 13 #define RTL8367C_SSC_STS3_OFS_BUSY_MASK 0x2000 #define RTL8367C_SSC_STS3_OFS_TOTAL_R_OFFSET 8 #define RTL8367C_SSC_STS3_OFS_TOTAL_R_MASK 0x1F00 #define RTL8367C_SSC_STS3_CNT_GRY0_OFFSET 4 #define RTL8367C_SSC_STS3_CNT_GRY0_MASK 0xF0 #define RTL8367C_SSC_STS3_OFS_GRY0_OFFSET 0 #define RTL8367C_SSC_STS3_OFS_GRY0_MASK 0xF #define RTL8367C_REG_PHY_POLL_CFG13 0x1d60 #define RTL8367C_REG_PHY_POLL_CFG14 0x1d61 #define RTL8367C_REG_FRC_SYS_CLK 0x1d62 #define RTL8367C_SYSCLK_FRC_MD_OFFSET 1 #define RTL8367C_SYSCLK_FRC_MD_MASK 0x2 #define RTL8367C_SYSCLK_FRC_VAL_OFFSET 0 #define RTL8367C_SYSCLK_FRC_VAL_MASK 0x1 #define RTL8367C_REG_AFE_SSC_CTRL 0x1d63 #define RTL8367C_PH_RSTB_TXD1_OFFSET 9 #define RTL8367C_PH_RSTB_TXD1_MASK 0x200 #define RTL8367C_PH_RSTB_TXC1_OFFSET 8 #define RTL8367C_PH_RSTB_TXC1_MASK 0x100 #define RTL8367C_PH_RSTB_TXD0_OFFSET 7 #define RTL8367C_PH_RSTB_TXD0_MASK 0x80 #define RTL8367C_PH_RSTB_TXC0_OFFSET 6 #define RTL8367C_PH_RSTB_TXC0_MASK 0x40 #define RTL8367C_PH_RSTBSYS_OFFSET 5 #define RTL8367C_PH_RSTBSYS_MASK 0x20 #define RTL8367C_PH_RSTB8051_OFFSET 4 #define RTL8367C_PH_RSTB8051_MASK 0x10 #define RTL8367C_OREG_SSC_OFFSET 0 #define RTL8367C_OREG_SSC_MASK 0xF #define RTL8367C_REG_BUFF_RST_CTRL0 0x1d64 #define RTL8367C_BUFFRST_TXESD_EN_OFFSET 13 #define RTL8367C_BUFFRST_TXESD_EN_MASK 0x2000 #define RTL8367C_BUFF_RST_TIME_LONG_OFFSET 8 #define RTL8367C_BUFF_RST_TIME_LONG_MASK 0x1F00 #define RTL8367C_BUFF_RST_TIME_SHORT_OFFSET 3 #define RTL8367C_BUFF_RST_TIME_SHORT_MASK 0xF8 #define RTL8367C_SW_BUFF_RST_OFFSET 2 #define RTL8367C_SW_BUFF_RST_MASK 0x4 #define RTL8367C_IMS_BUFF_RST_OFFSET 1 #define RTL8367C_IMS_BUFF_RST_MASK 0x2 #define RTL8367C_IMR_BUFF_RST_OFFSET 0 #define RTL8367C_IMR_BUFF_RST_MASK 0x1 #define RTL8367C_REG_BUFF_RST_CTRL1 0x1d65 #define RTL8367C_BUFFRST_SYSOVER_EN_OFFSET 10 #define RTL8367C_BUFFRST_SYSOVER_EN_MASK 0x400 #define RTL8367C_BUFFRST_SYSOVER_THR_OFFSET 0 #define RTL8367C_BUFFRST_SYSOVER_THR_MASK 0x3FF #define RTL8367C_REG_BUFF_RST_CTRL2 0x1d66 #define RTL8367C_BUFFRST_QOVER_EN_OFFSET 10 #define RTL8367C_BUFFRST_QOVER_EN_MASK 0x400 #define RTL8367C_BUFFRST_QOVER_THR_OFFSET 0 #define RTL8367C_BUFFRST_QOVER_THR_MASK 0x3FF #define RTL8367C_REG_BUFF_RST_CTRL3 0x1d67 #define RTL8367C_DSC_TIMER_OFFSET 11 #define RTL8367C_DSC_TIMER_MASK 0x7800 #define RTL8367C_BUFFRST_DSCOVER_THR_OFFSET 1 #define RTL8367C_BUFFRST_DSCOVER_THR_MASK 0x7FE #define RTL8367C_BUFFRST_DSCOVER_EN_OFFSET 0 #define RTL8367C_BUFFRST_DSCOVER_EN_MASK 0x1 #define RTL8367C_REG_BUFF_RST_CTRL4 0x1d68 #define RTL8367C_INDSC_TIMER_OFFSET 11 #define RTL8367C_INDSC_TIMER_MASK 0x7800 #define RTL8367C_BUFFRST_INDSCOVER_THR_OFFSET 1 #define RTL8367C_BUFFRST_INDSCOVER_THR_MASK 0x7FE #define RTL8367C_BUFFRST_INDSCOVER_EN_OFFSET 0 #define RTL8367C_BUFFRST_INDSCOVER_EN_MASK 0x1 #define RTL8367C_REG_BUFF_RST_CTRL5 0x1d69 #define RTL8367C_TX_ESD_MODE_OFFSET 8 #define RTL8367C_TX_ESD_MODE_MASK 0x100 #define RTL8367C_TX_ESD_LVL_OFFSET 0 #define RTL8367C_TX_ESD_LVL_MASK 0xFF #define RTL8367C_REG_TOP_CON0 0x1d70 #define RTL8367C_TOP_CON0_SDS_PWR_ISO_1_OFFSET 15 #define RTL8367C_TOP_CON0_SDS_PWR_ISO_1_MASK 0x8000 #define RTL8367C_OCP_TIMEOUT_P7_5_OFFSET 12 #define RTL8367C_OCP_TIMEOUT_P7_5_MASK 0x7000 #define RTL8367C_FIB_EEE_AB_OFFSET 11 #define RTL8367C_FIB_EEE_AB_MASK 0x800 #define RTL8367C_ADCCKIEN_OFFSET 10 #define RTL8367C_ADCCKIEN_MASK 0x400 #define RTL8367C_OCP_TIMEOUT_OFFSET 5 #define RTL8367C_OCP_TIMEOUT_MASK 0x3E0 #define RTL8367C_TOP_CON0_SDS_PWR_ISO_OFFSET 4 #define RTL8367C_TOP_CON0_SDS_PWR_ISO_MASK 0x10 #define RTL8367C_RG2_TXC_SEL_OFFSET 3 #define RTL8367C_RG2_TXC_SEL_MASK 0x8 #define RTL8367C_RG1TXC_SEL_OFFSET 2 #define RTL8367C_RG1TXC_SEL_MASK 0x4 #define RTL8367C_SYNC_1588_EN_OFFSET 1 #define RTL8367C_SYNC_1588_EN_MASK 0x2 #define RTL8367C_LS_MODE_OFFSET 0 #define RTL8367C_LS_MODE_MASK 0x1 #define RTL8367C_REG_TOP_CON1 0x1d71 #define RTL8367C_TA_CHK_EN_OFFSET 2 #define RTL8367C_TA_CHK_EN_MASK 0x4 #define RTL8367C_SLV_EG_SEL_OFFSET 1 #define RTL8367C_SLV_EG_SEL_MASK 0x2 #define RTL8367C_IIC_OP_DRAIN_OFFSET 0 #define RTL8367C_IIC_OP_DRAIN_MASK 0x1 #define RTL8367C_REG_SWR_FPWM 0x1d72 #define RTL8367C_SWR_FPWM_OFFSET 0 #define RTL8367C_SWR_FPWM_MASK 0x1 #define RTL8367C_REG_EEEP_CTRL_500M 0x1d73 #define RTL8367C_REG_SHORT_PRMB 0x1d74 #define RTL8367C_SHORT_PRMB_OFFSET 0 #define RTL8367C_SHORT_PRMB_MASK 0x1 #define RTL8367C_REG_INDSC_THR_CTRL 0x1d75 #define RTL8367C_INDSC_THR_CTRL_OFFSET 0 #define RTL8367C_INDSC_THR_CTRL_MASK 0x7FF #define RTL8367C_REG_SET_PAD_CTRL_NEW 0x1d80 #define RTL8367C_SET_PAD_CTRL_NEW_OFFSET 0 #define RTL8367C_SET_PAD_CTRL_NEW_MASK 0x1 #define RTL8367C_REG_SET_PAD_DRI_0 0x1d81 #define RTL8367C_REG_SET_PAD_DRI_1 0x1d82 #define RTL8367C_REG_SET_PAD_DRI_2 0x1d83 #define RTL8367C_REG_SET_PAD_SLEW_0 0x1d84 #define RTL8367C_REG_SET_PAD_SLEW_1 0x1d85 #define RTL8367C_REG_SET_PAD_SLEW_2 0x1d86 #define RTL8367C_REG_SET_PAD_SMT_0 0x1d87 #define RTL8367C_REG_SET_PAD_SMT_1 0x1d88 #define RTL8367C_REG_SET_PAD_SMT_2 0x1d89 #define RTL8367C_REG_M_I2C_CTL_STA_REG 0x1d8a #define RTL8367C_TX_RX_DATA_OFFSET 8 #define RTL8367C_TX_RX_DATA_MASK 0xFF00 #define RTL8367C_DUMB_RW_ERR_OFFSET 7 #define RTL8367C_DUMB_RW_ERR_MASK 0x80 #define RTL8367C_SLV_ACK_FLAG_OFFSET 6 #define RTL8367C_SLV_ACK_FLAG_MASK 0x40 #define RTL8367C_M_I2C_BUS_IDLE_OFFSET 5 #define RTL8367C_M_I2C_BUS_IDLE_MASK 0x20 #define RTL8367C_I2C_CMD_TYPE_OFFSET 1 #define RTL8367C_I2C_CMD_TYPE_MASK 0x1E #define RTL8367C_I2C_CMD_EXEC_OFFSET 0 #define RTL8367C_I2C_CMD_EXEC_MASK 0x1 #define RTL8367C_REG_M_I2C_DUMB_RW_ADDR_0 0x1d8b #define RTL8367C_REG_M_I2C_DUMB_RW_ADDR_1 0x1d8c #define RTL8367C_REG_M_I2C_DUMB_RW_DATA_0 0x1d8d #define RTL8367C_REG_M_I2C_DUMB_RW_DATA_1 0x1d8e #define RTL8367C_REG_M_I2C_DUMB_RW_CTL 0x1d8f #define RTL8367C_DUMB_I2C_CTL_CODE_OFFSET 8 #define RTL8367C_DUMB_I2C_CTL_CODE_MASK 0x7F00 #define RTL8367C_DUMB_RW_I2C_FORMAT_OFFSET 4 #define RTL8367C_DUMB_RW_I2C_FORMAT_MASK 0x10 #define RTL8367C_DUMB_RW_DATA_MODE_OFFSET 2 #define RTL8367C_DUMB_RW_DATA_MODE_MASK 0xC #define RTL8367C_DUMB_RW_ADDR_MODE_OFFSET 0 #define RTL8367C_DUMB_RW_ADDR_MODE_MASK 0x3 #define RTL8367C_REG_M_I2C_SYS_CTL 0x1d90 #define RTL8367C_M_I2C_SCL_IO_MUX_OFFSET 12 #define RTL8367C_M_I2C_SCL_IO_MUX_MASK 0x3000 #define RTL8367C_M_I2C_SDA_IO_MUX_OFFSET 10 #define RTL8367C_M_I2C_SDA_IO_MUX_MASK 0xC00 #define RTL8367C_M_I2C_SDA_OD_EN_OFFSET 9 #define RTL8367C_M_I2C_SDA_OD_EN_MASK 0x200 #define RTL8367C_M_I2C_SCL_OD_EN_OFFSET 8 #define RTL8367C_M_I2C_SCL_OD_EN_MASK 0x100 #define RTL8367C_M_I2C_SCL_F_DIV_OFFSET 0 #define RTL8367C_M_I2C_SCL_F_DIV_MASK 0xFF #define RTL8367C_REG_HT_PB_SRAM_CTRL 0x1da0 #define RTL8367C_HTPB_RW_OFFSET 2 #define RTL8367C_HTPB_RW_MASK 0x4 #define RTL8367C_HTPB_SEL_OFFSET 1 #define RTL8367C_HTPB_SEL_MASK 0x2 #define RTL8367C_HTPB_CE_OFFSET 0 #define RTL8367C_HTPB_CE_MASK 0x1 #define RTL8367C_REG_HT_PB_SRAM_ADDR 0x1da1 #define RTL8367C_REG_HT_PB_SRAM_DIN0 0x1da2 #define RTL8367C_REG_HT_PB_SRAM_DIN1 0x1da3 #define RTL8367C_REG_HT_PB_SRAM_DOUT0 0x1da4 #define RTL8367C_REG_HT_PB_SRAM_DOUT1 0x1da5 #define RTL8367C_REG_PHY_STAT_0 0x1db0 #define RTL8367C_REG_PHY_STAT_1 0x1db1 #define RTL8367C_REG_PHY_STAT_2 0x1db2 #define RTL8367C_REG_PHY_STAT_3 0x1db3 #define RTL8367C_REG_PHY_STAT_4 0x1db4 #define RTL8367C_REG_PHY_STAT_5 0x1db5 #define RTL8367C_REG_PHY_STAT_6 0x1db6 #define RTL8367C_REG_PHY_STAT_7 0x1db7 #define RTL8367C_REG_SDS_STAT_0 0x1db8 #define RTL8367C_REG_SDS_STAT_1 0x1db9 #define RTL8367C_REG_MAC_LINK_STAT_0 0x1dba #define RTL8367C_MAC_LINK_STAT_CUR_0_OFFSET 8 #define RTL8367C_MAC_LINK_STAT_CUR_0_MASK 0xFF00 #define RTL8367C_MAC_LINK_STAT_LATCH_0_OFFSET 0 #define RTL8367C_MAC_LINK_STAT_LATCH_0_MASK 0xFF #define RTL8367C_REG_MAC_LINK_STAT_1 0x1dbb #define RTL8367C_MAC_LINK_STAT_1_Reserved_OFFSET 6 #define RTL8367C_MAC_LINK_STAT_1_Reserved_MASK 0xFFC0 #define RTL8367C_MAC_LINK_STAT_CUR_1_OFFSET 3 #define RTL8367C_MAC_LINK_STAT_CUR_1_MASK 0x38 #define RTL8367C_MAC_LINK_STAT_LATCH_1_OFFSET 0 #define RTL8367C_MAC_LINK_STAT_LATCH_1_MASK 0x7 #define RTL8367C_REG_MISC_CONTROL_1 0x1dc0 #define RTL8367C_P7_FB_CPL_OFFSET 2 #define RTL8367C_P7_FB_CPL_MASK 0x4 #define RTL8367C_P6_FB_CPL_OFFSET 1 #define RTL8367C_P6_FB_CPL_MASK 0x2 #define RTL8367C_P5_FB_CPL_OFFSET 0 #define RTL8367C_P5_FB_CPL_MASK 0x1 #define RTL8367C_REG_SDS_MISC_1 0x1dc1 #define RTL8367C_CFG_SGMII_RXFC_1_OFFSET 14 #define RTL8367C_CFG_SGMII_RXFC_1_MASK 0x4000 #define RTL8367C_CFG_SGMII_TXFC_1_OFFSET 13 #define RTL8367C_CFG_SGMII_TXFC_1_MASK 0x2000 #define RTL8367C_CFG_MAC9_SEL_HSGMII_OFFSET 11 #define RTL8367C_CFG_MAC9_SEL_HSGMII_MASK 0x800 #define RTL8367C_CFG_SGMII_FDUP_1_OFFSET 10 #define RTL8367C_CFG_SGMII_FDUP_1_MASK 0x400 #define RTL8367C_CFG_SGMII_LINK_1_OFFSET 9 #define RTL8367C_CFG_SGMII_LINK_1_MASK 0x200 #define RTL8367C_CFG_SGMII_SPD_1_OFFSET 7 #define RTL8367C_CFG_SGMII_SPD_1_MASK 0x180 #define RTL8367C_CFG_MAC9_SEL_SGMII_OFFSET 6 #define RTL8367C_CFG_MAC9_SEL_SGMII_MASK 0x40 #define RTL8367C_CFG_SDS_MODE_14C_1_OFFSET 0 #define RTL8367C_CFG_SDS_MODE_14C_1_MASK 0x7 #define RTL8367C_REG_FIBER_CFG_2_1 0x1dc2 #define RTL8367C_SDS_RX_DISABLE_1_OFFSET 6 #define RTL8367C_SDS_RX_DISABLE_1_MASK 0xC0 #define RTL8367C_SDS_TX_DISABLE_1_OFFSET 4 #define RTL8367C_SDS_TX_DISABLE_1_MASK 0x30 #define RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_OFFSET 2 #define RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_MASK 0xC #define RTL8367C_SDS_FRC_LD_1_OFFSET 0 #define RTL8367C_SDS_FRC_LD_1_MASK 0x3 #define RTL8367C_REG_FIBER_CFG_1_1 0x1dc3 #define RTL8367C_SDS_FRC_REG4_1_OFFSET 12 #define RTL8367C_SDS_FRC_REG4_1_MASK 0x1000 #define RTL8367C_SDS_FRC_REG4_FIB100_1_OFFSET 11 #define RTL8367C_SDS_FRC_REG4_FIB100_1_MASK 0x800 #define RTL8367C_SDS_FRC_MODE_1_OFFSET 3 #define RTL8367C_SDS_FRC_MODE_1_MASK 0x8 #define RTL8367C_SDS_MODE_1_OFFSET 0 #define RTL8367C_SDS_MODE_1_MASK 0x7 #define RTL8367C_REG_PHYSTS_CTRL0_1 0x1dc4 #define RTL8367C_LNKUP_DLY_EN_EXT2_OFFSET 9 #define RTL8367C_LNKUP_DLY_EN_EXT2_MASK 0x200 #define RTL8367C_GE_100M_LNKUP_DLY_EXT2_OFFSET 7 #define RTL8367C_GE_100M_LNKUP_DLY_EXT2_MASK 0x180 #define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_OFFSET 5 #define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_MASK 0x60 #define RTL8367C_LNKUP_DLY_EN_EXT1_OFFSET 4 #define RTL8367C_LNKUP_DLY_EN_EXT1_MASK 0x10 #define RTL8367C_GE_100M_LNKUP_DLY_EXT1_OFFSET 2 #define RTL8367C_GE_100M_LNKUP_DLY_EXT1_MASK 0xC #define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_OFFSET 0 #define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_MASK 0x3 #define RTL8367C_REG_FIBER_CFG_3_1 0x1dc5 #define RTL8367C_FIBER_CFG_3_1_OFFSET 0 #define RTL8367C_FIBER_CFG_3_1_MASK 0xFFF #define RTL8367C_REG_FIBER_CFG_4_1 0x1dc6 #define RTL8367C_REG_BUFF_RST_CTRL2_2 0x1dc7 #define RTL8367C_Cfg_buffrst_sysover_thr_1_OFFSET 3 #define RTL8367C_Cfg_buffrst_sysover_thr_1_MASK 0x8 #define RTL8367C_Cfg_buffrst_qover_thr_OFFSET 2 #define RTL8367C_Cfg_buffrst_qover_thr_MASK 0x4 #define RTL8367C_Cfg_buffrst_indscover_thr_1_OFFSET 1 #define RTL8367C_Cfg_buffrst_indscover_thr_1_MASK 0x2 #define RTL8367C_Cfg_buffrst_dscover_thr_1_OFFSET 0 #define RTL8367C_Cfg_buffrst_dscover_thr_1_MASK 0x1 #define RTL8367C_REG_PHY_DEBUG_CNT_CTRL 0x1dc8 #define RTL8367C_PHY_MIB_RST_7_OFFSET 15 #define RTL8367C_PHY_MIB_RST_7_MASK 0x8000 #define RTL8367C_PHY_MIB_RST_6_OFFSET 14 #define RTL8367C_PHY_MIB_RST_6_MASK 0x4000 #define RTL8367C_PHY_MIB_RST_5_OFFSET 13 #define RTL8367C_PHY_MIB_RST_5_MASK 0x2000 #define RTL8367C_PHY_MIB_RST_4_OFFSET 12 #define RTL8367C_PHY_MIB_RST_4_MASK 0x1000 #define RTL8367C_PHY_MIB_RST_3_OFFSET 11 #define RTL8367C_PHY_MIB_RST_3_MASK 0x800 #define RTL8367C_PHY_MIB_RST_2_OFFSET 10 #define RTL8367C_PHY_MIB_RST_2_MASK 0x400 #define RTL8367C_PHY_MIB_RST_1_OFFSET 9 #define RTL8367C_PHY_MIB_RST_1_MASK 0x200 #define RTL8367C_PHY_MIB_RST_0_OFFSET 8 #define RTL8367C_PHY_MIB_RST_0_MASK 0x100 #define RTL8367C_PHY_MIB_EN_7_OFFSET 7 #define RTL8367C_PHY_MIB_EN_7_MASK 0x80 #define RTL8367C_PHY_MIB_EN_6_OFFSET 6 #define RTL8367C_PHY_MIB_EN_6_MASK 0x40 #define RTL8367C_PHY_MIB_EN_5_OFFSET 5 #define RTL8367C_PHY_MIB_EN_5_MASK 0x20 #define RTL8367C_PHY_MIB_EN_4_OFFSET 4 #define RTL8367C_PHY_MIB_EN_4_MASK 0x10 #define RTL8367C_PHY_MIB_EN_3_OFFSET 3 #define RTL8367C_PHY_MIB_EN_3_MASK 0x8 #define RTL8367C_PHY_MIB_EN_2_OFFSET 2 #define RTL8367C_PHY_MIB_EN_2_MASK 0x4 #define RTL8367C_PHY_MIB_EN_1_OFFSET 1 #define RTL8367C_PHY_MIB_EN_1_MASK 0x2 #define RTL8367C_PHY_MIB_EN_0_OFFSET 0 #define RTL8367C_PHY_MIB_EN_0_MASK 0x1 #define RTL8367C_REG_TXPKT_CNT_L_0 0x1dc9 #define RTL8367C_REG_TXPKT_CNT_H_0 0x1dca #define RTL8367C_REG_RXPKT_CNT_L_0 0x1dcb #define RTL8367C_REG_RXPKT_CNT_H_0 0x1dcc #define RTL8367C_REG_TX_CRC_0 0x1dcd #define RTL8367C_REG_RX_CRC_0 0x1dce #define RTL8367C_REG_TXPKT_CNT_L_1 0x1dcf #define RTL8367C_REG_TXPKT_CNT_H_1 0x1dd0 #define RTL8367C_REG_RXPKT_CNT_L_1 0x1dd1 #define RTL8367C_REG_RXPKT_CNT_H_1 0x1dd2 #define RTL8367C_REG_TX_CRC_1 0x1dd3 #define RTL8367C_REG_RX_CRC_1 0x1dd4 #define RTL8367C_REG_TXPKT_CNT_L_2 0x1dd5 #define RTL8367C_REG_TXPKT_CNT_H_2 0x1dd6 #define RTL8367C_REG_RXPKT_CNT_L_2 0x1dd7 #define RTL8367C_REG_RXPKT_CNT_H_2 0x1dd8 #define RTL8367C_REG_TX_CRC_2 0x1dd9 #define RTL8367C_REG_RX_CRC_2 0x1dda #define RTL8367C_REG_TXPKT_CNT_L_3 0x1ddb #define RTL8367C_REG_TXPKT_CNT_H_3 0x1ddc #define RTL8367C_REG_RXPKT_CNT_L_3 0x1ddd #define RTL8367C_REG_RXPKT_CNT_H_3 0x1dde #define RTL8367C_REG_TX_CRC_3 0x1ddf #define RTL8367C_REG_RX_CRC_3 0x1de0 #define RTL8367C_REG_TXPKT_CNT_L_4 0x1de1 #define RTL8367C_REG_TXPKT_CNT_H_4 0x1de2 #define RTL8367C_REG_RXPKT_CNT_L_4 0x1de3 #define RTL8367C_REG_RXPKT_CNT_H_4 0x1de4 #define RTL8367C_REG_TX_CRC_4 0x1de5 #define RTL8367C_REG_RX_CRC_4 0x1de6 #define RTL8367C_REG_TXPKT_CNT_L_5 0x1de7 #define RTL8367C_REG_TXPKT_CNT_H_5 0x1de8 #define RTL8367C_REG_RXPKT_CNT_L_5 0x1de9 #define RTL8367C_REG_RXPKT_CNT_H_5 0x1dea #define RTL8367C_REG_TX_CRC_5 0x1deb #define RTL8367C_REG_RX_CRC_5 0x1dec #define RTL8367C_REG_TXPKT_CNT_L_6 0x1ded #define RTL8367C_REG_TXPKT_CNT_H_6 0x1dee #define RTL8367C_REG_RXPKT_CNT_L_6 0x1def #define RTL8367C_REG_RXPKT_CNT_H_6 0x1df0 #define RTL8367C_REG_TX_CRC_6 0x1df1 #define RTL8367C_REG_RX_CRC_6 0x1df2 #define RTL8367C_REG_TXPKT_CNT_L_7 0x1df3 #define RTL8367C_REG_TXPKT_CNT_H_7 0x1df4 #define RTL8367C_REG_RXPKT_CNT_L_7 0x1df5 #define RTL8367C_REG_RXPKT_CNT_H_7 0x1df6 #define RTL8367C_REG_TX_CRC_7 0x1df7 #define RTL8367C_REG_RX_CRC_7 0x1df8 #define RTL8367C_REG_BOND_DBG_0 0x1df9 #define RTL8367C_REG_BOND_DBG_1 0x1dfa #define RTL8367C_REG_STRP_DBG_0 0x1dfb #define RTL8367C_REG_STRP_DBG_1 0x1dfc #define RTL8367C_REG_STRP_DBG_2 0x1dfd /* (16'h1f00)patch_reg */ #define RTL8367C_REG_INDRECT_ACCESS_CTRL 0x1f00 #define RTL8367C_RW_OFFSET 1 #define RTL8367C_RW_MASK 0x2 #define RTL8367C_CMD_OFFSET 0 #define RTL8367C_CMD_MASK 0x1 #define RTL8367C_REG_INDRECT_ACCESS_STATUS 0x1f01 #define RTL8367C_INDRECT_ACCESS_STATUS_OFFSET 2 #define RTL8367C_INDRECT_ACCESS_STATUS_MASK 0x7 #define RTL8367C_REG_INDRECT_ACCESS_ADDRESS 0x1f02 #define RTL8367C_REG_INDRECT_ACCESS_WRITE_DATA 0x1f03 #define RTL8367C_REG_INDRECT_ACCESS_READ_DATA 0x1f04 /* (16'h6200)fib_page */ #define RTL8367C_REG_FIB0_CFG00 0x6200 #define RTL8367C_FIB0_CFG00_CFG_FIB_RST_OFFSET 15 #define RTL8367C_FIB0_CFG00_CFG_FIB_RST_MASK 0x8000 #define RTL8367C_FIB0_CFG00_CFG_FIB_LPK_OFFSET 14 #define RTL8367C_FIB0_CFG00_CFG_FIB_LPK_MASK 0x4000 #define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_OFFSET 13 #define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_MASK 0x2000 #define RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_OFFSET 12 #define RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_MASK 0x1000 #define RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_OFFSET 11 #define RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_MASK 0x800 #define RTL8367C_FIB0_CFG00_CFG_FIB_ISO_OFFSET 10 #define RTL8367C_FIB0_CFG00_CFG_FIB_ISO_MASK 0x400 #define RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_OFFSET 9 #define RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_MASK 0x200 #define RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_OFFSET 8 #define RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_MASK 0x100 #define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_OFFSET 6 #define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_MASK 0x40 #define RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_OFFSET 5 #define RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_MASK 0x20 #define RTL8367C_REG_FIB0_CFG01 0x6201 #define RTL8367C_FIB0_CFG01_CAPBILITY_OFFSET 6 #define RTL8367C_FIB0_CFG01_CAPBILITY_MASK 0xFFC0 #define RTL8367C_FIB0_CFG01_AN_COMPLETE_OFFSET 5 #define RTL8367C_FIB0_CFG01_AN_COMPLETE_MASK 0x20 #define RTL8367C_FIB0_CFG01_R_FAULT_OFFSET 4 #define RTL8367C_FIB0_CFG01_R_FAULT_MASK 0x10 #define RTL8367C_FIB0_CFG01_NWAY_ABILITY_OFFSET 3 #define RTL8367C_FIB0_CFG01_NWAY_ABILITY_MASK 0x8 #define RTL8367C_FIB0_CFG01_LINK_STATUS_OFFSET 2 #define RTL8367C_FIB0_CFG01_LINK_STATUS_MASK 0x4 #define RTL8367C_FIB0_CFG01_JABBER_DETECT_OFFSET 1 #define RTL8367C_FIB0_CFG01_JABBER_DETECT_MASK 0x2 #define RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_OFFSET 0 #define RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_MASK 0x1 #define RTL8367C_REG_FIB0_CFG02 0x6202 #define RTL8367C_REG_FIB0_CFG03 0x6203 #define RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_OFFSET 10 #define RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_MASK 0xFC00 #define RTL8367C_FIB0_CFG03_MODEL_NO_OFFSET 4 #define RTL8367C_FIB0_CFG03_MODEL_NO_MASK 0x3F0 #define RTL8367C_FIB0_CFG03_REVISION_NO_OFFSET 0 #define RTL8367C_FIB0_CFG03_REVISION_NO_MASK 0xF #define RTL8367C_REG_FIB0_CFG04 0x6204 #define RTL8367C_REG_FIB0_CFG05 0x6205 #define RTL8367C_REG_FIB0_CFG06 0x6206 #define RTL8367C_FIB0_CFG06_FIB_NP_EN_OFFSET 2 #define RTL8367C_FIB0_CFG06_FIB_NP_EN_MASK 0x4 #define RTL8367C_FIB0_CFG06_RXPAGE_OFFSET 1 #define RTL8367C_FIB0_CFG06_RXPAGE_MASK 0x2 #define RTL8367C_REG_FIB0_CFG07 0x6207 #define RTL8367C_REG_FIB0_CFG08 0x6208 #define RTL8367C_REG_FIB0_CFG09 0x6209 #define RTL8367C_REG_FIB0_CFG10 0x620a #define RTL8367C_REG_FIB0_CFG11 0x620b #define RTL8367C_REG_FIB0_CFG12 0x620c #define RTL8367C_REG_FIB0_CFG13 0x620d #define RTL8367C_FIB0_CFG13_INDR_FUNC_OFFSET 14 #define RTL8367C_FIB0_CFG13_INDR_FUNC_MASK 0xC000 #define RTL8367C_FIB0_CFG13_DUMMY_OFFSET 5 #define RTL8367C_FIB0_CFG13_DUMMY_MASK 0x3FE0 #define RTL8367C_FIB0_CFG13_INDR_DEVAD_OFFSET 0 #define RTL8367C_FIB0_CFG13_INDR_DEVAD_MASK 0x1F #define RTL8367C_REG_FIB0_CFG14 0x620e #define RTL8367C_REG_FIB0_CFG15 0x620f #define RTL8367C_REG_FIB1_CFG00 0x6210 #define RTL8367C_FIB1_CFG00_CFG_FIB_RST_OFFSET 15 #define RTL8367C_FIB1_CFG00_CFG_FIB_RST_MASK 0x8000 #define RTL8367C_FIB1_CFG00_CFG_FIB_LPK_OFFSET 14 #define RTL8367C_FIB1_CFG00_CFG_FIB_LPK_MASK 0x4000 #define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_OFFSET 13 #define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_MASK 0x2000 #define RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_OFFSET 12 #define RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_MASK 0x1000 #define RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_OFFSET 11 #define RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_MASK 0x800 #define RTL8367C_FIB1_CFG00_CFG_FIB_ISO_OFFSET 10 #define RTL8367C_FIB1_CFG00_CFG_FIB_ISO_MASK 0x400 #define RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_OFFSET 9 #define RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_MASK 0x200 #define RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_OFFSET 8 #define RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_MASK 0x100 #define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_OFFSET 6 #define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_MASK 0x40 #define RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_OFFSET 5 #define RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_MASK 0x20 #define RTL8367C_REG_FIB1_CFG01 0x6211 #define RTL8367C_FIB1_CFG01_CAPBILITY_OFFSET 6 #define RTL8367C_FIB1_CFG01_CAPBILITY_MASK 0xFFC0 #define RTL8367C_FIB1_CFG01_AN_COMPLETE_OFFSET 5 #define RTL8367C_FIB1_CFG01_AN_COMPLETE_MASK 0x20 #define RTL8367C_FIB1_CFG01_R_FAULT_OFFSET 4 #define RTL8367C_FIB1_CFG01_R_FAULT_MASK 0x10 #define RTL8367C_FIB1_CFG01_NWAY_ABILITY_OFFSET 3 #define RTL8367C_FIB1_CFG01_NWAY_ABILITY_MASK 0x8 #define RTL8367C_FIB1_CFG01_LINK_STATUS_OFFSET 2 #define RTL8367C_FIB1_CFG01_LINK_STATUS_MASK 0x4 #define RTL8367C_FIB1_CFG01_JABBER_DETECT_OFFSET 1 #define RTL8367C_FIB1_CFG01_JABBER_DETECT_MASK 0x2 #define RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_OFFSET 0 #define RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_MASK 0x1 #define RTL8367C_REG_FIB1_CFG02 0x6212 #define RTL8367C_REG_FIB1_CFG03 0x6213 #define RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_OFFSET 10 #define RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_MASK 0xFC00 #define RTL8367C_FIB1_CFG03_MODEL_NO_OFFSET 4 #define RTL8367C_FIB1_CFG03_MODEL_NO_MASK 0x3F0 #define RTL8367C_FIB1_CFG03_REVISION_NO_OFFSET 0 #define RTL8367C_FIB1_CFG03_REVISION_NO_MASK 0xF #define RTL8367C_REG_FIB1_CFG04 0x6214 #define RTL8367C_REG_FIB1_CFG05 0x6215 #define RTL8367C_REG_FIB1_CFG06 0x6216 #define RTL8367C_FIB1_CFG06_FIB_NP_EN_OFFSET 2 #define RTL8367C_FIB1_CFG06_FIB_NP_EN_MASK 0x4 #define RTL8367C_FIB1_CFG06_RXPAGE_OFFSET 1 #define RTL8367C_FIB1_CFG06_RXPAGE_MASK 0x2 #define RTL8367C_REG_FIB1_CFG07 0x6217 #define RTL8367C_REG_FIB1_CFG08 0x6218 #define RTL8367C_REG_FIB1_CFG09 0x6219 #define RTL8367C_REG_FIB1_CFG10 0x621a #define RTL8367C_REG_FIB1_CFG11 0x621b #define RTL8367C_REG_FIB1_CFG12 0x621c #define RTL8367C_REG_FIB1_CFG13 0x621d #define RTL8367C_FIB1_CFG13_INDR_FUNC_OFFSET 14 #define RTL8367C_FIB1_CFG13_INDR_FUNC_MASK 0xC000 #define RTL8367C_FIB1_CFG13_DUMMY_OFFSET 5 #define RTL8367C_FIB1_CFG13_DUMMY_MASK 0x3FE0 #define RTL8367C_FIB1_CFG13_INDR_DEVAD_OFFSET 0 #define RTL8367C_FIB1_CFG13_INDR_DEVAD_MASK 0x1F #define RTL8367C_REG_FIB1_CFG14 0x621e #define RTL8367C_REG_FIB1_CFG15 0x621f /* (16'h6400)timer_1588 */ #define RTL8367C_REG_PTP_TIME_NSEC_L_NSEC 0x6400 #define RTL8367C_REG_PTP_TIME_NSEC_H_NSEC 0x6401 #define RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET 15 #define RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK 0x8000 #define RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET 12 #define RTL8367C_PTP_TIME_NSEC_H_CMD_MASK 0x3000 #define RTL8367C_PTP_TIME_NSEC_H_NSEC_OFFSET 0 #define RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK 0x7FF #define RTL8367C_REG_PTP_TIME_SEC_L_SEC 0x6402 #define RTL8367C_REG_PTP_TIME_SEC_H_SEC 0x6403 #define RTL8367C_REG_PTP_TIME_CFG 0x6404 #define RTL8367C_CFG_TIMER_EN_FRC_OFFSET 2 #define RTL8367C_CFG_TIMER_EN_FRC_MASK 0x4 #define RTL8367C_CFG_TIMER_1588_EN_OFFSET 1 #define RTL8367C_CFG_TIMER_1588_EN_MASK 0x2 #define RTL8367C_CFG_CLK_SRC_OFFSET 0 #define RTL8367C_CFG_CLK_SRC_MASK 0x1 #define RTL8367C_REG_OTAG_TPID 0x6405 #define RTL8367C_REG_ITAG_TPID 0x6406 #define RTL8367C_REG_MAC_ADDR_L 0x6407 #define RTL8367C_REG_MAC_ADDR_M 0x6408 #define RTL8367C_REG_MAC_ADDR_H 0x6409 #define RTL8367C_REG_PTP_TIME_NSEC_L_NSEC_RD 0x640a #define RTL8367C_REG_PTP_TIME_NSEC_H_NSEC_RD 0x640b #define RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_OFFSET 0 #define RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_MASK 0x7FF #define RTL8367C_REG_PTP_TIME_SEC_L_SEC_RD 0x640c #define RTL8367C_REG_PTP_TIME_SEC_H_SEC_RD 0x640d #define RTL8367C_REG_PTP_TIME_CFG2 0x640e #define RTL8367C_CFG_EN_OFFLOAD_OFFSET 9 #define RTL8367C_CFG_EN_OFFLOAD_MASK 0x200 #define RTL8367C_CFG_SAVE_OFF_TS_OFFSET 8 #define RTL8367C_CFG_SAVE_OFF_TS_MASK 0x100 #define RTL8367C_CFG_IMR_OFFSET 0 #define RTL8367C_CFG_IMR_MASK 0xFF #define RTL8367C_REG_PTP_INTERRUPT_CFG 0x640f #define RTL8367C_P9_INTERRUPT_OFFSET 9 #define RTL8367C_P9_INTERRUPT_MASK 0x200 #define RTL8367C_P8_INTERRUPT_OFFSET 8 #define RTL8367C_P8_INTERRUPT_MASK 0x100 #define RTL8367C_P7_INTERRUPT_OFFSET 7 #define RTL8367C_P7_INTERRUPT_MASK 0x80 #define RTL8367C_P6_INTERRUPT_OFFSET 6 #define RTL8367C_P6_INTERRUPT_MASK 0x40 #define RTL8367C_P5_INTERRUPT_OFFSET 5 #define RTL8367C_P5_INTERRUPT_MASK 0x20 #define RTL8367C_P4_INTERRUPT_OFFSET 4 #define RTL8367C_P4_INTERRUPT_MASK 0x10 #define RTL8367C_P3_INTERRUPT_OFFSET 3 #define RTL8367C_P3_INTERRUPT_MASK 0x8 #define RTL8367C_P2_INTERRUPT_OFFSET 2 #define RTL8367C_P2_INTERRUPT_MASK 0x4 #define RTL8367C_P1_INTERRUPT_OFFSET 1 #define RTL8367C_P1_INTERRUPT_MASK 0x2 #define RTL8367C_P0_INTERRUPT_OFFSET 0 #define RTL8367C_P0_INTERRUPT_MASK 0x1 #define RTL8367C_REG_P0_TX_SYNC_SEQ_ID 0x6410 #define RTL8367C_REG_P0_TX_DELAY_REQ_SEQ_ID 0x6411 #define RTL8367C_REG_P0_TX_PDELAY_REQ_SEQ_ID 0x6412 #define RTL8367C_REG_P0_TX_PDELAY_RESP_SEQ_ID 0x6413 #define RTL8367C_REG_P0_RX_SYNC_SEQ_ID 0x6414 #define RTL8367C_REG_P0_RX_DELAY_REQ_SEQ_ID 0x6415 #define RTL8367C_REG_P0_RX_PDELAY_REQ_SEQ_ID 0x6416 #define RTL8367C_REG_P0_RX_PDELAY_RESP_SEQ_ID 0x6417 #define RTL8367C_REG_P0_PORT_NSEC_15_0 0x6418 #define RTL8367C_REG_P0_PORT_NSEC_26_16 0x6419 #define RTL8367C_P0_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P0_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P0_PORT_SEC_15_0 0x641a #define RTL8367C_REG_P0_PORT_SEC_31_16 0x641b #define RTL8367C_REG_P0_EAV_CFG 0x641c #define RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P0_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P0_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P0_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P0_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P1_TX_SYNC_SEQ_ID 0x6420 #define RTL8367C_REG_P1_TX_DELAY_REQ_SEQ_ID 0x6421 #define RTL8367C_REG_P1_TX_PDELAY_REQ_SEQ_ID 0x6422 #define RTL8367C_REG_P1_TX_PDELAY_RESP_SEQ_ID 0x6423 #define RTL8367C_REG_P1_RX_SYNC_SEQ_ID 0x6424 #define RTL8367C_REG_P1_RX_DELAY_REQ_SEQ_ID 0x6425 #define RTL8367C_REG_P1_RX_PDELAY_REQ_SEQ_ID 0x6426 #define RTL8367C_REG_P1_RX_PDELAY_RESP_SEQ_ID 0x6427 #define RTL8367C_REG_P1_PORT_NSEC_15_0 0x6428 #define RTL8367C_REG_P1_PORT_NSEC_26_16 0x6429 #define RTL8367C_P1_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P1_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P1_PORT_SEC_15_0 0x642a #define RTL8367C_REG_P1_PORT_SEC_31_16 0x642b #define RTL8367C_REG_P1_EAV_CFG 0x642c #define RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P1_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P1_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P1_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P1_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P2_TX_SYNC_SEQ_ID 0x6430 #define RTL8367C_REG_P2_TX_DELAY_REQ_SEQ_ID 0x6431 #define RTL8367C_REG_P2_TX_PDELAY_REQ_SEQ_ID 0x6432 #define RTL8367C_REG_P2_TX_PDELAY_RESP_SEQ_ID 0x6433 #define RTL8367C_REG_P2_RX_SYNC_SEQ_ID 0x6434 #define RTL8367C_REG_P2_RX_DELAY_REQ_SEQ_ID 0x6435 #define RTL8367C_REG_P2_RX_PDELAY_REQ_SEQ_ID 0x6436 #define RTL8367C_REG_P2_RX_PDELAY_RESP_SEQ_ID 0x6437 #define RTL8367C_REG_P2_PORT_NSEC_15_0 0x6438 #define RTL8367C_REG_P2_PORT_NSEC_26_16 0x6439 #define RTL8367C_P2_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P2_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P2_PORT_SEC_15_0 0x643a #define RTL8367C_REG_P2_PORT_SEC_31_16 0x643b #define RTL8367C_REG_P2_EAV_CFG 0x643c #define RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P2_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P2_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P2_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P2_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P3_TX_SYNC_SEQ_ID 0x6440 #define RTL8367C_REG_P3_TX_DELAY_REQ_SEQ_ID 0x6441 #define RTL8367C_REG_P3_TX_PDELAY_REQ_SEQ_ID 0x6442 #define RTL8367C_REG_P3_TX_PDELAY_RESP_SEQ_ID 0x6443 #define RTL8367C_REG_P3_RX_SYNC_SEQ_ID 0x6444 #define RTL8367C_REG_P3_RX_DELAY_REQ_SEQ_ID 0x6445 #define RTL8367C_REG_P3_RX_PDELAY_REQ_SEQ_ID 0x6446 #define RTL8367C_REG_P3_RX_PDELAY_RESP_SEQ_ID 0x6447 #define RTL8367C_REG_P3_PORT_NSEC_15_0 0x6448 #define RTL8367C_REG_P3_PORT_NSEC_26_16 0x6449 #define RTL8367C_P3_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P3_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P3_PORT_SEC_15_0 0x644a #define RTL8367C_REG_P3_PORT_SEC_31_16 0x644b #define RTL8367C_REG_P3_EAV_CFG 0x644c #define RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P3_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P3_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P3_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P3_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P4_TX_SYNC_SEQ_ID 0x6450 #define RTL8367C_REG_P4_TX_DELAY_REQ_SEQ_ID 0x6451 #define RTL8367C_REG_P4_TX_PDELAY_REQ_SEQ_ID 0x6452 #define RTL8367C_REG_P4_TX_PDELAY_RESP_SEQ_ID 0x6453 #define RTL8367C_REG_P4_RX_SYNC_SEQ_ID 0x6454 #define RTL8367C_REG_P4_RX_DELAY_REQ_SEQ_ID 0x6455 #define RTL8367C_REG_P4_RX_PDELAY_REQ_SEQ_ID 0x6456 #define RTL8367C_REG_P4_RX_PDELAY_RESP_SEQ_ID 0x6457 #define RTL8367C_REG_P4_PORT_NSEC_15_0 0x6458 #define RTL8367C_REG_P4_PORT_NSEC_26_16 0x6459 #define RTL8367C_P4_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P4_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P4_PORT_SEC_15_0 0x645a #define RTL8367C_REG_P4_PORT_SEC_31_16 0x645b #define RTL8367C_REG_P4_EAV_CFG 0x645c #define RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P4_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P4_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P4_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P4_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P6_TX_SYNC_SEQ_ID 0x6460 #define RTL8367C_REG_P6_TX_DELAY_REQ_SEQ_ID 0x6461 #define RTL8367C_REG_P6_TX_PDELAY_REQ_SEQ_ID 0x6462 #define RTL8367C_REG_P6_TX_PDELAY_RESP_SEQ_ID 0x6463 #define RTL8367C_REG_P6_RX_SYNC_SEQ_ID 0x6464 #define RTL8367C_REG_P6_RX_DELAY_REQ_SEQ_ID 0x6465 #define RTL8367C_REG_P6_RX_PDELAY_REQ_SEQ_ID 0x6466 #define RTL8367C_REG_P6_RX_PDELAY_RESP_SEQ_ID 0x6467 #define RTL8367C_REG_P6_PORT_NSEC_15_0 0x6468 #define RTL8367C_REG_P6_PORT_NSEC_26_16 0x6469 #define RTL8367C_P6_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P6_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P6_PORT_SEC_15_0 0x646a #define RTL8367C_REG_P6_PORT_SEC_31_16 0x646b #define RTL8367C_REG_P6_EAV_CFG 0x646c #define RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P6_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P6_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P6_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P6_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P7_TX_SYNC_SEQ_ID 0x6470 #define RTL8367C_REG_P7_TX_DELAY_REQ_SEQ_ID 0x6471 #define RTL8367C_REG_P7_TX_PDELAY_REQ_SEQ_ID 0x6472 #define RTL8367C_REG_P7_TX_PDELAY_RESP_SEQ_ID 0x6473 #define RTL8367C_REG_P7_RX_SYNC_SEQ_ID 0x6474 #define RTL8367C_REG_P7_RX_DELAY_REQ_SEQ_ID 0x6475 #define RTL8367C_REG_P7_RX_PDELAY_REQ_SEQ_ID 0x6476 #define RTL8367C_REG_P7_RX_PDELAY_RESP_SEQ_ID 0x6477 #define RTL8367C_REG_P7_PORT_NSEC_15_0 0x6478 #define RTL8367C_REG_P7_PORT_NSEC_26_16 0x6479 #define RTL8367C_P7_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P7_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P7_PORT_SEC_15_0 0x647a #define RTL8367C_REG_P7_PORT_SEC_31_16 0x647b #define RTL8367C_REG_P7_EAV_CFG 0x647c #define RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P7_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P7_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P7_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P7_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P5_TX_SYNC_SEQ_ID 0x6480 #define RTL8367C_REG_P5_TX_DELAY_REQ_SEQ_ID 0x6481 #define RTL8367C_REG_P5_TX_PDELAY_REQ_SEQ_ID 0x6482 #define RTL8367C_REG_P5_TX_PDELAY_RESP_SEQ_ID 0x6483 #define RTL8367C_REG_P5_RX_SYNC_SEQ_ID 0x6484 #define RTL8367C_REG_P5_RX_DELAY_REQ_SEQ_ID 0x6485 #define RTL8367C_REG_P5_RX_PDELAY_REQ_SEQ_ID 0x6486 #define RTL8367C_REG_P5_RX_PDELAY_RESP_SEQ_ID 0x6487 #define RTL8367C_REG_P5_PORT_NSEC_15_0 0x6488 #define RTL8367C_REG_P5_PORT_NSEC_26_16 0x6489 #define RTL8367C_P5_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P5_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P5_PORT_SEC_15_0 0x648a #define RTL8367C_REG_P5_PORT_SEC_31_16 0x648b #define RTL8367C_REG_P5_EAV_CFG 0x648c #define RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P5_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P5_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P5_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P5_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P8_TX_SYNC_SEQ_ID 0x6490 #define RTL8367C_REG_P8_TX_DELAY_REQ_SEQ_ID 0x6491 #define RTL8367C_REG_P8_TX_PDELAY_REQ_SEQ_ID 0x6492 #define RTL8367C_REG_P8_TX_PDELAY_RESP_SEQ_ID 0x6493 #define RTL8367C_REG_P8_RX_SYNC_SEQ_ID 0x6494 #define RTL8367C_REG_P8_RX_DELAY_REQ_SEQ_ID 0x6495 #define RTL8367C_REG_P8_RX_PDELAY_REQ_SEQ_ID 0x6496 #define RTL8367C_REG_P8_RX_PDELAY_RESP_SEQ_ID 0x6497 #define RTL8367C_REG_P8_PORT_NSEC_15_0 0x6498 #define RTL8367C_REG_P8_PORT_NSEC_26_16 0x6499 #define RTL8367C_P8_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P8_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P8_PORT_SEC_15_0 0x649a #define RTL8367C_REG_P8_PORT_SEC_31_16 0x649b #define RTL8367C_REG_P8_EAV_CFG 0x649c #define RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P8_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P8_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P8_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P8_EAV_CFG_TX_SYNC_MASK 0x1 #define RTL8367C_REG_P9_TX_SYNC_SEQ_ID 0x64a0 #define RTL8367C_REG_P9_TX_DELAY_REQ_SEQ_ID 0x64a1 #define RTL8367C_REG_P9_TX_PDELAY_REQ_SEQ_ID 0x64a2 #define RTL8367C_REG_P9_TX_PDELAY_RESP_SEQ_ID 0x64a3 #define RTL8367C_REG_P9_RX_SYNC_SEQ_ID 0x64a4 #define RTL8367C_REG_P9_RX_DELAY_REQ_SEQ_ID 0x64a5 #define RTL8367C_REG_P9_RX_PDELAY_REQ_SEQ_ID 0x64a6 #define RTL8367C_REG_P9_RX_PDELAY_RESP_SEQ_ID 0x64a7 #define RTL8367C_REG_P9_PORT_NSEC_15_0 0x64a8 #define RTL8367C_REG_P9_PORT_NSEC_26_16 0x64a9 #define RTL8367C_P9_PORT_NSEC_26_16_OFFSET 0 #define RTL8367C_P9_PORT_NSEC_26_16_MASK 0x7FF #define RTL8367C_REG_P9_PORT_SEC_15_0 0x64aa #define RTL8367C_REG_P9_PORT_SEC_31_16 0x64ab #define RTL8367C_REG_P9_EAV_CFG 0x64ac #define RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 #define RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 #define RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 #define RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 #define RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 #define RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 #define RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_OFFSET 5 #define RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_MASK 0x20 #define RTL8367C_P9_EAV_CFG_RX_SYNC_OFFSET 4 #define RTL8367C_P9_EAV_CFG_RX_SYNC_MASK 0x10 #define RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 #define RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 #define RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 #define RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 #define RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_OFFSET 1 #define RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_MASK 0x2 #define RTL8367C_P9_EAV_CFG_TX_SYNC_OFFSET 0 #define RTL8367C_P9_EAV_CFG_TX_SYNC_MASK 0x1 /* (16'h6600)sds_indacs_reg */ #define RTL8367C_REG_SDS_INDACS_CMD 0x6600 #define RTL8367C_SDS_CMD_BUSY_OFFSET 8 #define RTL8367C_SDS_CMD_BUSY_MASK 0x100 #define RTL8367C_SDS_CMD_OFFSET 7 #define RTL8367C_SDS_CMD_MASK 0x80 #define RTL8367C_SDS_RWOP_OFFSET 6 #define RTL8367C_SDS_RWOP_MASK 0x40 #define RTL8367C_SDS_INDEX_OFFSET 0 #define RTL8367C_SDS_INDEX_MASK 0x3F #define RTL8367C_REG_SDS_INDACS_ADR 0x6601 #define RTL8367C_SDS_PAGE_OFFSET 5 #define RTL8367C_SDS_PAGE_MASK 0x7E0 #define RTL8367C_SDS_REGAD_OFFSET 0 #define RTL8367C_SDS_REGAD_MASK 0x1F #define RTL8367C_REG_SDS_INDACS_DATA 0x6602 #endif /*#ifndef _RTL8367C_REG_H_*/