Lines Matching refs:__uint32_t
240 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
243 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
246 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
247 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
277 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
280 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
283 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
284 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
324 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
327 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
330 __uint32_t fpu_mxcsr; /* MXCSR Register state */
331 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
361 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
364 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
367 __uint32_t fpu_mxcsr; /* MXCSR Register state */
368 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
406 __uint32_t __err;
407 __uint32_t __faultvaddr;
415 __uint32_t err;
416 __uint32_t faultvaddr;
519 __uint32_t __fpu_ip; /* offset */
525 __uint32_t __fpu_dp; /* offset */
529 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
530 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
570 __uint32_t __fpu_ip; /* offset */
576 __uint32_t __fpu_dp; /* offset */
580 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
581 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
639 __uint32_t fpu_ip; /* offset */
645 __uint32_t fpu_dp; /* offset */
649 __uint32_t fpu_mxcsr; /* MXCSR Register state */
650 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
690 __uint32_t fpu_ip; /* offset */
696 __uint32_t fpu_dp; /* offset */
700 __uint32_t fpu_mxcsr; /* MXCSR Register state */
701 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
755 __uint32_t __err;
764 __uint32_t err;