Lines Matching refs:dsi
6 * driver from drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c and the
245 static inline void dsi_write(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 val)
247 writel(val, dsi->base + reg);
250 static inline u32 dsi_read(struct dw_rockchip_dsi_priv *dsi, u32 reg)
252 return readl(dsi->base + reg);
255 static inline void dsi_set(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 mask)
257 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
260 static inline void dsi_clear(struct dw_rockchip_dsi_priv *dsi, u32 reg, u32 mask)
262 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
265 static inline void dsi_update_bits(struct dw_rockchip_dsi_priv *dsi, u32 reg,
268 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
271 static void dw_mipi_dsi_phy_write(struct dw_rockchip_dsi_priv *dsi,
280 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
282 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
285 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
287 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
290 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
357 static inline unsigned int ns2bc(struct dw_rockchip_dsi_priv *dsi, int ns)
359 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
365 static inline unsigned int ns2ui(struct dw_rockchip_dsi_priv *dsi, int ns)
367 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
374 struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
377 if (generic_phy_valid(&dsi->phy)) {
378 ret = generic_phy_configure(&dsi->phy, &dsi->phy_opts);
380 dev_err(dsi->dsi_host,
386 ret = generic_phy_power_on(&dsi->phy);
388 dev_err(dsi->dsi_host,
408 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
410 i = max_mbps_to_parameter(dsi->lane_mbps);
412 dev_err(dsi->dsi_host,
414 dsi->lane_mbps);
418 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
424 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
426 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
430 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
433 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
434 INPUT_DIVIDER(dsi->input_div));
435 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
436 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
444 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
446 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
447 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
449 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
452 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
454 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
457 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
461 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
464 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
469 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
470 TLP_PROGRAM_EN | ns2bc(dsi, 500));
471 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
472 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
473 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
474 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
475 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
476 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
477 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
478 BIT(5) | ns2bc(dsi, 100));
479 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
480 BIT(5) | (ns2bc(dsi, 60) + 7));
482 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
483 TLP_PROGRAM_EN | ns2bc(dsi, 500));
484 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
485 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
486 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
487 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
488 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
489 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
490 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
491 BIT(5) | ns2bc(dsi, 100));
500 struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
502 dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
505 if (!dsi)
512 * stm32 dsi driver and is unknown if necessary for Rockchip.
516 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
518 dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
527 struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
541 dev_err(dsi->dsi_host,
554 dev_err(dsi->dsi_host,
559 if (generic_phy_valid(&dsi->phy)) {
562 &dsi->phy_opts);
563 dsi->lane_mbps = target_mbps;
564 *lane_mbps = dsi->lane_mbps;
569 fin = clk_get_rate(dsi->ref);
612 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
613 *lane_mbps = dsi->lane_mbps;
614 dsi->input_div = best_prediv;
615 dsi->feedback_div = best_fbdiv;
617 dev_err(dsi->dsi_host, "Can not find best_freq for DPHY\n");
743 dev_err(dev, "No video dsi host detected %d\n", ret);
750 dev_err(dev, "failed to initialize mipi dsi host\n");
775 dev_err(dev, "failed to enable mipi dsi host\n");
782 static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi)
784 if (dsi->cdata->lanecfg1_grf_reg)
785 rk_setreg(dsi->grf + dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1);
787 if (dsi->cdata->lanecfg2_grf_reg)
788 rk_setreg(dsi->grf + dsi->cdata->lanecfg2_grf_reg, dsi->cdata->lanecfg2);
790 if (dsi->cdata->enable_grf_reg)
791 rk_setreg(dsi->grf + dsi->cdata->enable_grf_reg, dsi->cdata->enable);
820 dev_err(dev, "dsi dt register address error\n");
837 dev_err(dev, "no dsi-config for %s node\n", dev->name);
897 dev_err(dev, "missing dsi hardware reset %d\n", ret);
983 { .compatible = "rockchip,rk3399-mipi-dsi",
986 { .compatible = "rockchip,rk3568-mipi-dsi",
993 .name = "dw-mipi-dsi-rockchip",