drivers/video/logicore_dp_tx.c

186  * @dpcd_rx_caps:           RX device's status registers, see below
187  * @lane_status_ajd_reqs:   Lane status and adjustment requests information for
192  * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
193  * bytes correspond to the lane status associated with clock recovery, channel
253  * status.
262 		int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
264 		if (status)
276  * @mask: Bit mask specifying which bit in the status register should be waited
310 	int status;
315 		status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
321 	} while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
340 		int status = get_reg(dev, REG_REPLY_STATUS);
343 		if (status & REPLY_STATUS_REPLY_ERROR_MASK)
347 		if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
348 		    !(status &
350 		    !(status &
379 	int status;
385 		status = get_reg(dev, REG_REPLY_STATUS);
391 	} while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
392 		 (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
413 	status = aux_wait_reply(dev);
414 	if (status)
419 	status = get_reg(dev, REG_AUX_REPLY_CODE);
420 	if (status == AUX_REPLY_CODE_DEFER ||
421 	    status == AUX_REPLY_CODE_I2C_DEFER) {
424 	} else if ((status == AUX_REPLY_CODE_NACK) ||
425 		   (status == AUX_REPLY_CODE_I2C_NACK)) {
438 			status = get_reg(dev, REG_REPLY_DATA_COUNT);
444 		} while (status != request->num_bytes);
473 		int status = aux_wait_ready(dev);
475 		if (status) {
481 		status = aux_request_send(dev, request);
482 		if (status == -EAGAIN) {
485 		} else if (status == -ETIMEDOUT) {
493 			return status;
532 		int status;
562 		status = aux_request(dev, &request);
563 		if (status)
564 			return status;
587 	int status;
593 	status = aux_common(dev, AUX_CMD_READ, dpcd_address,
596 	return status;
616 	int status;
622 	status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
625 	return status;
746 	int status;
753 	status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
755 	if (status)
849 	int status;
865 	status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
866 	if (status)
874 	status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
875 	if (status)
894 	int status;
908 	status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
909 	if (status)
914 	status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
915 	if (status)
934 	int status;
951 	status = wait_phy_ready(dev, mask);
952 	if (status)
971 	int status;
977 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
981 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
985 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
990 	if (status)
999 	status = aux_write(dev, DPCD_LINK_BW_SET, 1,
1001 	if (status)
1095 	int status;
1162 	status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
1163 	if (status)
1170  * get_lane_status_adj_reqs() - Read lane status and adjustment requests
1175  * the status registers will be stored for later use by check_clock_recovery,
1178  * Return: 0 if the status information were read successfully, -ve on error
1183 	int status;
1186 	 * Read and store 4 bytes of lane status and 2 bytes of adjustment
1189 	status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
1191 	if (status)
1323 	int status;
1358 		status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
1360 		status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
1361 	if (status)
1399 	int status;
1417 	status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
1418 	if (status)
1426 		status = get_lane_status_adj_reqs(dev);
1427 		if (status)
1434 		status = check_clock_recovery(dev,
1436 		if (!status)
1457 		status = adj_vswing_preemp(dev);
1458 		if (status)
1499 	int status;
1514 		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
1516 		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
1518 	if (status)
1526 		status = get_lane_status_adj_reqs(dev);
1527 		if (status)
1532 		status = check_clock_recovery(dev,
1534 		if (status)
1541 		status =
1544 		if (!status)
1548 		status = adj_vswing_preemp(dev);
1549 		if (status)
1578 	int status;
1582 		status = set_link_rate(dev, LINK_BW_SET_270GBPS);
1583 		if (status) {
1584 			status = TS_FAILURE;
1587 		status = TS_CLOCK_RECOVERY;
1590 		status = set_link_rate(dev, LINK_BW_SET_162GBPS);
1591 		if (status) {
1592 			status = TS_FAILURE;
1595 		status = TS_CLOCK_RECOVERY;
1602 		status = TS_ADJUST_LANE_COUNT;
1606 	return status;
1624 	int status;
1628 		status = set_lane_count(dev, LANE_COUNT_SET_2);
1629 		if (status) {
1630 			status = TS_FAILURE;
1634 		status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1635 		if (status) {
1636 			status = TS_FAILURE;
1639 		status = TS_CLOCK_RECOVERY;
1642 		status = set_lane_count(dev, LANE_COUNT_SET_1);
1643 		if (status) {
1644 			status = TS_FAILURE;
1648 		status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1649 		if (status) {
1650 			status = TS_FAILURE;
1653 		status = TS_CLOCK_RECOVERY;
1660 		status = TS_FAILURE;
1664 	return status;
1668  * check_link_status() - Check status of link
1676  * Return: 0 if the link status is OK, -ve if a error occurred during checking
1687 		int status;
1690 		status = get_lane_status_adj_reqs(dev);
1691 		if (status)
1730 	int status;
1765 			status = set_training_pattern(dev,
1767 			if (status)
1772 	/* Final status check. */
1773 	status = check_link_status(dev, dp_tx->link_config.lane_count);
1774 	if (status)
1794 	int status;
1803 	status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1804 	if (status)
1805 		return status;
1811 	status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
1812 	if (status)
1813 		return status;
1830 	int status;
1841 	status = wait_phy_ready(dev, mask);
1842 	if (status)
1846 	status = run_training(dev);
1850 	if (status || status2)