9  * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
263 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
265 	writel(val, dsi->base + reg);
268 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
270 	return readl(dsi->base + reg);
276 	struct dw_mipi_dsi *dsi = host_to_dsi(host);
278 	if (device->lanes > dsi->max_data_lanes) {
285 	dsi->channel = device->channel;
290 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
301 	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
302 	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
305 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
310 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
314 		dev_err(dsi->dsi_host.dev,
319 	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
322 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
326 		dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n");
333 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
345 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
349 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
354 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
358 			dev_err(dsi->dsi_host.dev,
366 	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
369 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
377 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
381 		dev_err(dsi->dsi_host.dev, "Timeout during read operation\n");
387 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
391 			dev_err(dsi->dsi_host.dev,
396 		val = dsi_read(dsi, DSI_GEN_PLD_DATA);
407 	struct dw_mipi_dsi *dsi = host_to_dsi(host);
417 	dw_mipi_message_config(dsi, msg);
419 	ret = dw_mipi_dsi_write(dsi, &packet);
424 		ret = dw_mipi_dsi_read(dsi, msg);
440 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
442 	struct mipi_dsi_device *device = dsi->device;
459 	dsi_write(dsi, DSI_VID_MODE_CFG, val);
462 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
465 	const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
467 	dsi_write(dsi, DSI_PWR_UP, RESET);
470 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
471 		dw_mipi_dsi_video_mode_config(dsi);
472 		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
474 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
478 		phy_ops->post_set_mode(dsi->device, mode_flags);
480 	dsi_write(dsi, DSI_PWR_UP, POWERUP);
483 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
485 	const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
494 		phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
505 	esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
507 	dsi_write(dsi, DSI_PWR_UP, RESET);
514 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
518 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
521 	struct mipi_dsi_device *device = dsi->device;
544 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
545 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
546 	dsi_write(dsi, DSI_DPI_CFG_POL, val);
553 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
557 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
559 	dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
562 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
572 	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
575 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
577 	const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
584 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
590 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
591 	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
594 		phy_ops->post_set_mode(dsi->device, 0);
598 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
604 	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
614 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
629 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
630 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
632 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
633 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
635 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
636 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
639 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
649 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
650 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
651 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
652 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
655 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
657 	const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
662 		phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
672 	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
675 		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
677 		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
679 		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
683 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
687 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
689 	struct mipi_dsi_device *device = dsi->device;
693 	 * stop wait time should be the maximum between host dsi
696 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
700 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
703 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
705 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
706 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
707 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
710 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
715 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
718 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
721 		dev_dbg(dsi->dsi_host.dev,
724 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
728 		dev_dbg(dsi->dsi_host.dev,
732 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
734 	dsi_read(dsi, DSI_INT_ST0);
735 	dsi_read(dsi, DSI_INT_ST1);
736 	dsi_write(dsi, DSI_INT_MSK0, 0);
737 	dsi_write(dsi, DSI_INT_MSK1, 0);
740 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
743 	const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
744 	struct mipi_dsi_device *device = dsi->device;
747 	ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
748 				     device->format, &dsi->lane_mbps);
750 		dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n");
752 	dw_mipi_dsi_init_pll(dsi);
753 	dw_mipi_dsi_dpi_config(dsi, timings);
754 	dw_mipi_dsi_packet_handler_config(dsi);
755 	dw_mipi_dsi_video_mode_config(dsi);
756 	dw_mipi_dsi_video_packet_config(dsi, timings);
757 	dw_mipi_dsi_command_mode_config(dsi);
758 	dw_mipi_dsi_line_timer_config(dsi, timings);
759 	dw_mipi_dsi_vertical_timing_config(dsi, timings);
761 	dw_mipi_dsi_dphy_init(dsi);
762 	dw_mipi_dsi_dphy_timing_config(dsi);
763 	dw_mipi_dsi_dphy_interface_config(dsi);
765 	dw_mipi_dsi_clear_err(dsi);
767 	ret = phy_ops->init(dsi->device);
769 		dev_warn(dsi->dsi_host.dev, "Phy init() failed\n");
771 	dw_mipi_dsi_dphy_enable(dsi);
776 	dw_mipi_dsi_set_mode(dsi, 0);
785 	struct dw_mipi_dsi *dsi = dev_get_priv(dev);
794 	dsi->phy_ops = phy_ops;
795 	dsi->max_data_lanes = max_data_lanes;
796 	dsi->device = device;
797 	dsi->dsi_host.dev = (struct device *)dev;
798 	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
799 	device->host = &dsi->dsi_host;
801 	dsi->base = dev_read_addr_ptr(device->dev);
802 	if (!dsi->base) {
803 		dev_err(device->dev, "dsi dt register address error\n");
812 		dw_mipi_dsi_bridge_set(dsi, timings);
825 	dw_mipi_dsi_bridge_set(dsi, timings);
832 	struct dw_mipi_dsi *dsi = dev_get_priv(dev);
835 	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
863 MODULE_ALIAS("platform:dw-mipi-dsi");

Indexes created Sat Sep 07 21:54:46 MDT 2024