Lines Matching defs:to
13 * names of its contributors may be used to endorse or promote products
124 * For an op to be DTR, cmd phase along with every other non-empty
125 * phase should have dtr field set to 1. If an op phase has zero
214 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
215 * SPI clock rate is less than or equal to the requested clock rate.
267 * CS0 to 4b'1110
268 * CS1 to 4b'1101
269 * CS2 to 4b'1011
270 * CS3 to 4b'0111
296 /* Convert to ns. */
299 /* Convert to ns. */
302 /* The controller adds additional delay to that programmed in the reg */
646 /* Convert to clock cycles. */
717 * Handle non-4-byte aligned access to avoid
852 * Use bounce buffer for non 32 bit aligned txbuf to avoid data
871 * Some delay is required for the above bit to be internally
932 u32 to = op->addr.val;
939 * But this controller does not support sending dummy address bytes to
945 if (!priv->dtr && priv->use_dac_mode && (to + len < priv->ahbsize)) {
946 memcpy_toio(priv->ahbbase + to, buf, len);