ram/rockchip/sdram_rk3188.c

38 	struct chan_info chan[1];
259 static void phy_cfg(const struct chan_info *chan, int channel,
262 	struct rk3288_ddr_publ *publ = chan->publ;
263 	struct rk3188_msch *msch = chan->msch;
380 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
383 	struct rk3288_ddr_pctl *pctl = chan->pctl;
384 	struct rk3288_ddr_publ *publ = chan->publ;
385 	struct rk3188_msch *msch = chan->msch;
418 static int data_training(const struct chan_info *chan, int channel,
426 	struct rk3288_ddr_publ *publ = chan->publ;
427 	struct rk3288_ddr_pctl *pctl = chan->pctl;
481 static void move_to_access_state(const struct chan_info *chan)
483 	struct rk3288_ddr_publ *publ = chan->publ;
484 	struct rk3288_ddr_pctl *pctl = chan->pctl;
522 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
525 	struct rk3288_ddr_publ *publ = chan->publ;
533 	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
539 	unsigned int chan;
544 	for (chan = 0; chan < sdram_params->num_channels; chan++) {
546 			&sdram_params->ch[chan];
548 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
549 		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
550 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
551 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
552 		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
553 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
554 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
555 		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
556 		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
558 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
573 	const struct chan_info *chan = &dram->chan[channel];
574 	struct rk3288_ddr_publ *publ = chan->publ;
578 	if (data_training(chan, channel, sdram_params) < 0) {
597 			set_bandwidth_ratio(chan, channel,
607 	    (data_training(chan, channel, sdram_params) < 0)) {
634 	const struct chan_info *chan = &dram->chan[channel];
635 	struct rk3288_ddr_pctl *pctl = chan->pctl;
636 	struct rk3288_ddr_publ *publ = chan->publ;
659 	writel(1, &chan->msch->ddrconf);
660 	move_to_access_state(chan);
733 		const struct chan_info *chan = &dram->chan[channel];
734 		struct rk3288_ddr_pctl *pctl = chan->pctl;
735 		struct rk3288_ddr_publ *publ = chan->publ;
744 		phy_cfg(chan, channel, sdram_params);
757 		set_bandwidth_ratio(chan, channel,
777 		writel(1, &chan->msch->ddrconf);
786 		writel(4, &chan->msch->ddrconf);
787 		move_to_access_state(chan);
900 	priv->chan[0].msch = regmap_get_range(map, 0);
904 	priv->chan[0].pctl = regmap_get_range(plat->map, 0);
905 	priv->chan[0].publ = regmap_get_range(plat->map, 1);