ram/rockchip/sdram_rk3066.c

38 	struct rk3066_dmc_chan_info chan[1];
246 static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel,
249 	struct rk3288_ddr_publ *publ = chan->publ;
250 	struct rk3188_msch *msch = chan->msch;
367 static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel,
370 	struct rk3288_ddr_pctl *pctl = chan->pctl;
371 	struct rk3288_ddr_publ *publ = chan->publ;
372 	struct rk3188_msch *msch = chan->msch;
403 static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel,
411 	struct rk3288_ddr_publ *publ = chan->publ;
412 	struct rk3288_ddr_pctl *pctl = chan->pctl;
466 static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan)
468 	struct rk3288_ddr_publ *publ = chan->publ;
469 	struct rk3288_ddr_pctl *pctl = chan->pctl;
507 static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum,
510 	struct rk3288_ddr_publ *publ = chan->publ;
518 	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
524 	unsigned int chan;
529 	for (chan = 0; chan < sdram_params->num_channels; chan++) {
531 				&sdram_params->ch[chan];
533 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
534 		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
535 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
536 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
537 		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
538 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
539 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
540 		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
541 		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
543 		rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
558 	const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
559 	struct rk3288_ddr_publ *publ = chan->publ;
563 	if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) {
582 			rk3066_dmc_set_bandwidth_ratio(chan, channel,
592 	    (rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) {
611 	const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
612 	struct rk3288_ddr_pctl *pctl = chan->pctl;
613 	struct rk3288_ddr_publ *publ = chan->publ;
636 	writel(1, &chan->msch->ddrconf);
637 	rk3066_dmc_move_to_access_state(chan);
703 		const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
704 		struct rk3288_ddr_pctl *pctl = chan->pctl;
705 		struct rk3288_ddr_publ *publ = chan->publ;
714 		rk3066_dmc_phy_cfg(chan, channel, sdram_params);
727 		rk3066_dmc_set_bandwidth_ratio(chan, channel,
747 		writel(1, &chan->msch->ddrconf);
758 		writel(4, &chan->msch->ddrconf);
759 		rk3066_dmc_move_to_access_state(chan);
833 		priv->chan[0].msch = regmap_get_range(map, 0);
836 		priv->chan[0].pctl = regmap_get_range(plat->map, 0);
837 		priv->chan[0].publ = regmap_get_range(plat->map, 1);