ram/octeon/octeon3_lmc.c

392 		 * reset both memory locations with the same pattern. Failing
712 				    int if_num, int dimm_count, int pattern,
727 				       pattern);
742 	 * same pattern into each of the 4 MPR locations in the DRAM, so
747 	 * clock-like pattern for OFFSET training, but does not want a
748 	 * clock pattern for Bit-Deskew.  You should then be able to call
750 	 * change the pattern to a new value.
753 	 * A correction: PHY doesn't need any pattern during offset
754 	 * training, but needs clock like pattern for internal vref and
757 	 * the pattern.  David
826 	 * 6) Write all 4 MPR registers with the desired pattern (have to
829 	 * MR_MPR_CTL.MR_WR_SEL=0, MR_MPR_CTL.MR_WR_ADDR[7:0]=pattern
7767 	 * using the DDR3 multipurpose register predefined pattern for system
7778 	 * the DDR3 multipurpose register predefined pattern for system
7781 	 * disables the predefined pattern via another DDR3 MR3 write
9942 	 * 3) Setup GENERAL_PURPOSE[0-2] registers with the data pattern
10120 // setup default for byte test pattern array
10164 	 * 3) Setup GENERAL_PURPOSE[0-2] registers with the data pattern
10193 	 * here data comes from the LFSR generating a PRBS pattern
10253 	int pattern;
10260 	for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) {
10262 			setup_lfsr_pattern(priv, lmc, lfsr_patterns[pattern]);
10264 			pattern_p = byte_patterns[pattern];
10270 		      __func__, pattern, phys_addr, errs);
10292 	int pattern;
10327 	// start of pattern loop
10328 	// we do the set of tests for each pattern supplied...
10331 	for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) {
10335 			pattern_p = byte_patterns[pattern];
10338 			setup_lfsr_pattern(priv, lmc, lfsr_patterns[pattern]);
10470 		// now choose the best byte_offsets for this pattern
10497 			// sum the pattern averages
10503 		      node, lmc, mode_str, pattern);
10508 	// end of pattern loop
10762  * first pattern example:
10842 	 * this will yield a clk/2 pattern:
10847 	 * here data comes from the LFSR generating a PRBS pattern