drivers/pci/pcie_mediatek.c

32 /* PCIe per port registers */
60 /* PCIe V2 per-port registers */
178 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
183 	err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val,
188 	if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
194 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
200 	       port->base + PCIE_CFG_HEADER0);
201 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
203 	       port->base + PCIE_CFG_HEADER2);
206 	tmp = readl(port->base + PCIE_APP_TLP_REQ);
208 	writel(tmp, port->base + PCIE_APP_TLP_REQ);
211 	if (mtk_pcie_check_cfg_cpld(port))
215 	*val = readl(port->base + PCIE_CFG_RDATA);
225 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
230 	       port->base + PCIE_CFG_HEADER0);
231 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
233 	       port->base + PCIE_CFG_HEADER2);
237 	writel(val, port->base + PCIE_CFG_WDATA);
240 	val = readl(port->base + PCIE_APP_TLP_REQ);
242 	writel(val, port->base + PCIE_APP_TLP_REQ);
245 	return mtk_pcie_check_cfg_cpld(port);
252 	struct mtk_pcie_port *port;
270 	list_for_each_entry(port, &pcie->ports, list) {
271 		if ((PCI_BUS(bdf) == 0) && (PCI_DEV(bdf) == port->slot))
272 			return port;
275 		    PCI_DEV(pplat->devfn) == port->slot)
276 			return port;
286 	struct mtk_pcie_port *port;
289 	port = mtk_pcie_find_port(bus, bdf);
290 	if (!port) {
295 	ret = mtk_pcie_hw_rd_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), valuep);
306 	struct mtk_pcie_port *port;
308 	port = mtk_pcie_find_port(bus, bdf);
309 	if (!port)
316 	return mtk_pcie_hw_wr_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), value);
324 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
326 	list_del(&port->list);
327 	free(port);
330 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
332 	struct mtk_pcie *pcie = port->pcie;
336 	/* assert port PERST_N */
337 	setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
338 	/* de-assert port PERST_N */
339 	clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
342 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
349 		     PCIE_PORT_INT_EN(port->slot));
353 	       port->base + PCIE_BAR0_SETUP);
356 	writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
359 	val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE;
365 	val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE;
373 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
375 	struct mtk_pcie *pcie = port->pcie;
384 		val |= PCIE_CSR_LTSSM_EN(port->slot) |
385 		       PCIE_CSR_ASPM_L1_EN(port->slot);
390 	writel(0, port->base + PCIE_RST_CTRL);
397 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
401 	val = readl(port->base + PCIE_RST_CTRL);
403 	writel(val, port->base + PCIE_RST_CTRL);
407 	writel(val, port->base + PCIE_RST_CTRL);
411 	writew(val, port->base + PCIE_CONF_VEND_ID);
414 	writew(val, port->base + PCIE_CONF_CLASS_ID);
417 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
428 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
431 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
435 	writel(val, port->base + PCIE_AXI_WINDOW0);
440 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
444 	err = clk_enable(&port->sys_ck);
448 	err = reset_assert(&port->reset);
452 	err = reset_deassert(&port->reset);
456 	err = generic_phy_init(&port->phy);
460 	err = generic_phy_power_on(&port->phy);
464 	if (!mtk_pcie_startup_port(port))
467 	pr_err("Port%d link down\n", port->slot);
469 	generic_phy_power_off(&port->phy);
471 	generic_phy_exit(&port->phy);
474 	clk_disable(&port->sys_ck);
476 	mtk_pcie_port_free(port);
479 static void mtk_pcie_enable_port_v2(struct mtk_pcie_port *port)
483 	err = clk_enable(&port->sys_ck);
489 	err = clk_enable(&port->ahb_ck);
495 	err = clk_enable(&port->aux_ck);
501 	err = clk_enable(&port->axi_ck);
507 	err = clk_enable(&port->obff_ck);
513 	err = clk_enable(&port->pipe_ck);
519 	err = mtk_pcie_startup_port_v2(port);
523 	pr_err("Port%d link down\n", port->slot);
525 	mtk_pcie_port_free(port);
531 	struct mtk_pcie_port *port;
535 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
536 	if (!port)
539 	snprintf(name, sizeof(name), "port%d", slot);
540 	port->base = dev_remap_addr_name(dev, name);
541 	if (!port->base)
545 	err = clk_get_by_name(dev, name, &port->sys_ck);
549 	err = reset_get_by_index(dev, slot, &port->reset);
553 	err = generic_phy_get_by_index(dev, slot, &port->phy);
557 	port->slot = slot;
558 	port->pcie = pcie;
560 	INIT_LIST_HEAD(&port->list);
561 	list_add_tail(&port->list, &pcie->ports);
569 	struct mtk_pcie_port *port;
573 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
574 	if (!port)
577 	snprintf(name, sizeof(name), "port%d", slot);
578 	port->base = dev_remap_addr_name(dev, name);
579 	if (!port->base) {
580 		debug("failed to map port%d base\n", slot);
585 	err = clk_get_by_name(dev, name, &port->sys_ck);
592 	err = clk_get_by_name(dev, name, &port->ahb_ck);
599 	err = clk_get_by_name(dev, name, &port->aux_ck);
606 	err = clk_get_by_name(dev, name, &port->axi_ck);
613 	err = clk_get_by_name(dev, name, &port->obff_ck);
620 	err = clk_get_by_name(dev, name, &port->pipe_ck);
626 	port->slot = slot;
627 	port->pcie = pcie;
629 	INIT_LIST_HEAD(&port->list);
630 	list_add_tail(&port->list, &pcie->ports);
638 	struct mtk_pcie_port *port, *tmp;
675 	/* enable each port, and then check link status */
676 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
677 		mtk_pcie_enable_port(port);
685 	struct mtk_pcie_port *port, *tmp;
713 	/* enable each port, and then check link status */
714 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
715 		mtk_pcie_enable_port_v2(port);