Lines Matching defs:port

41 #define CORE_PHY_DEFAULT_BASE(port)	(0x84000 + 0x4000 * (port))
211 struct apple_pcie_port *port)
217 rmw_set(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
219 rmw_set(PHY_LANE_CFG_REFCLK0REQ, port->phy + PHY_LANE_CFG);
221 res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
227 rmw_set(PHY_LANE_CFG_REFCLK1REQ, port->phy + PHY_LANE_CFG);
228 res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
236 rmw_clear(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
238 rmw_set(PHY_LANE_CFG_REFCLKEN, port->phy + PHY_LANE_CFG);
241 rmw_set(PORT_REFCLK_EN, port->base + pcie->hw->port_refclk);
248 struct apple_pcie_port *port;
259 port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL);
260 if (!port)
267 /* Use the first reg entry to work out the port index */
268 port->idx = idx >> 11;
269 port->pcie = pcie;
270 port->reset = reset;
271 port->np = np;
273 snprintf(name, sizeof(name), "port%d", port->idx);
276 addr = dev_read_addr_index(pcie->dev, port->idx + 2);
279 port->base = map_sysmem(addr, 0);
281 snprintf(name, sizeof(name), "phy%d", port->idx);
284 port->phy = pcie->base + CORE_PHY_DEFAULT_BASE(port->idx);
286 port->phy = map_sysmem(addr, 0);
288 rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
293 ret = apple_pcie_setup_refclk(pcie, port);
301 rmw_set(PORT_PERST_OFF, port->base + pcie->hw->port_perst);
307 ret = readl_poll_sleep_timeout(port->base + PORT_STATUS, stat,
310 dev_err(pcie->dev, "port %d ready wait timeout\n", port->idx);
314 list_add_tail(&port->entry, &pcie->ports);
316 writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
322 readl_poll_sleep_timeout(port->base + PORT_LINKSTS, stat,
326 rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK);
328 rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG);
329 rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK);
374 struct apple_pcie_port *port, *tmp;
376 list_for_each_entry_safe(port, tmp, &pcie->ports, entry) {
377 gpio_free_list_nodev(&port->reset, 1);
378 free(port);