Lines Matching defs:is
160 u32 is; /* 0xC: Interrupt status */
202 /* Wait till MDIO interface is ready to accept a new transaction. */
362 * and the external PHY is not obtained.
376 printf("axiemac: Warning, PCS/PMA PHY@%d is not ready, link is down\n",
496 * will be valid until this bit is valid.
497 * The bit is always a 1 for all other PHY interfaces.
502 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
525 writel(XAE_INT_RXRJECT_MASK, ®s->is);
568 /* Reset is done when the reset bit is low */
587 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
588 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
622 /* It is necessary to flush rxframe because if you don't do it
631 /* Rx BD is ready - start */
667 /* If size is less than min packet size, pad to min size */
734 * If Reception done interrupt is asserted, call RX call back function
755 /* Disable IRQ for a moment till packet is handled */
777 /* It is useful to clear buffer to be sure that it is consistent */
794 /* It is necessary to flush rxframe because if you don't do it
798 /* Rx BD is ready - start again */
834 /* RX channel offset is 0x30 */