Lines Matching refs:CTRL
1653 ctrl = E1000_READ_REG(hw, CTRL);
1655 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1766 reg_ctrl = E1000_READ_REG(hw, CTRL);
1770 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
2196 ctrl = E1000_READ_REG(hw, CTRL);
2214 * configure the two flow control enable bits in the CTRL register.
2263 E1000_WRITE_REG(hw, CTRL, ctrl);
2274 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2321 ctrl = E1000_READ_REG(hw, CTRL);
2329 E1000_WRITE_REG(hw, CTRL, ctrl);
2333 E1000_WRITE_REG(hw, CTRL, ctrl);
3508 ctrl = E1000_READ_REG(hw, CTRL);
3535 E1000_WRITE_REG(hw, CTRL, ctrl);
3558 ctrl = E1000_READ_REG(hw, CTRL);
3602 E1000_WRITE_REG(hw, CTRL, ctrl);
3849 ctrl = E1000_READ_REG(hw, CTRL);
3982 ctrl = E1000_READ_REG(hw, CTRL);
3984 E1000_WRITE_REG(hw, CTRL, ctrl);
4003 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4209 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4226 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4253 ctrl = E1000_READ_REG(hw, CTRL);
4269 E1000_WRITE_REG(hw, CTRL, ctrl);
4302 ctrl = E1000_READ_REG(hw, CTRL);
4308 E1000_WRITE_REG(hw, CTRL, ctrl);
4321 ctrl = E1000_READ_REG(hw, CTRL);
4596 ctrl = E1000_READ_REG(hw, CTRL);
4597 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4605 E1000_WRITE_REG(hw, CTRL, ctrl);